From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 14383 invoked by alias); 23 Apr 2019 02:08:48 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 14375 invoked by uid 89); 23 Apr 2019 02:08:47 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-20.6 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,KAM_NUMSUBJECT,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.1 spammy=HX-Languages-Length:1218, imagination X-HELO: mail-it1-f181.google.com Received: from mail-it1-f181.google.com (HELO mail-it1-f181.google.com) (209.85.166.181) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 23 Apr 2019 02:08:46 +0000 Received: by mail-it1-f181.google.com with SMTP id y10so21338451itc.1 for ; Mon, 22 Apr 2019 19:08:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=1xLO8Y+U9EylsTSacYfhwz8aln7j+d4IyMbv7Phe9RQ=; b=C/+Ef5zxJAL5QmBAXQVw/85a0mHpj5470qbnbrFwmKLXamGqhRB49PK5LXDO1DlHd0 EtPQbA4BPF3T77uhnM2bGflC7pT8ihnnyzaRvWecTeOtbr4DDvWBcWhOGS4LeVtvpNJm i+EOJrtLms/l+JgIpxxQJV08VuoZkXm/OI8GQYpZuoI84RdeK97DR4kdj1sTO6DhN89M RJSONpOBHoa3vEbb43VV7jGRUa2g13/hPSA9cFdkbLFNCqSHXjkzYDqK9L+2sDAAq7LL 63j8q2pEOWTKV1Gf8+vx1VHzY080c/DU1obSpn3dmO6NIemGtek0NgmJG9pA5NFYoPPO 2yaQ== MIME-Version: 1.0 References: <20190419210422.142060-1-fshahbazker@wavecomp.com> In-Reply-To: <20190419210422.142060-1-fshahbazker@wavecomp.com> From: Paul Hua Date: Tue, 23 Apr 2019 02:08:00 -0000 Message-ID: Subject: Re: [PATCH] [MIPS] Fix M5100 flags test with interAptiv-MR2 To: Faraz Shahbazker Cc: "binutils@sourceware.org" Content-Type: text/plain; charset="UTF-8" X-SW-Source: 2019-04/txt/msg00222.txt.bz2 ok. On Sat, Apr 20, 2019 at 5:03 AM Faraz Shahbazker wrote: > > From: Matthew Fortune > > ld/ > * testsuite/ld-mips-elf/mips-elf-flags.exp: Fix expected ASEs > for M5100. > --- > This failure is exposed by a previous assembler fix to apply ASE > information correctly for MIPS processors. > > ld/testsuite/ld-mips-elf/mips-elf-flags.exp | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/ld/testsuite/ld-mips-elf/mips-elf-flags.exp b/ld/testsuite/ld-mips-elf/mips-elf-flags.exp > index 89d2a10..58c9b67 100644 > --- a/ld/testsuite/ld-mips-elf/mips-elf-flags.exp > +++ b/ld/testsuite/ld-mips-elf/mips-elf-flags.exp > @@ -314,7 +314,8 @@ good_combination { "-march=interaptiv-mr2 -32" "-mips32r5 -32" } \ > good_combination { "-march=interaptiv-mr2 -32" "-march=m5100 -32" } \ > { mips32r2 interaptiv-mr2 } \ > MIPS32r5 "Imagination interAptiv MR2" \ > - { "DSP ASE" "Enhanced VA Scheme" "MT ASE" } > + { "DSP ASE" "Enhanced VA Scheme" \ > + "MCU (MicroController) ASE" "MT ASE" } > > good_combination { "-march=gs464 -32" "-march=gs464e -32" } \ > { gs464e o32 } \ > -- > 2.9.5 >