Re: Help needed - to add custom instruction to binutils-gdb

[Vijay Kumar Salian <salianvk@gmail.com>]

Hi,

Thank you for the email.

Does the "encoding overlap" mean that the *MATCH_** macro values of 2
instructions are the same?
I have to check this once since I have added other instructions too.

I am using the riscv toolchain from this link:
https://github.com/riscv/riscv-gnu-toolchain
I hope this is the right toolchain for risc-v.

--
Thanks & Regards,
Vijay


On Mon, 21 Jun 2021 at 13:42, Nelson Chu <nelson.chu@sifive.com> wrote:

> On Mon, Jun 21, 2021 at 3:31 PM Vijay Kumar Salian via Binutils
> <binutils@sourceware.org> wrote:
> >
> > Hi,
> >
> > Below are the steps that I followed to add new custom instructions to
> > binutils.
> >
> > 1. Identified the instruction to add as "z.rol".
> >
> > 2. Add the below match and mask macros to riscv-gnu-toolchain/riscv-
> > binutils/include/opcode/riscv-opc.h
> > #define MATCH_Z_ROL 0x6057
> > #define MASK_Z_ROL  0xfe00707f
> >
> > 3. Add the below macro to riscv-gnu-toolchain/riscv-
> > binutils/include/opcode/riscv-opc.h
> > DECLARE_INSN(z_rol, MATCH_Z_ROL, MASK_Z_ROL)
> >
> > 4. Add new entry into const struct riscv_opcode riscv_opcodes[] in file
> > riscv-gnu-toolchain/riscv-binutils/opcodes/riscv-opc.c
> >
> > {"z.rol",       0, INSN_CLASS_I, "d,s,t", MATCH_Z_ROL, MASK_Z_ROL,
> > match_opcode, 0},
>
> The steps are correct.
>
> > 5. Compile the toolchain and test the assembly code with new
> instructions.
> >
> > The new instruction addition worked ONLY when the new entries were made
> at
> > the top of *const struct riscv_opcode riscv_opcodes[]*. But when I tried
> to
> > add the new entries at the *end* of *const struct riscv_opcode
> > riscv_opcodes[],* then toolchain compilation gave a lot of errors during
> > compilation and some of the GCC tools did not get compiled.
>
> The order does affect the results, but the premise is that the
> encoding has overlap, or the new instructions are the aliases of
> others which had existed.  I can get your expected result when adding
> the z.rol at the end of riscv_opcodes, so it should not be the order
> problem for your example.
>
> nelson@LAPTOP-QFSGI1F2:~/test$ cat tmp.s
> .word   0x6057
> z.rol   a0, a1, a2
> nelson@LAPTOP-QFSGI1F2:~/test$ riscv64-unknown-elf-as tmp.s -o tmp.o
> nelson@LAPTOP-QFSGI1F2:~/test$ riscv64-unknown-elf-objdump -d tmp.o
>
> tmp.o:     file format elf64-littleriscv
>
>
> Disassembly of section .text:
>
> 0000000000000000 <.text>:
>    0:   00006057                z.rol   zero,zero,zero
>    4:   00c5e557                z.rol   a0,a1,a2
>
>
> Thanks
> Nelson
>