From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 124674 invoked by alias); 11 Feb 2020 11:53:24 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 124666 invoked by uid 89); 11 Feb 2020 11:53:24 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-2.4 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.1 spammy=H*i:sk:fad30d8, H*f:sk:fad30d8, H*RU:209.85.167.193, HX-Spam-Relays-External:209.85.167.193 X-HELO: mail-oi1-f193.google.com Received: from mail-oi1-f193.google.com (HELO mail-oi1-f193.google.com) (209.85.167.193) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 11 Feb 2020 11:53:22 +0000 Received: by mail-oi1-f193.google.com with SMTP id a142so12506743oii.7 for ; Tue, 11 Feb 2020 03:53:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=BmnnHw1ydUo3azigx9EcWwwFMR8cAhruA+ye3BmRyKA=; b=eCPNqMBbVIn2PW58bdhjM6FnU7zhucZaFD5xGCW0v9k+7yzGW6wjYliHKgYYzJKo2x UQ5ooEzVv3ji8yHY+hCNNvkhp6X1VfDDR1re8G3sZjuLFF9TewV64V5wETDtiy8qNu6a XL6pGT0fjges08Nlv0IZWqaUlIatuRc/GU+pOK6Cn6HOacCjEVls3McBR9qSEDjF4Rfv TURWFSO7gejrRNwxfvW0N+Q8N7m7bRIQ2F6hFc4Ajo6EgW00W+MqJXKHz24++6WAe+Lw MKMnmxN/bPbg4XnhN6X7wgGza7bq7rsvs7eyswbFe7FJp9nNAlrk0A29TWKbF4iE8pcJ wPFg== MIME-Version: 1.0 References: <1e1b8eba-93ff-39ed-460a-a922d12af27e@suse.com> In-Reply-To: From: "H.J. Lu" Date: Tue, 11 Feb 2020 11:53:00 -0000 Message-ID: Subject: Re: [PATCH v5 5/5] x86-64: Intel64 adjustments for insns dealing with far pointers To: Jan Beulich Cc: "binutils@sourceware.org" Content-Type: text/plain; charset="UTF-8" X-IsSubscribed: yes X-SW-Source: 2020-02/txt/msg00177.txt.bz2 On Tue, Feb 11, 2020 at 2:26 AM Jan Beulich wrote: > > AMD and Intel differ in their handling of far indirect branches as well > as LFS/LGS/LSS: AMD CPUs ignore REX.W while Intel ones honors it. (Note > how the latter three were hybrids so far, while far branches were fully > AMD-like.) > > gas/ > 2020-02-XX Jan Beulich > > PR gas/24546 > * config/tc-i386-intel.c (i386_intel_operand): Also handle CALL/JMP > in O_tbyte_ptr case. > * doc/c-i386.texi: Mention far call and full pointer load ISA > differences. > * testsuite/gas/i386/x86-64-branch-3.s, > testsuite/gas/i386/x86-64-intel64.s: Add 64-bit far call cases. > * testsuite/gas/i386/x86-64-branch-3.d, > testsuite/gas/i386/x86-64-intel64.d: Adjust expectations. > * testsuite/gas/i386/x86-64-branch-5.l, > testsuite/gas/i386/x86-64-branch-5.s: New. > * testsuite/gas/i386/i386.exp: Run new test. > > opcodes/ > 2020-02-XX Jan Beulich > > PR gas/24546 > * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode. > * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into > Amd64 and Intel64 templates. > (call, jmp): Likewise for far indirect variants. Dro > Unspecified. > * i386-tbl.h: Re-generate. OK. Thanks. -- H.J.