From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 7803 invoked by alias); 17 Feb 2020 15:45:59 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 7410 invoked by uid 89); 17 Feb 2020 15:45:41 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-2.2 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,KAM_NUMSUBJECT,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=no version=3.3.1 spammy=SSE4*, H*f:sk:4f3e523, flavors, sse4* X-HELO: mail-ot1-f67.google.com Received: from mail-ot1-f67.google.com (HELO mail-ot1-f67.google.com) (209.85.210.67) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 17 Feb 2020 15:45:22 +0000 Received: by mail-ot1-f67.google.com with SMTP id r27so16452090otc.8 for ; Mon, 17 Feb 2020 07:45:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=XTZ4vssUMBVJOyQAWNQm2/tBqNZFn3qdmgw7wGMEZUc=; b=i9FJQWigfY6BZwRBgLNVjDQ66cIl5ShP63wLaNlTFW6NNnnxge2jyIlMztatw7YuJN WzCrzv/QVm+WsS/FyuD2O3pPQXzfXCFunJG5KL2XgqXYVIkh5MB2kgCg3hhQKq/JdZy+ oWMsEr1fVimzgvQQOygNCa9qQA12guTeza4eQHj39uos9hIV945Q5B6cKzARxAJXCBSj MMOw/pXDwlMQdFm1mX5Ssfjr3+i0v8mc0EMHVUuZ/yQ0SZUKxyXF23AEf7IMqiVM5w6X CW7YZltn/2fcwqteHwmN+S5Cg9A6LS9pFpYPnooGOj+V4uEsw90GY+2v9bKhzpib8n37 Q6sw== MIME-Version: 1.0 References: <3bc597bb-10f9-80f9-8e00-f28aeb2eea77@suse.com> <4f3e5233-fb2f-a957-2788-8ffde3939ce2@suse.com> <70b8fc74-e036-1064-ab65-5e0cfe5ec401@suse.com> In-Reply-To: <70b8fc74-e036-1064-ab65-5e0cfe5ec401@suse.com> From: "H.J. Lu" Date: Mon, 17 Feb 2020 15:45:00 -0000 Message-ID: Subject: Re: [committed, PATCH] x86: Don't disable SSE4a when disabling SSE4 To: Jan Beulich Cc: "binutils@sourceware.org" Content-Type: text/plain; charset="UTF-8" X-IsSubscribed: yes X-SW-Source: 2020-02/txt/msg00403.txt.bz2 On Mon, Feb 17, 2020 at 7:32 AM Jan Beulich wrote: > > On 17.02.2020 16:30, H.J. Lu wrote: > > On Mon, Feb 17, 2020 at 7:27 AM Jan Beulich wrote: > >> > >> On 16.02.2020 17:47, H.J. Lu wrote: > >>> On Wed, Feb 12, 2020 at 9:18 AM H.J. Lu wrote: > >>>> > >>>> On Wed, Feb 12, 2020 at 9:08 AM Jan Beulich wrote: > >>>>> > >>>>> Since ".arch sse4a" enables SSE3 and earlier, disabling SSE3 should also > >>>>> disable SSE4a. And as per its name, ".arch .nosse4" should also do so. > >>>>> > >>>>> gas/ > >>>>> 2020-02-XX Jan Beulich > >>>>> > >>>>> * config/tc-i386.c (cpu_noarch): Use CPU_ANY_SSE4_FLAGS in > >>>>> "nosse4" entry. > >>>>> > >>>>> opcodes/ > >>>>> 2020-02-XX Jan Beulich > >>>>> > >>>>> * i386-gen.c (cpu_flag_init): Move CpuSSE4a from > >>>>> CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add > >>>>> CPU_ANY_SSE4_FLAGS entry. > >>>>> * i386-init.h: Re-generate. > >>>>> > >>>> > >>>> OK. > >>>> > >>>> Thanks. > >>> > >>> commit 7deea9aad8 changed nosse4 to include CpuSSE4a. But AMD SSE4a is > >>> a superset of SSE3 and Intel SSE4 is a superset of SSSE3. Disable Intel > >>> SSE4 shouldn't disable AMD SSE4a. This patch restores nosse4. It also > >>> adds .sse4a and nosse4a. > >> > >> And where is it said that "nosse4" means only the Intel flavors? As > >> said in the commit message of said change, to me the clear implication > >> is that anything called SSE4* will get disabled. > >> > > > > SSE4 refers to SSE4 from Intel, which includes SSE4.1 and SSE4.2. > > SSE4a from AMD is unrelated from Intel SSE4. > > Repeating my question then: Where is this being said? (Best imo > would be to delete ".arch .nosse4" support then, eliminating > the ambiguity.) We have both .sse4 and nosse4 which are aliases for SSE4.2. Please feel free to add documentation. -- H.J.