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Lu" Date: Thu, 11 Aug 2022 10:23:33 -0700 Message-ID: Subject: Re: [PATCH 08/12] x86: template-ize vector packed dword/qword integer insns To: Jan Beulich Cc: Binutils Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-3018.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 11 Aug 2022 17:24:17 -0000 On Fri, Aug 5, 2022 at 5:26 AM Jan Beulich wrote: > > Many of the vector integer insns come in dword/qword element pairs. Most > of these pairs follow certain encoding patterns. Introduce a "dq" > template to reduce redundancy. > > Note that in the course of the conversion > - a few otherwise untouched templates are moved, so they end up next to > their siblings), > - drop an unhelpful Cpu64 from the GPR form of VPBROADCASTQ, matching > what we already have for KMOVQ - the diagnostic is better this way for > insns with multiple forms (i.e. the same Cpu64 attributes on {,V}MOVQ, > {,V}PEXTRQ, and {,V}PINSRQ are useful to keep), > - this adds benign/meaningless IgnoreSize attributes to the GPR forms of > KMOVD and VPBROADCASTD; it didn't seem worth avoiding this. > --- > For VPCOMPRESS{D,Q} and VPEXPAND{D,Q} the conversion could only be done > if we allowed Dword/Qword on the memory operands. Imo permitting this > makes sense anyway (as the memory operands aren't full [XYZ]mmword > ones), but such a functional change should probably be a separate patch. > > --- a/opcodes/i386-opc.tbl > +++ b/opcodes/i386-opc.tbl > @@ -971,6 +971,10 @@ pause, 0xf390, None, Cpu186, No_bSuf|No_ > $avx:CpuAVX:Vex128|VexW0|SSE2AVX:VexLIG|VexW0|SSE2AVX:VexVVVV:Vex128= |VexVVVV=3D2|VexW0|SSE2AVX, + > $sse:CpuSSE2::NoRex64::> > > + + d:0:VexW0:IgnoreSize:Dword::Reg32:66, + > + q:1:VexW1:VexW1:Qword:Cpu64:Reg64:> > + > emms, 0xf77, None, CpuMMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ld= Suf, {} > // These really shouldn't allow for Reg64 (movq is the right mnemonic fo= r > // copying between Reg64/Mem64 and RegXMM/RegMMX, as is mandated by Inte= l's > @@ -1016,20 +1020,16 @@ pmullw, 0x0fd5, None, por, 0x0feb, None, , Modrm||C|No_bSuf|N= o_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { ||Unspecified|= BaseIndex, } > psllw, 0x0ff1, None, , Modrm||No_bSuf|N= o_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { ||Unspecified|= BaseIndex, } > psllw, 0x0f71, 6, , Modrm||No_bSuf|No_= wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, } > -pslld, 0x0ff2, None, , Modrm||No_bSuf|N= o_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { ||Unspecified|= BaseIndex, } > -pslld, 0x0f72, 6, , Modrm||No_bSuf|No_= wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, } > -psllq, 0x0ff3, None, , Modrm||No_bSuf|N= o_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { ||Unspecified|= BaseIndex, } > -psllq, 0x0f73, 6, , Modrm||No_bSuf|No_= wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, } > +psll, 0x0ff2 | , None, , Modrm||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { ||Unspecified|BaseIndex, } > +psll, 0x0f72 | , 6, , Modrm||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, } > psraw, 0x0fe1, None, , Modrm||No_bSuf|N= o_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { ||Unspecified|= BaseIndex, } > psraw, 0x0f71, 4, , Modrm||No_bSuf|No_= wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, } > psrad, 0x0fe2, None, , Modrm||No_bSuf|N= o_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { ||Unspecified|= BaseIndex, } > psrad, 0x0f72, 4, , Modrm||No_bSuf|No_= wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, } > psrlw, 0x0fd1, None, , Modrm||No_bSuf|N= o_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { ||Unspecified|= BaseIndex, } > psrlw, 0x0f71, 2, , Modrm||No_bSuf|No_= wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, } > -psrld, 0x0fd2, None, , Modrm||No_bSuf|N= o_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { ||Unspecified|= BaseIndex, } > -psrld, 0x0f72, 2, , Modrm||No_bSuf|No_= wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, } > -psrlq, 0x0fd3, None, , Modrm||No_bSuf|N= o_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { ||Unspecified|= BaseIndex, } > -psrlq, 0x0f73, 2, , Modrm||No_bSuf|No_= wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, } > +psrl, 0x0fd2 | , None, , Modrm||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { ||Unspecified|BaseIndex, } > +psrl, 0x0f72 | , 2, , Modrm||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, } > psubb, 0x0ff8, None, , Modrm||No_bSuf|N= o_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { ||Unspecified|= BaseIndex, } > psubw, 0x0ff9, None, , Modrm||No_bSuf|N= o_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { ||Unspecified|= BaseIndex, } > psubd, 0x0ffa, None, , Modrm||No_bSuf|N= o_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { ||Unspecified|= BaseIndex, } > @@ -1612,8 +1612,7 @@ vpermilp, 0x660c | , None, C > vpermilp, 0x6604 | , None, CpuAVX, Modrm|Vex|Space0F3A|VexW0= |CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Uns= pecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } > vpextrb, 0x6614, None, CpuAVX, RegMem|Vex|Space0F3A|VexWIG|No_bSuf|No_wS= uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64 } > vpextrb, 0x6614, None, CpuAVX, Modrm|Vex|Space0F3A|VexWIG|No_bSuf|No_wSu= f|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Byte|Unspecified|BaseIn= dex } > -vpextrd, 0x6616, None, CpuAVX, Modrm|Vex|Space0F3A|IgnoreSize|No_bSuf|No= _wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Dword|Unspeci= fied|BaseIndex } > -vpextrq, 0x6616, None, CpuAVX|Cpu64, Modrm|Vex|Space0F3A|VexW1|No_bSuf|N= o_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg64|Unspecified|= BaseIndex } > +vpextr, 0x6616, None, CpuAVX|, Modrm|Vex|Space0F3A||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, |Unspecified|BaseIndex } > vpextrw, 0x66c5, None, CpuAVX, Load|Modrm|Vex|Space0F|VexWIG|No_bSuf|No_= wSuf|No_sSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64 } > vpextrw, 0x6615, None, CpuAVX, RegMem|Vex|Space0F3A|VexWIG|No_bSuf|No_wS= uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64 } > vpextrw, 0x6615, None, CpuAVX, Modrm|Vex|Space0F3A|VexWIG|No_bSuf|No_wSu= f|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Word|Unspecified|BaseIn= dex } > @@ -1626,8 +1625,7 @@ vphsubsw, 0x6607, None, CpuAVX|CpuAVX2, > vphsubw, 0x6605, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWI= G|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecif= ied|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } > vpinsrb, 0x6620, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=3D1|VexWIG|No= _bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg32|Reg64, RegXMM= , RegXMM } > vpinsrb, 0x6620, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|No_bSu= f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Byte|Unspecified|BaseIn= dex, RegXMM, RegXMM } > -vpinsrd, 0x6622, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=3D1|IgnoreSiz= e|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg32|Dword|Uns= pecified|BaseIndex, RegXMM, RegXMM } > -vpinsrq, 0x6622, None, CpuAVX|Cpu64, Modrm|Vex|Space0F3A|VexVVVV=3D1|Vex= W1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg64|Unspecif= ied|BaseIndex, RegXMM, RegXMM } > +vpinsr, 0x6622, None, CpuAVX|, Modrm|Vex|Space0F3A|VexVVVV= ||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, |Unspecified|BaseIndex, RegXMM, RegXMM } > vpinsrw, 0x66c4, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|No_b= Suf|No_wSuf|No_sSuf|No_ldSuf, { Imm8, Reg32|Reg64, RegXMM, RegXMM } > vpinsrw, 0x66c4, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|No_bSuf|= No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Word|Unspecified|BaseInde= x, RegXMM, RegXMM } > vpmaddubsw, 0x6604, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|Ve= xWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspe= cified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } > @@ -1673,27 +1671,22 @@ vpshuflw, 0xf270, None, CpuAVX|CpuAVX2, > vpsignb, 0x6608, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWI= G|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecif= ied|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } > vpsignd, 0x660a, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWI= G|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecif= ied|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } > vpsignw, 0x6609, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWI= G|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecif= ied|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } > -vpslld, 0x6672, 6, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=3D2|VexWIG|= CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegX= MM|RegYMM, RegXMM|RegYMM } > -vpslld, 0x66f2, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|C= heckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified= |BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } > +vpsll, 0x6672 | , 6, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVV= VV=3D2|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf= , { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } > +vpsll, 0x66f2 | , None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|Ve= xVVVV|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,= { Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } > vpslldq, 0x6673, 7, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=3D2|VexWIG= |CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg= XMM|RegYMM, RegXMM|RegYMM } > -vpsllq, 0x6673, 6, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=3D2|VexWIG|= CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegX= MM|RegYMM, RegXMM|RegYMM } > -vpsllq, 0x66f3, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|C= heckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified= |BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } > vpsllw, 0x6671, 6, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=3D2|VexWIG|= CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegX= MM|RegYMM, RegXMM|RegYMM } > vpsllw, 0x66f1, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|C= heckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified= |BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } > vpsrad, 0x6672, 4, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=3D2|VexWIG|= CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegX= MM|RegYMM, RegXMM|RegYMM } > vpsrad, 0x66e2, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|C= heckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified= |BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } > vpsraw, 0x6671, 4, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=3D2|VexWIG|= CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegX= MM|RegYMM, RegXMM|RegYMM } > vpsraw, 0x66e1, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|C= heckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified= |BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } > -vpsrld, 0x6672, 2, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=3D2|VexWIG|= CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegX= MM|RegYMM, RegXMM|RegYMM } > -vpsrld, 0x66d2, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|C= heckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified= |BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } > +vpsrl, 0x6672 | , 2, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVV= VV=3D2|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf= , { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } > +vpsrl, 0x66d2 | , None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|Ve= xVVVV|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,= { Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } > vpsrldq, 0x6673, 3, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=3D2|VexWIG= |CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg= XMM|RegYMM, RegXMM|RegYMM } > -vpsrlq, 0x6673, 2, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=3D2|VexWIG|= CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegX= MM|RegYMM, RegXMM|RegYMM } > -vpsrlq, 0x66d3, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|C= heckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified= |BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } > vpsrlw, 0x6671, 2, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=3D2|VexWIG|= CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegX= MM|RegYMM, RegXMM|RegYMM } > vpsrlw, 0x66d1, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|C= heckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified= |BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } > vpsubb, 0x66f8, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|C= heckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Un= specified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } > -vpsubd, 0x66fa, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|C= heckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Un= specified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } > -vpsubq, 0x66fb, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|C= heckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Un= specified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } > +vpsub, 0x66fa | , None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|Ve= xVVVV|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|= Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegY= MM } > vpsubsb, 0x66e8, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|= CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecifie= d|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } > vpsubsw, 0x66e9, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|= CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecifie= d|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } > vpsubusb, 0x66d8, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG= |CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecifi= ed|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } > @@ -1751,8 +1744,7 @@ vbroadcastsd, 0x6619, None, CpuAVX2, Mod > vbroadcastss, 0x6618, None, CpuAVX2, Modrm|Vex|Space0F38|VexW=3D1|No_bSu= f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|RegYMM } > vpblendd, 0x6602, None, CpuAVX2, Modrm|Vex|Space0F3A|VexVVVV=3D1|VexW=3D= 1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Un= specified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } > vpbroadcastb, 0x6678, None, CpuAVX2, Modrm|Vex=3D1|Space0F38|VexW0|No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Byte|Unspecified|BaseIndex|R= egXMM, RegXMM|RegYMM } > -vpbroadcastd, 0x6658, None, CpuAVX2, Modrm|Vex=3D1|Space0F38|VexW0|No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|= RegXMM, RegXMM|RegYMM } > -vpbroadcastq, 0x6659, None, CpuAVX2, Modrm|Vex=3D1|Space0F38|VexW0|No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|= RegXMM, RegXMM|RegYMM } > +vpbroadcast, 0x6658 | , None, CpuAVX2, Modrm|Vex|Space0F38|V= exW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { |Unspecif= ied|BaseIndex|RegXMM, RegXMM|RegYMM } > vpbroadcastw, 0x6679, None, CpuAVX2, Modrm|Vex=3D1|Space0F38|VexW0|No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex|R= egXMM, RegXMM|RegYMM } > vperm2i128, 0x6646, None, CpuAVX2, Modrm|Vex=3D2|Space0F3A|VexVVVV=3D1|V= exW=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecifi= ed|BaseIndex|RegYMM, RegYMM, RegYMM } > vpermd, 0x6636, None, CpuAVX2, Modrm|Vex=3D2|Space0F38|VexVVVV=3D1|VexW= =3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIn= dex|RegYMM, RegYMM, RegYMM } > @@ -1761,15 +1753,11 @@ vpermps, 0x6616, None, CpuAVX2, Modrm|Ve > vpermq, 0x6600, None, CpuAVX2, Modrm|Vex=3D2|Space0F3A|VexW=3D2|No_bSuf|= No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|Reg= YMM, RegYMM } > vextracti128, 0x6639, None, CpuAVX2, Modrm|Vex=3D2|Space0F3A|VexW=3D1|No= _bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, Unspecified= |BaseIndex|RegXMM } > vinserti128, 0x6638, None, CpuAVX2, Modrm|Vex=3D2|Space0F3A|VexVVVV=3D1|= VexW=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecif= ied|BaseIndex|RegXMM, RegYMM, RegYMM } > -vpmaskmovd, 0x668e, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV=3D1|VexW= =3D1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXM= M|RegYMM, RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex } > -vpmaskmovd, 0x668c, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV=3D1|VexW= =3D1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmwo= rd|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } > -vpmaskmovq, 0x668e, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV=3D1|VexW= =3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXM= M|RegYMM, RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex } > -vpmaskmovq, 0x668c, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV=3D1|VexW= =3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmwo= rd|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } > -vpsllvd, 0x6647, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV=3D1|VexW=3D1= |CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecifi= ed|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } > -vpsllvq, 0x6647, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV=3D1|VexW=3D2= |CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecifi= ed|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } > +vpmaskmov, 0x668e, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV||CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM= |RegYMM, RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex } > +vpmaskmov, 0x668c, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV||CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmwor= d|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } > +vpsllv, 0x6647, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|= |CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecifi= ed|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } > vpsravd, 0x6646, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV=3D1|VexW=3D1= |CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecifi= ed|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } > -vpsrlvd, 0x6645, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV=3D1|VexW=3D1= |CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecifi= ed|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } > -vpsrlvq, 0x6645, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV=3D1|VexW=3D2= |CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecifi= ed|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } > +vpsrlv, 0x6645, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|= |CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecifi= ed|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } > > // AVX gather instructions > vgatherdpd, 0x6692, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW1|Che= ckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { Reg= XMM|RegYMM, Qword|Unspecified|BaseIndex, RegXMM|RegYMM } > @@ -1781,9 +1769,8 @@ vgatherqps, 0x6693, None, CpuAVX2, Modrm > vpgatherdd, 0x6690, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW0|No_= bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { RegXMM, Dword|Un= specified|BaseIndex, RegXMM } > vpgatherdd, 0x6690, None, CpuAVX2, Modrm|Vex=3D2|Space0F38|VexVVVV|VexW0= |No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB256, { RegYMM, Dwor= d|Unspecified|BaseIndex, RegYMM } > vpgatherdq, 0x6690, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW1|Che= ckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { Reg= XMM|RegYMM, Qword|Unspecified|BaseIndex, RegXMM|RegYMM } > -vpgatherqd, 0x6691, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW0|No_= bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { RegXMM, Dword|Un= specified|BaseIndex, RegXMM } > +vpgatherq, 0x6691, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { RegXMM, <= dq:elem>|Unspecified|BaseIndex, RegXMM } > vpgatherqd, 0x6691, None, CpuAVX2, Modrm|Vex=3D2|Space0F38|VexVVVV|VexW0= |No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB256, { RegXMM, Dwor= d|Unspecified|BaseIndex, RegXMM } > -vpgatherqq, 0x6691, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW1|No_= bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { RegXMM, Qword|Un= specified|BaseIndex, RegXMM } > vpgatherqq, 0x6691, None, CpuAVX2, Modrm|Vex=3D2|Space0F38|VexVVVV|VexW1= |No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB256, { RegYMM, Qwor= d|Unspecified|BaseIndex, RegYMM } > > // AES + AVX > @@ -1883,18 +1870,14 @@ vpcom, 0xcc | 0x vpcom, 0xcc | 0x | , , CpuXOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|No_bSu= f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Unspecified|Bas= eIndex, RegXMM, RegXMM } > vpermil2p, 0x6648 | , None, CpuXOP, Modrm|Space0F3A|VexVVVV|= VexW0|Vex|VexSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS= uf|No_ldSuf, { Imm8, RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, Re= gXMM|RegYMM, RegXMM|RegYMM } > vpermil2p, 0x6648 | , None, CpuXOP, Modrm|Space0F3A|VexVVVV|= VexW1|Vex|VexSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS= uf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, Re= gXMM|RegYMM, RegXMM|RegYMM } > -vphaddbd, 0xc2, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|No_wSuf|No_= lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } > -vphaddbq, 0xc3, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|No_wSuf|No_= lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } > +vphaddb, 0xc2 | , None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseI= ndex, RegXMM } > vphaddbw, 0xc1, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|No_wSuf|No_= lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } > vphadddq, 0xcb, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|No_wSuf|No_= lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } > -vphaddubd, 0xd2, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|No_wSuf|No= _lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM = } > -vphaddubq, 0xd3, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|No_wSuf|No= _lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM = } > +vphaddub, 0xd2 | , None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_b= Suf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|Base= Index, RegXMM } > vphaddubw, 0xd1, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|No_wSuf|No= _lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM = } > vphaddudq, 0xdb, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|No_wSuf|No= _lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM = } > -vphadduwd, 0xd6, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|No_wSuf|No= _lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM = } > -vphadduwq, 0xd7, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|No_wSuf|No= _lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM = } > -vphaddwd, 0xc6, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|No_wSuf|No_= lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } > -vphaddwq, 0xc7, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|No_wSuf|No_= lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } > +vphadduw, 0xd6 | , None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_b= Suf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|Base= Index, RegXMM } > +vphaddw, 0xc6 | , None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseI= ndex, RegXMM } > vphsubbw, 0xe1, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|No_wSuf|No_= lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } > vphsubdq, 0xe3, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|No_wSuf|No_= lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } > vphsubwd, 0xe2, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|No_wSuf|No_= lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } > @@ -2115,42 +2098,25 @@ vmuls, 0x59, None, vsqrts, 0x51, None, , Modrm|EVexLIG|Masking=3D3|= |VexVVVV||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf= |No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseI= ndex, RegXMM, RegXMM } > vsubs, 0x5C, None, , Modrm|EVexLIG|Masking=3D3|<= sdh:spc1>|VexVVVV||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|= No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIn= dex, RegXMM, RegXMM } > > -valignd, 0x6603, None, CpuAVX512F, Modrm|Masking=3D3|Space0F3A|VexVVVV= =3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|Bas= eIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > -vpternlogd, 0x6625, None, CpuAVX512F, Modrm|Masking=3D3|Space0F3A|VexVVV= V=3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|= No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|Ba= seIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > - > -valignq, 0x6603, None, CpuAVX512F, Modrm|Masking=3D3|Space0F3A|VexVVVV= =3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|Bas= eIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > -vpternlogq, 0x6625, None, CpuAVX512F, Modrm|Masking=3D3|Space0F3A|VexVVV= V=3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|= No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|Ba= seIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > - > +valign, 0x6603, None, CpuAVX512F, Modrm|Masking=3D3|Space0F3A|VexVVV= V=3D1||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf= |No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecifi= ed|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > vblendmp, 0x6665, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexV= VVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseI= ndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > -vpblendmq, 0x6664, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > +vpblendm, 0x6664, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexV= VVV=3D1||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lS= uf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|B= aseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > +vpermi2, 0x6676, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVV= VV=3D1||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSu= f|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|Ba= seIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > vpermi2p, 0x6677, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexV= VVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseI= ndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > -vpermi2q, 0x6676, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > +vpermt2, 0x667E, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVV= VV=3D1||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSu= f|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|Ba= seIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > vpermt2p, 0x667F, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexV= VVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseI= ndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > -vpermt2q, 0x667E, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > -vpmaxsq, 0x663D, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > -vpmaxuq, 0x663F, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > -vpminsq, 0x6639, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > -vpminuq, 0x663B, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > +vpmaxs, 0x663D, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVV= V=3D1||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf= |No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|Bas= eIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > +vpmaxu, 0x663F, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVV= V=3D1||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf= |No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|Bas= eIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > +vpmins, 0x6639, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVV= V=3D1||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf= |No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|Bas= eIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > +vpminu, 0x663B, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVV= V=3D1||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf= |No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|Bas= eIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > vpmuldq, 0x6628, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > -vprolvq, 0x6615, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > -vprorvq, 0x6614, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > -vpsllvq, 0x6647, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > -vpsravq, 0x6646, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > -vpsrlvq, 0x6645, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > - > -vpblendmd, 0x6664, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > -vpermi2d, 0x6676, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > -vpermt2d, 0x667E, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > -vpmaxsd, 0x663D, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > -vpmaxud, 0x663F, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > -vpminsd, 0x6639, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > -vpminud, 0x663B, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > vpmulld, 0x6640, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > -vprolvd, 0x6615, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > -vprorvd, 0x6614, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > -vpsllvd, 0x6647, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > -vpsravd, 0x6646, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > -vpsrlvd, 0x6645, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > +vprolv, 0x6615, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVV= V=3D1||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf= |No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|Bas= eIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > +vprorv, 0x6614, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVV= V=3D1||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf= |No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|Bas= eIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > +vpsllv, 0x6647, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVV= V=3D1||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf= |No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|Bas= eIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > +vpsrav, 0x6646, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVV= V=3D1||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf= |No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|Bas= eIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > +vpsrlv, 0x6645, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVV= V=3D1||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf= |No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|Bas= eIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > +vpternlog, 0x6625, None, CpuAVX512F, Modrm|Masking=3D3|Space0F3A|Vex= VVVV=3D1||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_l= Suf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspec= ified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > > vbroadcastf32x4, 0x661A, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|V= exW=3D1|Disp8MemShift=3D4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,= { XMMword|Unspecified|BaseIndex, RegYMM|RegZMM } > vbroadcasti32x4, 0x665A, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|V= exW=3D1|Disp8MemShift=3D4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,= { XMMword|Unspecified|BaseIndex, RegYMM|RegZMM } > @@ -2161,8 +2127,8 @@ vbroadcasti64x4, 0x665B, None, CpuAVX512 > vbroadcastss, 0x6618, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexW= 0|Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg= XMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } > vbroadcastsd, 0x6619, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexW= 1|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg= XMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM } > > -vpbroadcastd, 0x6658, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexW= 0|Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg= XMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } > -vpbroadcastd, 0x667C, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|No_b= Suf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, RegXMM|RegYMM|RegZMM= } > +vpbroadcast, 0x6658 | , None, CpuAVX512F, Modrm|Masking=3D3|= Space0F38||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N= o_ldSuf, { RegXMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } > +vpbroadcast, 0x667c, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|<= dq:vexw64>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { , Re= gXMM|RegYMM|RegZMM } > > vcmpp, 0xC2, 0x, CpuAVX512F, Modrm|= Masking=3D2|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|N= o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, { RegXMM|RegYMM= |RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } > vcmpp, 0xC2, None, CpuAVX512F, Modrm|Masking=3D2|Space0F|Ve= xVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf= |No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM||Unspe= cified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } > @@ -2343,52 +2309,33 @@ vmovs, 0x10, None, vmovshdup, 0xF316, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexW=3D1|= Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,= { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } > vmovsldup, 0xF312, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexW=3D1|= Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,= { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } > > -vpabsd, 0x661E, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexW=3D1|B= roadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|= No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM= |RegZMM } > -vpabsq, 0x661F, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexW=3D2|B= roadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|= No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM= |RegZMM } > - > +vpabs, 0x661e | , None, CpuAVX512F, Modrm|Masking=3D3|Space0= F38||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseI= ndex, RegXMM|RegYMM|RegZMM } > vpaddd, 0x66FE, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D1|= VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSu= f|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, Reg= XMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > -vpandd, 0x66DB, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D1|= VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSu= f|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseI= ndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > -vpandnd, 0x66DF, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D1= |VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|Base= Index, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > -vpord, 0x66EB, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D1|V= exW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf= |No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIn= dex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > -vpsubd, 0x66FA, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D1|= VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSu= f|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseI= ndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > +vpaddq, 0x66d4, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV|VexW= 1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS= uf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|Reg= YMM|RegZMM, RegXMM|RegYMM|RegZMM } > +vpand, 0x66db, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV|<= dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSu= f|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM||Unspecified|B= aseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > +vpandn, 0x66df, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV|= |Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM||Unspecified|= BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > +vpmuludq, 0x66f4, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV|Ve= xW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_= qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|R= egYMM|RegZMM, RegXMM|RegYMM|RegZMM } > +vpor, 0x66eb, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf= |No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM||Unspecified|Ba= seIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > +vpsub, 0x66fa | , None, CpuAVX512F, Modrm|Masking=3D3|Space0= F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_= lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM||Un= specified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > vpunpckhdq, 0x666A, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV= =3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > +vpunpckhqdq, 0x666d, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV= |VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|= No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXM= M|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > vpunpckldq, 0x6662, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV= =3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > -vpxord, 0x66EF, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D1|= VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSu= f|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseI= ndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > - > -vpaddq, 0x66D4, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D1|= VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSu= f|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, Reg= XMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > -vpandnq, 0x66DF, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D1= |VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|Base= Index, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > -vpandq, 0x66DB, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D1|= VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSu= f|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseI= ndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > -vpmuludq, 0x66F4, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D= 1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_s= Suf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, R= egXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > -vporq, 0x66EB, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D1|V= exW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf= |No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIn= dex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > -vpsubq, 0x66FB, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D1|= VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSu= f|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseI= ndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > -vpunpckhqdq, 0x666D, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV= =3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > -vpunpcklqdq, 0x666C, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV= =3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > -vpxorq, 0x66EF, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D1|= VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSu= f|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseI= ndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > - > -vpbroadcastq, 0x6659, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexW= 1|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg= XMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } > -vpbroadcastq, 0x667C, None, CpuAVX512F|Cpu64, Modrm|Masking=3D3|Space0F3= 8|VexW=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg64, RegXM= M|RegYMM|RegZMM } > +vpunpcklqdq, 0x666c, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV= |VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|= No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXM= M|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > +vpxor, 0x66ef, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV|<= dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSu= f|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM||Unspecified|B= aseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > > > > vpcmpeqd, 0x6676, None, CpuAVX512F, Modrm|Masking=3D2|Space0F|VexVVVV=3D= 1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_s= Suf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, R= egXMM|RegYMM|RegZMM, RegMask } > +vpcmpeqq, 0x6629, None, CpuAVX512F, Modrm|Masking=3D2|Space0F38|VexVVVV|= VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N= o_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM= |RegYMM|RegZMM, RegMask } > vpcmpgtd, 0x6666, None, CpuAVX512F, Modrm|Masking=3D2|Space0F|VexVVVV=3D= 1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_s= Suf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, R= egXMM|RegYMM|RegZMM, RegMask } > -vpcmpd, 0x661F, None, CpuAVX512F, Modrm|Masking=3D2|Space0F3A|VexVVVV=3D= 1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_s= Suf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIn= dex, RegXMM|RegYMM|RegZMM, RegMask } > -vpcmpd, 0x661F, , CpuAVX512F, Modrm|Masking=3D2|= Space0F3A|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf= |No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Dword|Unsp= ecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } > -vpcmpud, 0x661E, None, CpuAVX512F, Modrm|Masking=3D2|Space0F3A|VexVVVV= =3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|Bas= eIndex, RegXMM|RegYMM|RegZMM, RegMask } > -vpcmpud, 0x661E, , CpuAVX512F, Modrm|Masking=3D2= |Space0F3A|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSu= f|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Dword|Uns= pecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } > - > -vpcmpeqq, 0x6629, None, CpuAVX512F, Modrm|Masking=3D2|Space0F38|VexVVVV= =3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegMask } > -vpcmpgtq, 0x6637, None, CpuAVX512F, Modrm|Masking=3D2|Space0F38|VexVVVV= =3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegMask } > -vpcmpq, 0x661F, None, CpuAVX512F, Modrm|Masking=3D2|Space0F3A|VexVVVV=3D= 1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_s= Suf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIn= dex, RegXMM|RegYMM|RegZMM, RegMask } > -vpcmpq, 0x661F, , CpuAVX512F, Modrm|Masking=3D2|= Space0F3A|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf= |No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Qword|Unsp= ecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } > -vpcmpuq, 0x661E, None, CpuAVX512F, Modrm|Masking=3D2|Space0F3A|VexVVVV= =3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|Bas= eIndex, RegXMM|RegYMM|RegZMM, RegMask } > -vpcmpuq, 0x661E, , CpuAVX512F, Modrm|Masking=3D2= |Space0F3A|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSu= f|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Qword|Uns= pecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } > - > -vptestmd, 0x6627, None, CpuAVX512F, Modrm|Masking=3D2|Space0F38|VexVVVV= =3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegMask } > -vptestnmd, 0xF327, None, CpuAVX512F, Modrm|Masking=3D2|Space0F38|VexVVVV= =3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegMask } > +vpcmpgtq, 0x6637, None, CpuAVX512F, Modrm|Masking=3D2|Space0F38|VexVVVV|= VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N= o_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM= |RegYMM|RegZMM, RegMask } > +vpcmp, 0x661f, None, CpuAVX512F, Modrm|Masking=3D2|Space0F3A|VexVVVV= ||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_s= Suf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|Ba= seIndex, RegXMM|RegYMM|RegZMM, RegMask } > +vpcmpu, 0x661e, None, CpuAVX512F, Modrm|Masking=3D2|Space0F3A|VexVVV= V||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_= sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|B= aseIndex, RegXMM|RegYMM|RegZMM, RegMask } > +vpcmp, 0x661f, , CpuAVX512F, Modrm|Masking= =3D2|Space0F3A|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSu= f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|<= dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } > +vpcmpu, 0x661e, , CpuAVX512F, Modrm|Masking= =3D2|Space0F3A|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSu= f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|<= dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } > > -vptestmq, 0x6627, None, CpuAVX512F, Modrm|Masking=3D2|Space0F38|VexVVVV= =3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegMask } > -vptestnmq, 0xF327, None, CpuAVX512F, Modrm|Masking=3D2|Space0F38|VexVVVV= =3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegMask } > +vptestm, 0x6627, None, CpuAVX512F, Modrm|Masking=3D2|Space0F38|VexVV= VV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No= _sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIn= dex, RegXMM|RegYMM|RegZMM, RegMask } > +vptestnm, 0xf327, None, CpuAVX512F, Modrm|Masking=3D2|Space0F38|VexV= VVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseI= ndex, RegXMM|RegYMM|RegZMM, RegMask } > > vpermd, 0x6636, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=3D= 1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_s= Suf|No_qSuf|No_ldSuf, { RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|R= egZMM, RegYMM|RegZMM } > vpermps, 0x6616, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYM= M|RegZMM, RegYMM|RegZMM } > @@ -2436,30 +2383,20 @@ vpmovzxwd, 0x6633, None, CpuAVX512F, Mod > vpmovsxwq, 0x6624, None, CpuAVX512F, Modrm|EVex=3D1|Masking=3D3|Space0F3= 8|VexWIG|Disp8MemShift=3D4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf= , { RegXMM|Unspecified|BaseIndex, RegZMM } > vpmovzxwq, 0x6634, None, CpuAVX512F, Modrm|EVex=3D1|Masking=3D3|Space0F3= 8|VexWIG|Disp8MemShift=3D4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf= , { RegXMM|Unspecified|BaseIndex, RegZMM } > > -vprold, 0x6672, 1, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D2|Vex= W=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N= o_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, = RegXMM|RegYMM|RegZMM } > -vprord, 0x6672, 0, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D2|Vex= W=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N= o_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, = RegXMM|RegYMM|RegZMM } > - > -vprolq, 0x6672, 1, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D2|Vex= W=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N= o_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, = RegXMM|RegYMM|RegZMM } > -vprorq, 0x6672, 0, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D2|Vex= W=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N= o_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, = RegXMM|RegYMM|RegZMM } > +vprol, 0x6672, 1, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D2|= |Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|Bas= eIndex, RegXMM|RegYMM|RegZMM } > +vpror, 0x6672, 0, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D2|= |Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|Bas= eIndex, RegXMM|RegYMM|RegZMM } > > vpscatterqd, 0x66A1, None, CpuAVX512F, Modrm|EVex=3D1|Masking=3D2|NoDefM= ask|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_= sSuf|No_qSuf|No_ldSuf, { RegYMM, Dword|Unspecified|BaseIndex } > vscatterqps, 0x66A3, None, CpuAVX512F, Modrm|EVex=3D1|Masking=3D2|NoDefM= ask|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_= sSuf|No_qSuf|No_ldSuf, { RegYMM, Dword|Unspecified|BaseIndex } > > vpshufd, 0x6670, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexW=3D1|Br= oadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N= o_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|R= egYMM|RegZMM } > > -vpslld, 0x66F2, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV|VexW= 0|Disp8MemShift=3D4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No= _ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM= |RegZMM } > -vpslld, 0x6672, 6, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D2|Vex= W=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N= o_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, = RegXMM|RegYMM|RegZMM } > -vpsrad, 0x66E2, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D1|= VexW=3D1|Disp8MemShift=3D4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_= qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM= |RegYMM|RegZMM } > -vpsrad, 0x6672, 4, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D2|Vex= W=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N= o_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, = RegXMM|RegYMM|RegZMM } > -vpsrld, 0x66D2, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D1|= VexW=3D1|Disp8MemShift=3D4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_= qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM= |RegYMM|RegZMM } > -vpsrld, 0x6672, 2, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D2|Vex= W=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N= o_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, = RegXMM|RegYMM|RegZMM } > - > -vpsllq, 0x66F3, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D1|= VexW=3D2|Disp8MemShift=3D4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_= qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM= |RegYMM|RegZMM } > -vpsllq, 0x6673, 6, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D2|Vex= W=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N= o_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, = RegXMM|RegYMM|RegZMM } > -vpsraq, 0x66E2, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D1|= VexW=3D2|Disp8MemShift=3D4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_= qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM= |RegYMM|RegZMM } > -vpsraq, 0x6672, 4, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D2|Vex= W=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N= o_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, = RegXMM|RegYMM|RegZMM } > -vpsrlq, 0x66D3, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D1|= VexW=3D2|Disp8MemShift=3D4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_= qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM= |RegYMM|RegZMM } > -vpsrlq, 0x6673, 2, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D2|Vex= W=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N= o_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, = RegXMM|RegYMM|RegZMM } > +vpsll, 0x66f2 | , None, CpuAVX512F, Modrm|Masking=3D3|Space0= F|VexVVVV||Disp8MemShift=3D4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|= No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|Reg= ZMM, RegXMM|RegYMM|RegZMM } > +vpsll, 0x6672 | , 6, CpuAVX512F, Modrm|Masking=3D3|Space0F|V= exVVVV=3D2||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No= _lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unsp= ecified|BaseIndex, RegXMM|RegYMM|RegZMM } > +vpsra, 0x66e2, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV|<= dq:vexw>|Disp8MemShift=3D4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_= qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM= |RegYMM|RegZMM } > +vpsra, 0x6672, 4, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D2|= |Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|Bas= eIndex, RegXMM|RegYMM|RegZMM } > +vpsrl, 0x66d2 | , None, CpuAVX512F, Modrm|Masking=3D3|Space0= F|VexVVVV||Disp8MemShift=3D4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|= No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|Reg= ZMM, RegXMM|RegYMM|RegZMM } > +vpsrl, 0x6672 | , 2, CpuAVX512F, Modrm|Masking=3D3|Space0F|V= exVVVV=3D2||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No= _lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unsp= ecified|BaseIndex, RegXMM|RegYMM|RegZMM } > > vrcp14p, 0x664C, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, Reg= XMM|RegYMM|RegZMM } > vrcp14s, 0x664D, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0F= 38|VexVVVV||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|= No_ldSuf, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } > @@ -2485,11 +2422,9 @@ vunpcklp, 0x14, None, CpuAV > vpbroadcastmb2q, 0xF32A, None, CpuAVX512CD, Modrm|Space0F38|EVex=3D5|Vex= W=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegXMM|R= egYMM|RegZMM } > vpbroadcastmw2d, 0xF33A, None, CpuAVX512CD, Modrm|Space0F38|EVex=3D5|Vex= W=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegXMM|R= egYMM|RegZMM } > > -vpconflictd, 0x66C4, None, CpuAVX512CD, Modrm|Masking=3D3|Space0F38|VexW= =3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|= RegYMM|RegZMM } > -vpconflictq, 0x66C4, None, CpuAVX512CD, Modrm|Masking=3D3|Space0F38|VexW= =3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|= RegYMM|RegZMM } > +vpconflict, 0x66c4, None, CpuAVX512CD, Modrm|Masking=3D3|Space0F38|<= dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSu= f|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex,= RegXMM|RegYMM|RegZMM } > > -vplzcntd, 0x6644, None, CpuAVX512CD, Modrm|Masking=3D3|Space0F38|VexW=3D= 1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS= uf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|Reg= YMM|RegZMM } > -vplzcntq, 0x6644, None, CpuAVX512CD, Modrm|Masking=3D3|Space0F38|VexW=3D= 2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS= uf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|Reg= YMM|RegZMM } > +vplzcnt, 0x6644, None, CpuAVX512CD, Modrm|Masking=3D3|Space0F38||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N= o_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, Re= gXMM|RegYMM|RegZMM } > > // AVX512CD instructions end. > > @@ -2565,10 +2500,10 @@ vgatherdpd, 0x6692, None, CpuAVX512F|Cpu > vgatherqp, 0x6693, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Maski= ng=3D2|NoDefMask|Space0F38||Disp8MemShift|VecSIB128|No_bSuf|No_wSu= f|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { |Unspecified|BaseIndex, RegX= MM } > vgatherqpd, 0x6693, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D3|Masking= =3D2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3D3|VecSIB256|No_bSuf|No_wSuf|= No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegYMM } > vpgatherdq, 0x6690, None, CpuAVX512F|CpuAVX512VL, Modrm|Masking=3D2|NoDe= fMask|Space0F38|VexW1|Disp8MemShift=3D3|VecSIB128|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM|RegYMM } > -vpgatherqq, 0x6691, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D2|Masking= =3D2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3D3|VecSIB128|No_bSuf|No_wSuf|= No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM } > +vpgatherq, 0x6691, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Maski= ng=3D2|NoDefMask|Space0F38||Disp8MemShift|VecSIB128|No_bSuf|No_wSu= f|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { |Unspecified|BaseIndex, RegX= MM } > vpgatherqq, 0x6691, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D3|Masking= =3D2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3D3|VecSIB256|No_bSuf|No_wSuf|= No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegYMM } > vpscatterdq, 0x66A0, None, CpuAVX512F|CpuAVX512VL, Modrm|Masking=3D2|NoD= efMask|Space0F38|VexW1|Disp8MemShift=3D3|VecSIB128|No_bSuf|No_wSuf|No_lSuf|= No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex } > -vpscatterqq, 0x66A1, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D2|Maskin= g=3D2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3D3|VecSIB128|No_bSuf|No_wSuf= |No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex } > +vpscatterq, 0x66A1, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Mask= ing=3D2|NoDefMask|Space0F38||Disp8MemShift|VecSIB128|No_bSuf|No_wS= uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, |Unspecified|BaseIn= dex } > vpscatterqq, 0x66A1, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D3|Maskin= g=3D2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3D3|VecSIB256|No_bSuf|No_wSuf= |No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Qword|Unspecified|BaseIndex } > vscatterdpd, 0x66A2, None, CpuAVX512F|CpuAVX512VL, Modrm|Masking=3D2|NoD= efMask|Space0F38|VexW1|Disp8MemShift=3D3|VecSIB128|No_bSuf|No_wSuf|No_lSuf|= No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex } > vscatterqp, 0x66A3, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Mask= ing=3D2|NoDefMask|Space0F38||Disp8MemShift|VecSIB128|No_bSuf|No_wS= uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, |Unspecified|BaseIn= dex } > @@ -2579,11 +2514,9 @@ vgatherdps, 0x6692, None, CpuAVX512F|Cpu > vgatherqps, 0x6693, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D3|Masking= =3D2|NoDefMask|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB256|No_bSuf|No_wSuf|= No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM } > vpgatherdd, 0x6690, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D2|Masking= =3D2|NoDefMask|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB128|No_bSuf|No_wSuf|= No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM } > vpgatherdd, 0x6690, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D3|Masking= =3D2|NoDefMask|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB256|No_bSuf|No_wSuf|= No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegYMM } > -vpgatherqd, 0x6691, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D2|Masking= =3D2|NoDefMask|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB128|No_bSuf|No_wSuf|= No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM } > vpgatherqd, 0x6691, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D3|Masking= =3D2|NoDefMask|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB256|No_bSuf|No_wSuf|= No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM } > vpscatterdd, 0x66A0, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D2|Maskin= g=3D2|NoDefMask|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB128|No_bSuf|No_wSuf= |No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex } > vpscatterdd, 0x66A0, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D3|Maskin= g=3D2|NoDefMask|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB256|No_bSuf|No_wSuf= |No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Dword|Unspecified|BaseIndex } > -vpscatterqd, 0x66A1, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D2|Maskin= g=3D2|NoDefMask|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB128|No_bSuf|No_wSuf= |No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex } > vpscatterqd, 0x66A1, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D3|Maskin= g=3D2|NoDefMask|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB256|No_bSuf|No_wSuf= |No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex } > vscatterdps, 0x66A2, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D2|Maskin= g=3D2|NoDefMask|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB128|No_bSuf|No_wSuf= |No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex } > vscatterdps, 0x66A2, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D3|Maskin= g=3D2|NoDefMask|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB256|No_bSuf|No_wSuf= |No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Dword|Unspecified|BaseIndex } > @@ -2694,38 +2627,22 @@ vpmovzxwq, 0x6634, None, CpuAVX512F|CpuA > > // AVX512BW instructions. > > -kaddd, 0x664A, None, CpuAVX512BW, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|VexW= =3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, = RegMask } > -kandd, 0x6641, None, CpuAVX512BW, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|VexW= =3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, = RegMask } > -kandnd, 0x6642, None, CpuAVX512BW, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|Vex= W=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegMask,= RegMask, RegMask } > -kmovd, 0x6690, None, CpuAVX512BW, Modrm|Vex=3D1|Space0F|VexW1|No_bSuf|No= _wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask|Dword|Unspecified|BaseInd= ex, RegMask } > -kmovd, 0x6691, None, CpuAVX512BW, Modrm|Vex=3D1|Space0F|VexW=3D2|IgnoreS= ize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, Dword|Unsp= ecified|BaseIndex } > -kmovd, 0xF292, None, CpuAVX512BW, D|Modrm|Vex=3D1|Space0F|No_bSuf|No_wSu= f|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, RegMask } > -knotd, 0x6644, None, CpuAVX512BW, Modrm|Vex=3D1|Space0F|VexW=3D2|No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask } > -kord, 0x6645, None, CpuAVX512BW, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|VexW= =3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, = RegMask } > -kortestd, 0x6698, None, CpuAVX512BW, Modrm|Vex=3D1|Space0F|VexW=3D2|No_b= Suf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask } > -ktestd, 0x6699, None, CpuAVX512BW, Modrm|Vex=3D1|Space0F|VexW=3D2|No_bSu= f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask } > -kxnord, 0x6646, None, CpuAVX512BW, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|Vex= W=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask,= RegMask } > -kxord, 0x6647, None, CpuAVX512BW, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|VexW= =3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegMask, = RegMask, RegMask } > - > -kaddq, 0x4A, None, CpuAVX512BW, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|VexW= =3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, = RegMask } > -kandnq, 0x42, None, CpuAVX512BW, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|VexW= =3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegMask, = RegMask, RegMask } > -kandq, 0x41, None, CpuAVX512BW, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|VexW= =3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, = RegMask } > -kmovq, 0x90, None, CpuAVX512BW, Modrm|Vex=3D1|Space0F|VexW1|No_bSuf|No_w= Suf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask|Qword|Unspecified|BaseIndex= , RegMask } > -kmovq, 0x91, None, CpuAVX512BW, Modrm|Vex=3D1|Space0F|VexW=3D2|IgnoreSiz= e|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, Qword|Unspec= ified|BaseIndex } > -kmovq, 0xF292, None, CpuAVX512BW, D|Modrm|Vex=3D1|Space0F|VexW=3D2|No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg64, RegMask } > -knotq, 0x44, None, CpuAVX512BW, Modrm|Vex=3D1|Space0F|VexW=3D2|No_bSuf|N= o_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask } > -korq, 0x45, None, CpuAVX512BW, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|VexW=3D= 2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, Reg= Mask } > -kortestq, 0x98, None, CpuAVX512BW, Modrm|Vex=3D1|Space0F|VexW=3D2|No_bSu= f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask } > -ktestq, 0x99, None, CpuAVX512BW, Modrm|Vex=3D1|Space0F|VexW=3D2|No_bSuf|= No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask } > +kadd, 0x4a, None, CpuAVX512BW, Modrm|Vex256|Space0F|VexVVVV= |VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask= , RegMask } > +kand, 0x41, None, CpuAVX512BW, Modrm|Vex256|Space0F|VexVVVV= |VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask= , RegMask } > +kandn, 0x42, None, CpuAVX512BW, Modrm|Vex256|Space0F|VexVVV= V|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegMas= k, RegMask, RegMask } > +kmov, 0x90, None, CpuAVX512BW, Modrm|Vex128|Space0F|VexW1|N= o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask||Unspec= ified|BaseIndex, RegMask } > +kmov, 0x91, None, CpuAVX512BW, Modrm|Vex128|Space0F|VexW1|I= gnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, |Unspecified|BaseIndex } > +kmov, 0xf292, None, CpuAVX512BW, D|Modrm|Vex128|Space0F||= No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { , RegMask } > +knot, 0x44, None, CpuAVX512BW, Modrm|Vex128|Space0F|VexW1|N= o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask } > +kor, 0x45, None, CpuAVX512BW, Modrm|Vex256|Space0F|VexVVVV|= VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask,= RegMask } > +kortest, 0x98, None, CpuAVX512BW, Modrm|Vex128|Space0F|VexW= 1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask } > +ktest, 0x99, None, CpuAVX512BW, Modrm|Vex128|Space0F|VexW1|= No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask } > +kxnor, 0x46, None, CpuAVX512BW, Modrm|Vex256|Space0F|VexVVV= V|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMas= k, RegMask } > +kxor, 0x47, None, CpuAVX512BW, Modrm|Vex256|Space0F|VexVVVV= |VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegMask= , RegMask, RegMask } > kunpckdq, 0x4B, None, CpuAVX512BW, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|Vex= W=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask,= RegMask } > kunpckwd, 0x4B, None, CpuAVX512BW, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|Vex= W=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask,= RegMask } > -kxnorq, 0x46, None, CpuAVX512BW, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|VexW= =3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, = RegMask } > -kxorq, 0x47, None, CpuAVX512BW, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|VexW= =3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegMask, = RegMask, RegMask } > - > -kshiftld, 0x6633, None, CpuAVX512BW, Modrm|Vex=3D1|Space0F3A|VexW=3D1|No= _bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMask, RegMask } > -kshiftlq, 0x6633, None, CpuAVX512BW, Modrm|Vex=3D1|Space0F3A|VexW=3D2|No= _bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMask, RegMask } > -kshiftrd, 0x6631, None, CpuAVX512BW, Modrm|Vex=3D1|Space0F3A|VexW=3D1|No= _bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMask, RegMask } > -kshiftrq, 0x6631, None, CpuAVX512BW, Modrm|Vex=3D1|Space0F3A|VexW=3D2|No= _bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMask, RegMask } > +kshiftl, 0x6633, None, CpuAVX512BW, Modrm|Vex128|Space0F3A|= |No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMask, RegMask= } > +kshiftr, 0x6631, None, CpuAVX512BW, Modrm|Vex128|Space0F3A|= |No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMask, RegMask= } > > vdbpsadbw, 0x6642, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F3A|VexVVV= V=3D1|VexW=3D1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|= RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > > @@ -2940,11 +2857,8 @@ vextracti32x8, 0x663B, None, CpuAVX512DQ > vinsertf32x8, 0x661A, None, CpuAVX512DQ, Modrm|EVex=3D1|Masking=3D3|Spac= e0F3A|VexVVVV=3D1|VexW=3D1|Disp8MemShift=3D5|No_bSuf|No_wSuf|No_lSuf|No_sSu= f|No_qSuf|No_ldSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM } > vinserti32x8, 0x663A, None, CpuAVX512DQ, Modrm|EVex=3D1|Masking=3D3|Spac= e0F3A|VexVVVV=3D1|VexW=3D1|Disp8MemShift=3D5|No_bSuf|No_wSuf|No_lSuf|No_sSu= f|No_qSuf|No_ldSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM } > > -vpextrd, 0x6616, None, CpuAVX512DQ, Modrm|EVex128|Space0F3A|Disp8MemShif= t=3D2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, = RegXMM, Reg32|Dword|Unspecified|BaseIndex } > -vpinsrd, 0x6622, None, CpuAVX512DQ, Modrm|EVex128|Space0F3A|VexVVVV=3D1|= Disp8MemShift=3D2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS= uf, { Imm8, Reg32|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } > - > -vpextrq, 0x6616, None, CpuAVX512DQ|Cpu64, Modrm|EVex128|Space0F3A|VexW1|= Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8,= RegXMM, Reg64|Unspecified|BaseIndex } > -vpinsrq, 0x6622, None, CpuAVX512DQ|Cpu64, Modrm|EVex128|Space0F3A|VexVVV= V=3D1|VexW1|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ld= Suf, { Imm8, Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } > +vpextr, 0x6616, None, CpuAVX512DQ|, Modrm|EVex128|Space0F3= A||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSu= f, { Imm8, RegXMM, |Unspecified|BaseIndex } > +vpinsr, 0x6622, None, CpuAVX512DQ|, Modrm|EVex128|Space0F3= A|VexVVVV||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf= |No_ldSuf, { Imm8, |Unspecified|BaseIndex, RegXMM, RegXMM } > > vextractf64x2, 0x6619, None, CpuAVX512DQ, Modrm|MaskingMorZ|Space0F3A|Ve= xW=3D2|Disp8MemShift=3D4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, = { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex } > vextracti64x2, 0x6639, None, CpuAVX512DQ, Modrm|MaskingMorZ|Space0F3A|Ve= xW=3D2|Disp8MemShift=3D4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, = { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex } > @@ -2958,11 +2872,8 @@ vfpclasspx, 0x6666, None, CpuAVX512D > vfpclasspy, 0x6666, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex256|Mas= king=3D2|Space0F3A||Broadcast|Disp8MemShift=3D5|No_bSuf|No_wSuf|No= _lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM||Unspecified|BaseIn= dex, RegMask } > vfpclasss, 0x67, None, , Modrm|EVexLIG|Masking= =3D2|Space0F3A||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_= qSuf|No_ldSuf, { Imm8, RegXMM||Unspecified|BaseIndex, RegMask } > > -vpmovd2m, 0xF339, None, CpuAVX512DQ, Modrm|EVex=3D5|Space0F38|VexW=3D1|N= o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, Re= gMask } > -vpmovq2m, 0xF339, None, CpuAVX512DQ, Modrm|EVex=3D5|Space0F38|VexW=3D2|N= o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, Re= gMask } > - > -vpmovm2d, 0xF338, None, CpuAVX512DQ, Modrm|EVex=3D5|Space0F38|VexW=3D1|N= o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegXMM|RegYMM|R= egZMM } > -vpmovm2q, 0xF338, None, CpuAVX512DQ, Modrm|EVex=3D5|Space0F38|VexW=3D2|N= o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegXMM|RegYMM|R= egZMM } > +vpmov2m, 0xf339, None, CpuAVX512DQ, Modrm|EVexDYN|Space0F38||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM,= RegMask } > +vpmovm2, 0xf338, None, CpuAVX512DQ, Modrm|EVexDYN|Space0F38||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegXMM|RegYM= M|RegZMM } > > vpmullq, 0x6640, None, CpuAVX512DQ, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > > @@ -3014,8 +2925,7 @@ vp4dpwssds, 0xf253, None, CpuAVX512_4VNN > > // AVX512_VPOPCNTDQ instructions > > -vpopcntd, 0x6655, None, CpuAVX512_VPOPCNTDQ, Modrm|Masking=3D3|Space0F38= |VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, Re= gXMM|RegYMM|RegZMM } > -vpopcntq, 0x6655, None, CpuAVX512_VPOPCNTDQ, Modrm|Masking=3D3|Space0F38= |VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, Re= gXMM|RegYMM|RegZMM } > +vpopcnt, 0x6655, None, CpuAVX512_VPOPCNTDQ, Modrm|Masking=3D3|Space0= F38||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseI= ndex, RegXMM|RegYMM|RegZMM } > > // AVX512_VPOPCNTDQ instructions end > > @@ -3027,23 +2937,17 @@ vpcompressw, 0x6663, None, CpuAVX512_VBM > vpexpandb, 0x6662, None, CpuAVX512_VBMI2, Modrm|Masking=3D3|Space0F38|Ve= xW=3D1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg= XMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } > vpexpandw, 0x6662, None, CpuAVX512_VBMI2, Modrm|Masking=3D3|Space0F38|Ve= xW=3D2|Disp8MemShift=3D1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS= uf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|Re= gZMM } > > -vpshldvd, 0x6671, None, CpuAVX512_VBMI2, Modrm|Masking=3D3|Space0F38|Vex= VVVV=3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lS= uf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseI= ndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > -vpshrdvd, 0x6673, None, CpuAVX512_VBMI2, Modrm|Masking=3D3|Space0F38|Vex= VVVV=3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lS= uf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseI= ndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > - > -vpshldvq, 0x6671, None, CpuAVX512_VBMI2, Modrm|Masking=3D3|Space0F38|Vex= VVVV=3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lS= uf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseI= ndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > -vpshrdvq, 0x6673, None, CpuAVX512_VBMI2, Modrm|Masking=3D3|Space0F38|Vex= VVVV=3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lS= uf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseI= ndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > - > -vpshldvw, 0x6670, None, CpuAVX512_VBMI2, Modrm|Masking=3D3|Space0F38|Vex= VVVV=3D1|VexW=3D2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf= |No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|Reg= YMM|RegZMM, RegXMM|RegYMM|RegZMM } > -vpshrdvw, 0x6672, None, CpuAVX512_VBMI2, Modrm|Masking=3D3|Space0F38|Vex= VVVV=3D1|VexW=3D2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf= |No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|Reg= YMM|RegZMM, RegXMM|RegYMM|RegZMM } > +vpshldv, 0x6671, None, CpuAVX512_VBMI2, Modrm|Masking=3D3|Space0F38|= VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lS= uf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|B= aseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > +vpshldvw, 0x6670, None, CpuAVX512_VBMI2, Modrm|Masking=3D3|Space0F38|Vex= VVVV|VexW1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu= f|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|Reg= ZMM, RegXMM|RegYMM|RegZMM } > > -vpshldd, 0x6671, None, CpuAVX512_VBMI2, Modrm|Masking=3D3|Space0F3A|VexV= VVV=3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSu= f|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|= BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > -vpshrdd, 0x6673, None, CpuAVX512_VBMI2, Modrm|Masking=3D3|Space0F3A|VexV= VVV=3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSu= f|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|= BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > +vpshrdv, 0x6673, None, CpuAVX512_VBMI2, Modrm|Masking=3D3|Space0F38|= VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lS= uf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|B= aseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > +vpshrdvw, 0x6672, None, CpuAVX512_VBMI2, Modrm|Masking=3D3|Space0F38|Vex= VVVV|VexW1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu= f|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|Reg= ZMM, RegXMM|RegYMM|RegZMM } > > -vpshldq, 0x6671, None, CpuAVX512_VBMI2, Modrm|Masking=3D3|Space0F3A|VexV= VVV=3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSu= f|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|= BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > -vpshrdq, 0x6673, None, CpuAVX512_VBMI2, Modrm|Masking=3D3|Space0F3A|VexV= VVV=3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSu= f|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|= BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > +vpshld, 0x6671, None, CpuAVX512_VBMI2, Modrm|Masking=3D3|Space0F3A|V= exVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSu= f|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecif= ied|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > +vpshldw, 0x6670, None, CpuAVX512_VBMI2, Modrm|Masking=3D3|Space0F3A|VexV= VVV|VexW1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf= |No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYM= M|RegZMM, RegXMM|RegYMM|RegZMM } > > -vpshldw, 0x6670, None, CpuAVX512_VBMI2, Modrm|Masking=3D3|Space0F3A|VexV= VVV=3D1|VexW=3D2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|= No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXM= M|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > -vpshrdw, 0x6672, None, CpuAVX512_VBMI2, Modrm|Masking=3D3|Space0F3A|VexV= VVV=3D1|VexW=3D2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|= No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXM= M|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > +vpshrd, 0x6673, None, CpuAVX512_VBMI2, Modrm|Masking=3D3|Space0F3A|V= exVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSu= f|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecif= ied|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > +vpshrdw, 0x6672, None, CpuAVX512_VBMI2, Modrm|Masking=3D3|Space0F3A|VexV= VVV|VexW1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf= |No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYM= M|RegZMM, RegXMM|RegYMM|RegZMM } > > // AVX512_VBMI2 instructions end > > @@ -3237,8 +3141,7 @@ enqcmds, 0xf30f38f8, None, CpuENQCMD, Mo > > // VP2INTERSECT instructions. > > -vp2intersectd, 0xf268, None, CpuAVX512_VP2INTERSECT, Modrm|Space0F38|Vex= VVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_s= Suf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, R= egXMM|RegYMM|RegZMM, RegMask } > -vp2intersectq, 0xf268, None, CpuAVX512_VP2INTERSECT, Modrm|Space0F38|Vex= VVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_s= Suf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, R= egXMM|RegYMM|RegZMM, RegMask } > +vp2intersect, 0xf268, None, CpuAVX512_VP2INTERSECT, Modrm|Space0F38|= VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lS= uf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|B= aseIndex, RegXMM|RegYMM|RegZMM, RegMask } > > // VP2INTERSECT instructions end. > > OK. Thanks. --=20 H.J.