From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 12441 invoked by alias); 8 Oct 2013 15:32:05 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 12432 invoked by uid 89); 8 Oct 2013 15:32:04 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=2.8 required=5.0 tests=AWL,BAYES_50,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPAM_SUBJECT,SPF_PASS autolearn=no version=3.3.2 X-HELO: mail-ob0-f178.google.com Received: from mail-ob0-f178.google.com (HELO mail-ob0-f178.google.com) (209.85.214.178) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Tue, 08 Oct 2013 15:32:04 +0000 Received: by mail-ob0-f178.google.com with SMTP id uz6so602628obc.37 for ; Tue, 08 Oct 2013 08:32:02 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.182.1.196 with SMTP id 4mr498093obo.69.1381246322422; Tue, 08 Oct 2013 08:32:02 -0700 (PDT) Received: by 10.76.110.15 with HTTP; Tue, 8 Oct 2013 08:32:02 -0700 (PDT) In-Reply-To: <52543EE302000078000F9AF4@nat28.tlf.novell.com> References: <5254349502000078000F9A3D@nat28.tlf.novell.com> <525435BC02000078000F9A51@nat28.tlf.novell.com> <52543EE302000078000F9AF4@nat28.tlf.novell.com> Date: Tue, 08 Oct 2013 15:32:00 -0000 Message-ID: Subject: Re: [PATCH 2/6] x86/MPX: fix address size handling From: "H.J. Lu" To: Jan Beulich Cc: kirill.yukhin@intel.com, Binutils Content-Type: text/plain; charset=ISO-8859-1 X-IsSubscribed: yes X-SW-Source: 2013-10/txt/msg00082.txt.bz2 On Tue, Oct 8, 2013 at 8:20 AM, Jan Beulich wrote: >>>> On 08.10.13 at 17:15, "H.J. Lu" wrote: >> On Tue, Oct 8, 2013 at 7:41 AM, Jan Beulich wrote: >>> While address overrides are ignored in 64-bit mode (and hence shouldn't >>> result in an error), trying to use 16-bit addressing is documented to >>> result in #UD, and hence the assembler should reject the attempt. >>> >>> gas/ >>> 2013-10-08 Jan Beulich >>> >>> * tc-i386.c (md_assemble): Alter address size checking for MPX >>> instructions. >>> >>> --- 2013-10-07/gas/config/tc-i386.c >>> +++ 2013-10-07/gas/config/tc-i386.c >>> @@ -3549,10 +3549,15 @@ md_assemble (char *line) >>> if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok) >>> as_bad (_("expecting valid branch instruction after `bnd'")); >>> >>> - if (i.tm.cpu_flags.bitfield.cpumpx >>> - && flag_code == CODE_64BIT >>> - && i.prefix[ADDR_PREFIX]) >>> - as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions.")); >> >> It is done on purpose. When 32-bit address prefix in 64-bit is ignored, >> MPX doesn't work correctly for x32. > > I don't understand: It _is_ being ignored by the hardware as per > the documentation. So x32 need to get along with that. Maybe > an example would help, so I could understand why you think > this _needs_ to be an error... > X32 won't work with MPX since hardware assumes pointer size is always 64 bit in 64-bit mode with or without address size prefix. MPX depends on correct pointer size to work. I don't want people to use MPX in x32 by accident. -- H.J.