From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 24161 invoked by alias); 12 Oct 2013 15:58:27 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 24151 invoked by uid 89); 12 Oct 2013 15:58:26 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.3 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-ob0-f169.google.com Received: from mail-ob0-f169.google.com (HELO mail-ob0-f169.google.com) (209.85.214.169) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Sat, 12 Oct 2013 15:58:25 +0000 Received: by mail-ob0-f169.google.com with SMTP id wp4so3711749obc.0 for ; Sat, 12 Oct 2013 08:58:23 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.60.52.101 with SMTP id s5mr20679oeo.56.1381593503641; Sat, 12 Oct 2013 08:58:23 -0700 (PDT) Received: by 10.76.75.71 with HTTP; Sat, 12 Oct 2013 08:58:23 -0700 (PDT) In-Reply-To: References: <5254349502000078000F9A3D@nat28.tlf.novell.com> <5254364802000078000F9A5D@nat28.tlf.novell.com> <5255239602000078000F9DE5@nat28.tlf.novell.com> <5256C43B02000078000FA37F@nat28.tlf.novell.com> Date: Sat, 12 Oct 2013 15:58:00 -0000 Message-ID: Subject: Re: [PATCH 5/6] x86/MPX: fix operand size handling From: "H.J. Lu" To: Jan Beulich Cc: kirill.yukhin@intel.com, Binutils Content-Type: text/plain; charset=ISO-8859-1 X-IsSubscribed: yes X-SW-Source: 2013-10/txt/msg00206.txt.bz2 On Thu, Oct 10, 2013 at 8:14 AM, H.J. Lu wrote: > On Thu, Oct 10, 2013 at 6:14 AM, Jan Beulich wrote: >>>>> On 09.10.13 at 17:51, "H.J. Lu" wrote: >>> On Wed, Oct 9, 2013 at 12:36 AM, Jan Beulich wrote: >>>>>>> On 08.10.13 at 17:45, "H.J. Lu" wrote: >>>>> On Tue, Oct 8, 2013 at 7:43 AM, Jan Beulich wrote: >>>>>> All MPX instructions in 64-bit mode ignore REX.W, which means we neither >>>>>> need to encode this bit nor should disassemble with 32-bit register >>>>>> operands. >>>>>> >>>>>> No MPX instructions would ever take a 16-bit register operand. >>>>>> >>>>>> gas/ >>>>>> 2013-10-08 Jan Beulich >>>>>> >>>>>> * tc-i386.c (process_suffix): Warn about 32-bit register operands >>>>>> to MPX instructions in 64-bit mode. >>>>> >>>>> I think it should be an error. >>>> >>>> I can certainly change that - a warning just seemed a better match >>>> to hardware ignoring operand size here. >>> >>> We can use separate entries with Reg32 for CpuNo64 and Reg64 for Cpu64, >>> similar to mov with debug registers. Let's do that instead. >> >> Here's the updated patch. >> >> Jan >> >> General purpose register operands of MPX instructions can only ever be >> native size ones. >> >> opcodes/ >> 2013-10-08 Jan Beulich >> >> * i386-dis.c (intel_operand_size): Move v_bnd_mode alongside the >> default case. >> (OP_E_register): Move v_bnd_mode alongside m_mode. >> * i386-opc.tbl (bndcl, bndcu, bndcn): Split 32- and 64-bit variants. >> Drop Reg16 and Disp16. Add NoRex64. >> (bndmk, bndmov, bndldx, bndstx): Drop Disp16. >> * i386-tbl.h: Re-generate. >> > > It is OK. > I checked it in with testcase updates. Thanks. -- H.J.