From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oa1-x36.google.com (mail-oa1-x36.google.com [IPv6:2001:4860:4864:20::36]) by sourceware.org (Postfix) with ESMTPS id 6AC1B3858CDA for ; Wed, 30 Nov 2022 00:00:52 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 6AC1B3858CDA Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-oa1-x36.google.com with SMTP id 586e51a60fabf-12c8312131fso19146805fac.4 for ; Tue, 29 Nov 2022 16:00:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=WvuZ8vhU9BBvN1HTrjNOPb8AxLfJVfBS+at/l2/S5Eg=; b=A8ll1bRxPt/vWUcqAguUQ3BsGDsEA+C2jQ8rZsyFfW6b2SM6jyYeAcG66joGQNPiou 7MRRYEEYqFStyI7InBeKxsNcH0nKadmeQzSwRkxz3VVU3npWjXRiP0twbpGfurkErVlS dup8xAvDbXMtH8thh6YmBGwCF0dp/25XAgiqCAVAVHYfnkorxbQsFTXLJdNaHcWJmMin /JOEPCihekd998qARYh5N6rZOvvVWVbXWNif1BctXBjKkJkqWrEgRyt8zafMTfpfzum/ YzFGjlPdyRSEx5D0wwTbj0FFf9mDz6yYJROVCkhC/dirzK3Y7DkvaNtdNdC7t6p/UKbE JMpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=WvuZ8vhU9BBvN1HTrjNOPb8AxLfJVfBS+at/l2/S5Eg=; b=KhtbvDvTB8IqV9HcdVtf5rf4sDLC72VrHtqpkiDWFyC756kT8wvenmgjtAjRMcBldx p7hp/NNR7PX8nVS0EyfCqlibw1rpKpMdB7XLn0K0Qz6OuLurrR/Nkovs0YvvozuEYYx5 xuPixgF1IgMQmzJxd9L6XZOYncUvVwv2N3xVL24DBfEq4lOxshMrr49/oe3Qz2Q3q/E4 p+m3savyQ3mXVHXxlVKLbgwyRifpHvsSF9bwWJbct4j2bbUoWcH3BX7tpKyqp6qg3BG9 FFuKiFbxsdOpqVYufNsTPB8jGLPZdaxgci3hlI6Y5Pqu2SpOX1fLbH/oSEAOZrUZDCVI VuSA== X-Gm-Message-State: ANoB5plQ25ttarrzvwtyZGjiRTjhcteVmKXRSics3oOCW5CaJE+GNlUx 8jT3KKNUm62yV2ubBbLVSIZR0ZUqHjq8sBU18Iz8i0Ly X-Google-Smtp-Source: AA0mqf6dp3jLVw8A7/K+m8yX6r/LNdE2BEs2Fl2p0P0rdMYYQpO0PsG+1cn8uNdEDYqkb82ZDb7hC7o6gYPdRfCKsA8= X-Received: by 2002:a05:6871:4501:b0:13c:5da4:7229 with SMTP id nj1-20020a056871450100b0013c5da47229mr26806455oab.266.1669766450214; Tue, 29 Nov 2022 16:00:50 -0800 (PST) MIME-Version: 1.0 References: <0ef86245-7f0d-ef4e-957a-4086eb54ef43@suse.com> In-Reply-To: <0ef86245-7f0d-ef4e-957a-4086eb54ef43@suse.com> From: "H.J. Lu" Date: Tue, 29 Nov 2022 16:00:14 -0800 Message-ID: Subject: Re: [PATCH 2/3] x86: drop FloatR To: Jan Beulich Cc: Binutils Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-3017.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Thu, Nov 24, 2022 at 12:57 AM Jan Beulich wrote: > > There are just 4 templates using it, which can be easily identified by > other means, as D is set only on a very limited number of FPU templates. > Also move the respective conditional out of the code path taken by all > "reverse match" insns (it probably should have been this way already > before, to avoid the one conditional in the common case). > > With this the templates which had FloatR dropped no longer differ from > their AT&T syntax + mnemonic counterparts - the only difference is now > which of the two would be recognized. For this, however, we don't need > two templates - we can simply arrange the condition for setting > Opcode_FloatR accordingly. > > --- a/gas/config/tc-i386.c > +++ b/gas/config/tc-i386.c > @@ -6800,12 +6800,18 @@ match_template (char mnem_suffix) > specific_error = progress (i.error); > continue; > } > - /* found_reverse_match holds which of D or FloatR > + /* found_reverse_match holds which variant of D > we've found. */ > if (!t->opcode_modifier.d) > found_reverse_match = 0; > else if (operand_types[0].bitfield.tbyte) > - found_reverse_match = Opcode_FloatD; > + { > + found_reverse_match = Opcode_FloatD; > + /* FSUB{,R} and FDIV{,R} may need a 2nd bit flipped. */ > + if ((t->base_opcode & 0x20) > + && (intel_syntax || intel_mnemonic)) > + found_reverse_match |= Opcode_FloatR; > + } > else if (t->opcode_modifier.vexsources) > { > found_reverse_match = Opcode_VexW; > @@ -6820,8 +6826,6 @@ match_template (char mnem_suffix) > ? Opcode_ExtD : Opcode_SIMD_IntD; > else > found_reverse_match = Opcode_D; > - if (t->opcode_modifier.floatr) > - found_reverse_match |= Opcode_FloatR; > } > else > { > --- a/opcodes/i386-gen.c > +++ b/opcodes/i386-gen.c > @@ -731,7 +731,6 @@ static bitfield opcode_modifiers[] = > BITFIELD (Modrm), > BITFIELD (Jump), > BITFIELD (FloatMF), > - BITFIELD (FloatR), > BITFIELD (Size), > BITFIELD (CheckRegSize), > BITFIELD (OperandConstraint), > --- a/opcodes/i386-opc.h > +++ b/opcodes/i386-opc.h > @@ -487,8 +487,6 @@ enum > Jump, > /* FP insn memory format bit, sized by 0x4 */ > FloatMF, > - /* src/dest swap for floats. */ > - FloatR, > /* needs size prefix if in 32-bit mode */ > #define SIZE16 1 > /* needs size prefix if in 16-bit mode */ > @@ -743,7 +741,6 @@ typedef struct i386_opcode_modifier > unsigned int modrm:1; > unsigned int jump:3; > unsigned int floatmf:1; > - unsigned int floatr:1; > unsigned int size:2; > unsigned int checkregsize:1; > unsigned int operandconstraint:4; > --- a/opcodes/i386-opc.tbl > +++ b/opcodes/i386-opc.tbl > @@ -694,11 +694,10 @@ faddp, 0xdec0, None, CpuFP, NoSuf|Ugh, { > > // subtract > fsub, 0xd8e0, None, CpuFP, NoSuf, { FloatReg } > -fsub, 0xd8e0, None, CpuFP, D|NoSuf|ATTMnemonic|ATTSyntax, { FloatReg, FloatAcc } > +fsub, 0xd8e0, None, CpuFP, D|NoSuf, { FloatReg, FloatAcc } > // alias for fsubp > fsub, 0xdee1, None, CpuFP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {} > fsub, 0xdee9, None, CpuFP, NoSuf|Ugh|ATTMnemonic, {} > -fsub, 0xd8e0, None, CpuFP, NoSuf|D|FloatR, { FloatReg, FloatAcc } > fsub, 0xd8, 4, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex } > fisub, 0xde, 4, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex } > > @@ -711,11 +710,10 @@ fsubp, 0xdee9, None, CpuFP, NoSuf, {} > > // subtract reverse > fsubr, 0xd8e8, None, CpuFP, NoSuf, { FloatReg } > -fsubr, 0xd8e8, None, CpuFP, D|NoSuf|ATTMnemonic|ATTSyntax, { FloatReg, FloatAcc } > +fsubr, 0xd8e8, None, CpuFP, D|NoSuf, { FloatReg, FloatAcc } > // alias for fsubrp > fsubr, 0xdee9, None, CpuFP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {} > fsubr, 0xdee1, None, CpuFP, NoSuf|Ugh|ATTMnemonic, {} > -fsubr, 0xd8e8, None, CpuFP, NoSuf|D|FloatR, { FloatReg, FloatAcc } > fsubr, 0xd8, 5, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex } > fisubr, 0xde, 5, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex } > > @@ -741,11 +739,10 @@ fmulp, 0xdec8, None, CpuFP, NoSuf|Ugh, { > > // divide > fdiv, 0xd8f0, None, CpuFP, NoSuf, { FloatReg } > -fdiv, 0xd8f0, None, CpuFP, D|NoSuf|ATTMnemonic|ATTSyntax, { FloatReg, FloatAcc } > +fdiv, 0xd8f0, None, CpuFP, D|NoSuf, { FloatReg, FloatAcc } > // alias for fdivp > fdiv, 0xdef1, None, CpuFP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {} > fdiv, 0xdef9, None, CpuFP, NoSuf|Ugh|ATTMnemonic, {} > -fdiv, 0xd8f0, None, CpuFP, NoSuf|D|FloatR, { FloatReg, FloatAcc } > fdiv, 0xd8, 6, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex } > fidiv, 0xde, 6, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex } > > @@ -758,11 +755,10 @@ fdivp, 0xdef9, None, CpuFP, NoSuf, {} > > // divide reverse > fdivr, 0xd8f8, None, CpuFP, NoSuf, { FloatReg } > -fdivr, 0xd8f8, None, CpuFP, D|NoSuf|ATTMnemonic|ATTSyntax, { FloatReg, FloatAcc } > +fdivr, 0xd8f8, None, CpuFP, D|NoSuf, { FloatReg, FloatAcc } > // alias for fdivrp > fdivr, 0xdef9, None, CpuFP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {} > fdivr, 0xdef1, None, CpuFP, NoSuf|Ugh|ATTMnemonic, {} > -fdivr, 0xd8f8, None, CpuFP, NoSuf|D|FloatR, { FloatReg, FloatAcc } > fdivr, 0xd8, 7, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex } > fidivr, 0xde, 7, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex } > > OK. Thanks. -- H.J.