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From: "H.J. Lu" <hjl.tools@gmail.com>
Date: Fri, 5 Aug 2022 16:07:05 -0700
Message-ID: <CAMe9rOoJK1K5tqWJ7ybm=DJF1pC2Q2767gT_KTg7RYM-83qKXw@mail.gmail.com>
Subject: Re: [PATCH 07/12] x86: template-ize packed/scalar vector floating
 point insns
To: Jan Beulich <jbeulich@suse.com>, Lili Cui <lili.cui@intel.com>,
 haochen.jiang@intel.com
Cc: Binutils <binutils@sourceware.org>
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On Fri, Aug 5, 2022 at 5:24 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> The vast majority of vector FP insns comes in single/double pairs. Many
> pairs follow certain encoding patterns. Introduce an "sd" template to
> reduce redundancy. Similarly, to further cover similarities between
> AVX512F and AVX512-FP16, introduce an "sdh" template.
>
> For element-size Disp8 shift generalize i386-gen's broadcast size
> determination, allowing Disp8MemShift to be specified without an operand
> in the affected templated templates. While doing the adjustment also
> eliminate an unhelpful (lost information) diagnostic combined with a use
> after free in what is now get_element_size().
>
> Note that in the course of the conversion
> - the AVX512F form of VMOVUPD has a stray (leftover) Load attribute
>   dropped,
> - VMOVSH has a benign IgnoreSize added (the attribute is still strictly
>   necessary for VMOVSD, and necessary for VMOVSS as long as we permit
>   strange combinations like "-march=3Di286+avx"),
> - VFPCLASSPH is properly split to separate AT&T and Intel syntax forms,
>   matching VFPCLASSP{S,D}.
> ---
> For VCOMPRESSP{S,D} and VEXPANDP{S,D} the conversion could only be done
> if we allowed Dword/Qword on the memory operands. Imo permitting this
> makes sense anyway (as the memory operands aren't full [XYZ]mmword
> ones), but such a functional change should probably be a separate patch.
>
> Extending this to SSE/SSE2 may be possible, using something like
> <fp:...:cpu:..., s:...:<sse:cpu>:..., d:...:<sse2:cpu>:...>, but would
> presumably require adjustments to i386-gen's parsing (for the embedded
> template reference). For now I'm undecided whether that's worth it.
>
> --- a/opcodes/i386-gen.c
> +++ b/opcodes/i386-gen.c
> @@ -1111,18 +1111,21 @@ output_opcode_modifier (FILE *table, bit
>    fprintf (table, "%d },\n", modifier[i].value);
>  }
>
> +/* Returns LOG2 of element size.  */
>  static int
> -adjust_broadcast_modifier (char **opnd)
> +get_element_size (char **opnd, int lineno)
>  {
>    char *str, *next, *last, *op;
> -  int bcst_type =3D INT_MAX;
> +  const char *full =3D opnd[0];
> +  int elem_size =3D INT_MAX;
>
> -  /* Skip the immediate operand.  */
> -  op =3D opnd[0];
> -  if (strcasecmp(op, "Imm8") =3D=3D 0)
> -    op =3D opnd[1];
> +  /* Find the memory operand.  */
> +  while (full !=3D NULL && strstr(full, "BaseIndex") =3D=3D NULL)
> +    full =3D *++opnd;
> +  if (full =3D=3D NULL)
> +    fail (_("%s: %d: no memory operand\n"), filename, lineno);
>
> -  op =3D xstrdup (op);
> +  op =3D xstrdup (full);
>    last =3D op + strlen (op);
>    for (next =3D op; next && next < last; )
>      {
> @@ -1131,34 +1134,34 @@ adjust_broadcast_modifier (char **opnd)
>         {
>           if (strcasecmp(str, "Byte") =3D=3D 0)
>             {
> -             /* The smalest broadcast type, no need to check
> +             /* The smallest element size, no need to check
>                  further.  */
> -             bcst_type =3D BYTE_BROADCAST;
> +             elem_size =3D 0;
>               break;
>             }
>           else if (strcasecmp(str, "Word") =3D=3D 0)
>             {
> -             if (bcst_type > WORD_BROADCAST)
> -               bcst_type =3D WORD_BROADCAST;
> +             if (elem_size > 1)
> +               elem_size =3D 1;
>             }
>           else if (strcasecmp(str, "Dword") =3D=3D 0)
>             {
> -             if (bcst_type > DWORD_BROADCAST)
> -               bcst_type =3D DWORD_BROADCAST;
> +             if (elem_size > 2)
> +               elem_size =3D 2;
>             }
>           else if (strcasecmp(str, "Qword") =3D=3D 0)
>             {
> -             if (bcst_type > QWORD_BROADCAST)
> -               bcst_type =3D QWORD_BROADCAST;
> +             if (elem_size > 3)
> +               elem_size =3D 3;
>             }
>         }
>      }
>    free (op);
>
> -  if (bcst_type =3D=3D INT_MAX)
> -    fail (_("unknown broadcast operand: %s\n"), op);
> +  if (elem_size =3D=3D INT_MAX)
> +    fail (_("%s: %d: unknown element size: %s\n"), filename, lineno, ful=
l);
>
> -  return bcst_type;
> +  return elem_size;
>  }
>
>  static void
> @@ -1185,7 +1188,9 @@ process_i386_opcode_modifier (FILE *tabl
>             {
>               int val =3D 1;
>               if (strcasecmp(str, "Broadcast") =3D=3D 0)
> -               val =3D adjust_broadcast_modifier (opnd);
> +               val =3D get_element_size (opnd, lineno) + BYTE_BROADCAST;
> +             else if (strcasecmp(str, "Disp8MemShift") =3D=3D 0)
> +               val =3D get_element_size (opnd, lineno);
>
>               set_bitfield (str, modifiers, val, ARRAY_SIZE (modifiers),
>                             lineno);
> --- a/opcodes/i386-opc.tbl
> +++ b/opcodes/i386-opc.tbl
> @@ -1334,19 +1334,14 @@ pabsd<ssse3>, 0x<ssse3:pfx>0f381e, None,
>  // SSE4.1 instructions.
>
>  <sse41:cpu:attr:scal:vvvv, $avx:CpuAVX:Vex128|VexW0|SSE2AVX:VexLIG|VexW0=
|SSE2AVX:VexVVVV, $sse:CpuSSE4_1:::>
> +<sd:ppfx:spfx:opc:vexw:elem:scal, s::f3:0:VexW0:Dword:IgnoreSize, d:66:f=
2:1:VexW1:Qword:NoRex64>
>
> -blendpd<sse41>, 0x660f3a0d, None, <sse41:cpu>, Modrm|<sse41:attr>|<sse41=
:vvvv>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Uns=
pecified|BaseIndex, RegXMM }
> -blendps<sse41>, 0x660f3a0c, None, <sse41:cpu>, Modrm|<sse41:attr>|<sse41=
:vvvv>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Uns=
pecified|BaseIndex, RegXMM }
> -blendvpd, 0x664b, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=3D1|VexW=3D1=
|VexSources=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, {=
 Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM }
> -blendvpd, 0x664b, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=3D1|VexW=3D1=
|VexSources=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Implicit1s=
tXmm0|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
> -blendvpd, 0x660f3815, None, CpuSSE4_1, Modrm|No_bSuf|No_wSuf|No_lSuf|No_=
sSuf|No_qSuf|No_ldSuf, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM =
}
> -blendvpd, 0x660f3815, None, CpuSSE4_1, Modrm|No_bSuf|No_wSuf|No_lSuf|No_=
sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
> -blendvps, 0x664a, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=3D1|VexW=3D1=
|VexSources=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, {=
 Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM }
> -blendvps, 0x664a, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=3D1|VexW=3D1=
|VexSources=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Implicit1s=
tXmm0|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
> -blendvps, 0x660f3814, None, CpuSSE4_1, Modrm|No_bSuf|No_wSuf|No_lSuf|No_=
sSuf|No_qSuf|No_ldSuf, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM =
}
> -blendvps, 0x660f3814, None, CpuSSE4_1, Modrm|No_bSuf|No_wSuf|No_lSuf|No_=
sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
> -dppd<sse41>, 0x660f3a41, None, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:vv=
vv>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspec=
ified|BaseIndex, RegXMM }
> -dpps<sse41>, 0x660f3a40, None, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:vv=
vv>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspec=
ified|BaseIndex, RegXMM }
> +blendp<sd><sse41>, 0x660f3a0c | <sd:opc>, None, <sse41:cpu>, Modrm|<sse4=
1:attr>|<sse41:vvvv>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Im=
m8, RegXMM|Unspecified|BaseIndex, RegXMM }
> +blendvp<sd>, 0x664a | <sd:opc>, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVV=
V=3D1|VexW=3D1|VexSources=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ld=
Suf|SSE2AVX, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM }
> +blendvp<sd>, 0x664a | <sd:opc>, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVV=
V=3D1|VexW=3D1|VexSources=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ld=
Suf|Implicit1stXmm0|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
> +blendvp<sd>, 0x660f3814 | <sd:opc>, None, CpuSSE4_1, Modrm|No_bSuf|No_wS=
uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Acc|Xmmword, RegXMM|Unspecified|Base=
Index, RegXMM }
> +blendvp<sd>, 0x660f3814 | <sd:opc>, None, CpuSSE4_1, Modrm|No_bSuf|No_wS=
uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM=
 }
> +dpp<sd><sse41>, 0x660f3a40 | <sd:opc>, None, <sse41:cpu>, Modrm|<sse41:a=
ttr>|<sse41:vvvv>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8,=
 RegXMM|Unspecified|BaseIndex, RegXMM }
>  extractps, 0x6617, None, CpuAVX, Modrm|Vex|Space0F3A|VexWIG|IgnoreSize|N=
o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM, Re=
g32|Dword|Unspecified|BaseIndex }
>  extractps, 0x6617, None, CpuAVX|Cpu64, RegMem|Vex|Space0F3A|VexWIG|No_bS=
uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM, Reg64 =
}
>  extractps, 0x660f3a17, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf=
|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|=
BaseIndex }
> @@ -1397,10 +1392,8 @@ pmovzxdq<sse41>, 0x660f3835, None, <sse4
>  pmuldq<sse41>, 0x660f3828, None, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:=
vvvv>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecifie=
d|BaseIndex, RegXMM }
>  pmulld<sse41>, 0x660f3840, None, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:=
vvvv>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecifie=
d|BaseIndex, RegXMM }
>  ptest<sse41>, 0x660f3817, None, <sse41:cpu>, Modrm|<sse41:attr>|No_bSuf|=
No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, R=
egXMM }
> -roundpd<sse41>, 0x660f3a09, None, <sse41:cpu>, Modrm|<sse41:attr>|No_bSu=
f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|Base=
Index, RegXMM }
> -roundps<sse41>, 0x660f3a08, None, <sse41:cpu>, Modrm|<sse41:attr>|No_bSu=
f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|Base=
Index, RegXMM }
> -roundsd<sse41>, 0x660f3a0b, None, <sse41:cpu>, Modrm|<sse41:scal>|<sse41=
:vvvv>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, Qw=
ord|Unspecified|BaseIndex|RegXMM, RegXMM }
> -roundss<sse41>, 0x660f3a0a, None, <sse41:cpu>, Modrm|<sse41:scal>|<sse41=
:vvvv>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IgnoreSize, { Imm8,=
 Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
> +roundp<sd><sse41>, 0x660f3a08 | <sd:opc>, None, <sse41:cpu>, Modrm|<sse4=
1:attr>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Un=
specified|BaseIndex, RegXMM }
> +rounds<sd><sse41>, 0x660f3a0a | <sd:opc>, None, <sse41:cpu>, Modrm|<sse4=
1:scal>|<sse41:vvvv>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|<sd:s=
cal>, { Imm8, <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM }
>
>  // SSE4.2 instructions.
>
> @@ -1479,33 +1472,22 @@ gf2p8mulb<gfni>, 0x660f38cf, None, <gfni
>      nge_uq:19:, ngt_uq:1a:, false_os:1b:C, neq_os:1c:C, ge_oq:1d:, gt_oq=
:1e:, +
>      true_us:1f:C>
>
> -vaddpd, 0x6658, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|Check=
RegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|Bas=
eIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vaddps, 0x58, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|CheckRe=
gSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseI=
ndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vaddsd, 0xf258, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexVVVV|VexWIG|No_bS=
uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|=
RegXMM, RegXMM, RegXMM }
> -vaddss, 0xf358, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexVVVV|VexWIG|No_bS=
uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|=
RegXMM, RegXMM, RegXMM }
> +vaddp<sd>, 0x<sd:ppfx>58, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG=
|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecifi=
ed|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> +vadds<sd>, 0x<sd:spfx>58, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|Vex=
WIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <sd:elem>|Unspecifi=
ed|BaseIndex|RegXMM, RegXMM, RegXMM }
>  vaddsubpd, 0x66d0, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|Ch=
eckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|=
BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
>  vaddsubps, 0xf2d0, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|Ch=
eckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|=
BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vandnpd, 0x6655, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|Chec=
kRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Unspe=
cified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vandnps, 0x55, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|CheckR=
egSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Unspeci=
fied|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vandpd, 0x6654, None, CpuAVX, Modrm|C|Vex|Space0F|VexVVVV=3D1|VexWIG|Che=
ckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|B=
aseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vandps, 0x54, None, CpuAVX, Modrm|C|Vex|Space0F|VexVVVV=3D1|VexWIG|Check=
RegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|Bas=
eIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vblendpd, 0x660d, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=3D1|VexWIG|C=
heckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspe=
cified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vblendps, 0x660c, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=3D1|VexWIG|C=
heckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspe=
cified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vblendvpd, 0x664b, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=3D1|VexW=3D=
1|VexSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ld=
Suf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, R=
egXMM|RegYMM }
> -vblendvps, 0x664a, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=3D1|VexW=3D=
1|VexSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ld=
Suf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, R=
egXMM|RegYMM }
> +vandnp<sd>, 0x<sd:ppfx>55, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWI=
G|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, {=
 Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> +vandp<sd>, 0x<sd:ppfx>54, None, CpuAVX, Modrm|C|Vex|Space0F|VexVVVV|VexW=
IG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspeci=
fied|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> +vblendp<sd>, 0x660c | <sd:opc>, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVV=
V|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { I=
mm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> +vblendvp<sd>, 0x664a | <sd:opc>, None, CpuAVX, Modrm|Vex|Space0F3A|VexVV=
VV|VexW0|VexSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu=
f|No_ldSuf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|Re=
gYMM, RegXMM|RegYMM }
>  vbroadcastf128, 0x661a, None, CpuAVX, Modrm|Vex=3D2|Space0F38|VexW=3D1|N=
o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|Base=
Index, RegYMM }
>  vbroadcastsd, 0x6619, None, CpuAVX, Modrm|Vex=3D2|Space0F38|VexW=3D1|Ign=
oreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecifi=
ed|BaseIndex, RegYMM }
>  vbroadcastss, 0x6618, None, CpuAVX, Modrm|Vex|Space0F38|VexW=3D1|IgnoreS=
ize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|B=
aseIndex, RegXMM|RegYMM }
> -vcmp<avx_frel>pd, 0x66c2, 0x<avx_frel:imm>, CpuAVX, Modrm|<avx_frel:comm=
>|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N=
o_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYM=
M, RegXMM|RegYMM }
> -vcmp<avx_frel>ps, 0xc2, 0x<avx_frel:imm>, CpuAVX, Modrm|<avx_frel:comm>|=
Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_=
qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM,=
 RegXMM|RegYMM }
> -vcmp<avx_frel>sd, 0xf2c2, 0x<avx_frel:imm>, CpuAVX, Modrm|<avx_frel:comm=
>|VexLIG|Space0F|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_=
ldSuf|ImmExt, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
> -vcmp<avx_frel>ss, 0xf3c2, 0x<avx_frel:imm>, CpuAVX, Modrm|<avx_frel:comm=
>|VexLIG|Space0F|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_=
ldSuf|ImmExt, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
> -vcmppd, 0x66c2, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|Check=
RegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecifi=
ed|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vcmpps, 0xc2, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|CheckRe=
gSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified=
|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vcmpsd, 0xf2c2, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexVVVV|VexWIG|No_bS=
uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Qword|Unspecified|Base=
Index|RegXMM, RegXMM, RegXMM }
> -vcmpss, 0xf3c2, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexVVVV|VexWIG|No_bS=
uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|Unspecified|Base=
Index|RegXMM, RegXMM, RegXMM }
> -vcomisd, 0x662f, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexWIG|No_bSuf|No_w=
Suf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM,=
 RegXMM }
> -vcomiss, 0x2f, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexWIG|No_bSuf|No_wSu=
f|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, R=
egXMM }
> +vcmp<avx_frel>p<sd>, 0x<sd:ppfx>c2, 0x<avx_frel:imm>, CpuAVX, Modrm|<avx=
_frel:comm>|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf=
|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|Unspecified|BaseIndex, Re=
gXMM|RegYMM, RegXMM|RegYMM }
> +vcmp<avx_frel>s<sd>, 0x<sd:spfx>c2, 0x<avx_frel:imm>, CpuAVX, Modrm|<avx=
_frel:comm>|VexLIG|Space0F|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N=
o_qSuf|No_ldSuf|ImmExt, { RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, R=
egXMM }
> +vcmpp<sd>, 0x<sd:ppfx>c2, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG=
|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Uns=
pecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> +vcmps<sd>, 0x<sd:spfx>c2, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|Vex=
WIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, <sd:elem>|Uns=
pecified|BaseIndex|RegXMM, RegXMM, RegXMM }
> +vcomis<sd>, 0x<sd:ppfx>2f, None, CpuAVX, Modrm|VexLIG|Space0F|VexWIG|No_=
bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <sd:elem>|Unspecified|Base=
Index|RegXMM, RegXMM }
>  vcvtdq2pd, 0xf3e6, None, CpuAVX, Modrm|Vex128|Space0F|VexWIG|No_bSuf|No_=
wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex=
, RegXMM }
>  vcvtdq2pd, 0xf3e6, None, CpuAVX, Modrm|Vex256|Space0F|VexWIG|No_bSuf|No_=
wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegY=
MM }
>  vcvtdq2ps, 0x5b, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|No_=
bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegX=
MM|RegYMM, RegXMM|RegYMM }
> @@ -1522,10 +1504,8 @@ vcvtps2pd, 0x5a, None, CpuAVX, Modrm|Vex
>  vcvtps2pd, 0x5a, None, CpuAVX, Modrm|Vex256|Space0F|VexWIG|No_bSuf|No_wS=
uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegYMM=
 }
>  vcvtsd2si, 0xf22d, None, CpuAVX, Modrm|Vex=3D3|Space0F|IgnoreSize|No_bSu=
f|No_wSuf|No_sSuf|No_ldSuf|ToDword, { Qword|Unspecified|BaseIndex|RegXMM, R=
eg32|Reg64 }
>  vcvtsd2ss, 0xf25a, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexVVVV|VexWIG|No=
_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseInd=
ex|RegXMM, RegXMM, RegXMM }
> -vcvtsi2sd, 0xf22a, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|IgnoreSize=
|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ATTSyntax, { Reg32|Reg64|Unspecified|Base=
Index, RegXMM, RegXMM }
> -vcvtsi2sd, 0xf22a, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|No_bSuf|No=
_wSuf|No_sSuf|No_ldSuf|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, Re=
gXMM, RegXMM }
> -vcvtsi2ss, 0xf32a, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|IgnoreSize=
|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ATTSyntax, { Reg32|Reg64|Unspecified|Base=
Index, RegXMM, RegXMM }
> -vcvtsi2ss, 0xf32a, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|No_bSuf|No=
_wSuf|No_sSuf|No_ldSuf|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, Re=
gXMM, RegXMM }
> +vcvtsi2s<sd>, 0x<sd:spfx>2a, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|=
IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ATTSyntax, { Reg32|Reg64|Unspec=
ified|BaseIndex, RegXMM, RegXMM }
> +vcvtsi2s<sd>, 0x<sd:spfx>2a, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|=
No_bSuf|No_wSuf|No_sSuf|No_ldSuf|IntelSyntax, { Reg32|Reg64|Unspecified|Bas=
eIndex, RegXMM, RegXMM }
>  vcvtss2sd, 0xf35a, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexVVVV|VexWIG|No=
_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseInd=
ex|RegXMM, RegXMM, RegXMM }
>  vcvtss2si, 0xf32d, None, CpuAVX, Modrm|Vex=3D3|Space0F|No_bSuf|No_wSuf|N=
o_sSuf|No_ldSuf|ToQword, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 =
}
>  vcvttpd2dq, 0x66e6, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|No_bSuf|No_wS=
uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { RegXMM|RegYMM|Unspecifie=
d|BaseIndex, RegXMM }
> @@ -1535,10 +1515,8 @@ vcvttpd2dqy, 0x66e6, None, CpuAVX, Modrm
>  vcvttps2dq, 0xf35b, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|No_bSuf|No_wS=
uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM,=
 RegXMM|RegYMM }
>  vcvttsd2si, 0xf22c, None, CpuAVX, Modrm|Vex=3D3|Space0F|IgnoreSize|No_bS=
uf|No_wSuf|No_sSuf|No_ldSuf|ToDword, { Qword|Unspecified|BaseIndex|RegXMM, =
Reg32|Reg64 }
>  vcvttss2si, 0xf32c, None, CpuAVX, Modrm|Vex=3D3|Space0F|No_bSuf|No_wSuf|=
No_sSuf|No_ldSuf|ToQword, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64=
 }
> -vdivpd, 0x665e, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|Check=
RegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|Bas=
eIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vdivps, 0x5e, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|CheckRe=
gSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseI=
ndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vdivsd, 0xf25e, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexVVVV|VexWIG|No_bS=
uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|=
RegXMM, RegXMM, RegXMM }
> -vdivss, 0xf35e, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexVVVV|VexWIG|No_bS=
uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|=
RegXMM, RegXMM, RegXMM }
> +vdivp<sd>, 0x<sd:ppfx>5e, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG=
|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecifi=
ed|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> +vdivs<sd>, 0x<sd:spfx>5e, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|Vex=
WIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <sd:elem>|Unspecifi=
ed|BaseIndex|RegXMM, RegXMM, RegXMM }
>  vdppd, 0x6641, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=3D1|VexWIG|No_b=
Suf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex=
|RegXMM, RegXMM, RegXMM }
>  vdpps, 0x6640, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=3D1|VexWIG|Chec=
kRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecif=
ied|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
>  vextractf128, 0x6619, None, CpuAVX, Modrm|Vex=3D2|Space0F3A|VexW=3D1|No_=
bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, Unspecified|=
BaseIndex|RegXMM }
> @@ -1553,20 +1531,13 @@ vinsertps, 0x6621, None, CpuAVX, Modrm|V
>  vlddqu, 0xf2f0, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|No_b=
Suf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Ymmword|Unspecified=
|BaseIndex, RegXMM|RegYMM }
>  vldmxcsr, 0xae, 2, CpuAVX, Modrm|Vex128|Space0F|VexWIG|IgnoreSize|No_bSu=
f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex }
>  vmaskmovdqu, 0x66f7, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|No_bSuf|No_w=
Suf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM }
> -vmaskmovpd, 0x662f, None, CpuAVX, Modrm|Vex|Space0F38|VexVVVV=3D1|VexW=
=3D1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXM=
M|RegYMM, RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex }
> -vmaskmovpd, 0x662d, None, CpuAVX, Modrm|Vex|Space0F38|VexVVVV=3D1|VexW=
=3D1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmwo=
rd|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
> -vmaskmovps, 0x662e, None, CpuAVX, Modrm|Vex|Space0F38|VexVVVV=3D1|VexW=
=3D1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXM=
M|RegYMM, RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex }
> -vmaskmovps, 0x662c, None, CpuAVX, Modrm|Vex|Space0F38|VexVVVV=3D1|VexW=
=3D1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmwo=
rd|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
> -vmaxpd, 0x665f, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|Check=
RegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|Bas=
eIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vmaxps, 0x5f, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|CheckRe=
gSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseI=
ndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vmaxsd, 0xf25f, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexVVVV|VexWIG|No_bS=
uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|=
RegXMM, RegXMM, RegXMM }
> -vmaxss, 0xf35f, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexVVVV|VexWIG|No_bS=
uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|=
RegXMM, RegXMM, RegXMM }
> -vminpd, 0x665d, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|Check=
RegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|Bas=
eIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vminps, 0x5d, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|CheckRe=
gSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseI=
ndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vminsd, 0xf25d, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexVVVV|VexWIG|No_bS=
uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|=
RegXMM, RegXMM, RegXMM }
> -vminss, 0xf35d, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexVVVV|VexWIG|No_bS=
uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|=
RegXMM, RegXMM, RegXMM }
> -vmovapd, 0x6628, None, CpuAVX, D|Modrm|Vex|Space0F|VexWIG|CheckRegSize|N=
o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|Re=
gXMM|RegYMM, RegXMM|RegYMM }
> -vmovaps, 0x28, None, CpuAVX, D|Modrm|Vex|Space0F|VexWIG|CheckRegSize|No_=
bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegX=
MM|RegYMM, RegXMM|RegYMM }
> +vmaskmovp<sd>, 0x662e | <sd:opc>, None, CpuAVX, Modrm|Vex|Space0F38|VexV=
VVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { =
RegXMM|RegYMM, RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex }
> +vmaskmovp<sd>, 0x662c | <sd:opc>, None, CpuAVX, Modrm|Vex|Space0F38|VexV=
VVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { =
Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
> +vmaxp<sd>, 0x<sd:ppfx>5f, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG=
|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecifi=
ed|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> +vmaxs<sd>, 0x<sd:spfx>5f, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|Vex=
WIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <sd:elem>|Unspecifi=
ed|BaseIndex|RegXMM, RegXMM, RegXMM }
> +vminp<sd>, 0x<sd:ppfx>5d, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG=
|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecifi=
ed|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> +vmins<sd>, 0x<sd:spfx>5d, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|Vex=
WIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <sd:elem>|Unspecifi=
ed|BaseIndex|RegXMM, RegXMM, RegXMM }
> +vmovap<sd>, 0x<sd:ppfx>28, None, CpuAVX, D|Modrm|Vex|Space0F|VexWIG|Chec=
kRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|Ba=
seIndex|RegXMM|RegYMM, RegXMM|RegYMM }
>  // vmovd really shouldn't allow for 64bit operand (vmovq is the right
>  // mnemonic for copying between Reg64/Mem64 and RegXMM, as is mandated
>  // by Intel AVX spec).  To avoid extra template in gcc x86 backend and
> @@ -1579,39 +1550,27 @@ vmovddup, 0xf212, None, CpuAVX, Modrm|Ve
>  vmovdqa, 0x666f, None, CpuAVX, D|Modrm|Vex|Space0F|VexWIG|CheckRegSize|N=
o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|Re=
gXMM|RegYMM, RegXMM|RegYMM }
>  vmovdqu, 0xf36f, None, CpuAVX, D|Modrm|Vex|Space0F|VexWIG|CheckRegSize|N=
o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|Re=
gXMM|RegYMM, RegXMM|RegYMM }
>  vmovhlps, 0x12, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|No_bS=
uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
> -vmovhpd, 0x6616, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|Igno=
reSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecifie=
d|BaseIndex, RegXMM, RegXMM }
> -vmovhpd, 0x6617, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|IgnoreSize|No_bS=
uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|Ba=
seIndex }
> -vmovhps, 0x16, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|Ignore=
Size|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|=
BaseIndex, RegXMM, RegXMM }
> -vmovhps, 0x17, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|IgnoreSize|No_bSuf=
|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|Base=
Index }
> +vmovhp<sd>, 0x<sd:ppfx>16, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWI=
G|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unsp=
ecified|BaseIndex, RegXMM, RegXMM }
> +vmovhp<sd>, 0x<sd:ppfx>17, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|Ignore=
Size|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unsp=
ecified|BaseIndex }
>  vmovlhps, 0x16, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|No_bS=
uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
> -vmovlpd, 0x6612, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|Igno=
reSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecifie=
d|BaseIndex, RegXMM, RegXMM }
> -vmovlpd, 0x6613, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|IgnoreSize|No_bS=
uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|Ba=
seIndex }
> -vmovlps, 0x12, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|Ignore=
Size|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|=
BaseIndex, RegXMM, RegXMM }
> -vmovlps, 0x13, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|IgnoreSize|No_bSuf=
|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|Base=
Index }
> -vmovmskpd, 0x6650, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|No_bSuf|No_wSu=
f|No_sSuf|No_ldSuf, { RegXMM|RegYMM, Reg32|Reg64 }
> -vmovmskps, 0x50, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|No_bSuf|No_wSuf|=
No_sSuf|No_ldSuf, { RegXMM|RegYMM, Reg32|Reg64 }
> +vmovlp<sd>, 0x<sd:ppfx>12, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWI=
G|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unsp=
ecified|BaseIndex, RegXMM, RegXMM }
> +vmovlp<sd>, 0x<sd:ppfx>13, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|Ignore=
Size|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unsp=
ecified|BaseIndex }
> +vmovmskp<sd>, 0x<sd:ppfx>50, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|No_b=
Suf|No_wSuf|No_sSuf|No_ldSuf, { RegXMM|RegYMM, Reg32|Reg64 }
>  vmovntdq, 0x66e7, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|No=
_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Xmmword|Ym=
mword|Unspecified|BaseIndex }
>  vmovntdqa, 0x662a, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexWIG|Chec=
kRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Ymmwor=
d|Unspecified|BaseIndex, RegXMM|RegYMM }
> -vmovntpd, 0x662b, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|No=
_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Xmmword|Ym=
mword|Unspecified|BaseIndex }
> -vmovntps, 0x2b, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|No_b=
Suf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Xmmword|Ymmw=
ord|Unspecified|BaseIndex }
> +vmovntp<sd>, 0x<sd:ppfx>2b, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|Check=
RegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, =
Xmmword|Ymmword|Unspecified|BaseIndex }
>  vmovq, 0xf37e, None, CpuAVX, Load|Modrm|Vex=3D1|Space0F|VexWIG|No_bSuf|N=
o_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegX=
MM, RegXMM }
>  vmovq, 0x66d6, None, CpuAVX, Modrm|Vex=3D1|Space0F|VexWIG|No_bSuf|No_wSu=
f|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|R=
egXMM }
>  vmovq, 0x666e, None, CpuAVX|Cpu64, D|Modrm|Vex=3D1|Space0F|VexW=3D2|Igno=
reSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64|Uns=
pecified|BaseIndex, RegXMM }
> -vmovsd, 0xf210, None, CpuAVX, D|Modrm|Vex=3D3|Space0F|VexWIG|IgnoreSize|=
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseI=
ndex, RegXMM }
> -vmovsd, 0xf210, None, CpuAVX, D|Modrm|Vex=3D3|Space0F|VexVVVV=3D1|VexWIG=
|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM=
 }
> +vmovs<sd>, 0x<sd:spfx>10, None, CpuAVX, D|Modrm|VexLIG|Space0F|VexWIG|Ig=
noreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <sd:elem>|Unsp=
ecified|BaseIndex, RegXMM }
> +vmovs<sd>, 0x<sd:spfx>10, None, CpuAVX, D|Modrm|VexLIG|Space0F|VexVVVV|V=
exWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, R=
egXMM }
>  vmovshdup, 0xf316, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|N=
o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|Re=
gXMM|RegYMM, RegXMM|RegYMM }
>  vmovsldup, 0xf312, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|N=
o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|Re=
gXMM|RegYMM, RegXMM|RegYMM }
> -vmovss, 0xf310, None, CpuAVX, D|Modrm|Vex=3D3|Space0F|VexWIG|IgnoreSize|=
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseI=
ndex, RegXMM }
> -vmovss, 0xf310, None, CpuAVX, D|Modrm|Vex=3D3|Space0F|VexVVVV=3D1|VexWIG=
|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM=
 }
> -vmovupd, 0x6610, None, CpuAVX, D|Modrm|Vex|Space0F|VexWIG|CheckRegSize|N=
o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|Re=
gXMM|RegYMM, RegXMM|RegYMM }
> -vmovups, 0x10, None, CpuAVX, D|Modrm|Vex|Space0F|VexWIG|CheckRegSize|No_=
bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegX=
MM|RegYMM, RegXMM|RegYMM }
> +vmovup<sd>, 0x<sd:ppfx>10, None, CpuAVX, D|Modrm|Vex|Space0F|VexWIG|Chec=
kRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|Ba=
seIndex|RegXMM|RegYMM, RegXMM|RegYMM }
>  vmpsadbw, 0x6642, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F3A|VexVVVV|VexW=
IG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, U=
nspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vmulpd, 0x6659, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|Check=
RegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|Bas=
eIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vmulps, 0x59, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|CheckRe=
gSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseI=
ndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vmulsd, 0xf259, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexVVVV|VexWIG|No_bS=
uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|=
RegXMM, RegXMM, RegXMM }
> -vmulss, 0xf359, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexVVVV|VexWIG|No_bS=
uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|=
RegXMM, RegXMM, RegXMM }
> -vorpd, 0x6656, None, CpuAVX, Modrm|C|Vex|Space0F|VexVVVV=3D1|VexWIG|Chec=
kRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|Ba=
seIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vorps, 0x56, None, CpuAVX, Modrm|C|Vex|Space0F|VexVVVV=3D1|VexWIG|CheckR=
egSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|Base=
Index|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> +vmulp<sd>, 0x<sd:ppfx>59, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG=
|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecifi=
ed|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> +vmuls<sd>, 0x<sd:spfx>59, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|Vex=
WIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <sd:elem>|Unspecifi=
ed|BaseIndex|RegXMM, RegXMM, RegXMM }
> +vorp<sd>, 0x<sd:ppfx>56, None, CpuAVX, Modrm|C|Vex|Space0F|VexVVVV|VexWI=
G|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecif=
ied|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
>  vpabsb, 0x661c, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexWIG|CheckRe=
gSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseI=
ndex|RegXMM|RegYMM, RegXMM|RegYMM }
>  vpabsd, 0x661e, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexWIG|CheckRe=
gSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseI=
ndex|RegXMM|RegYMM, RegXMM|RegYMM }
>  vpabsw, 0x661d, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexWIG|CheckRe=
gSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseI=
ndex|RegXMM|RegYMM, RegXMM|RegYMM }
> @@ -1649,10 +1608,8 @@ vpcmpgtw, 0x6665, None, CpuAVX|CpuAVX2,
>  vpcmpistri, 0x6663, None, CpuAVX, Modrm|Vex|Space0F3A|VexWIG|No_bSuf|No_=
wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM=
, RegXMM }
>  vpcmpistrm, 0x6662, None, CpuAVX, Modrm|Vex|Space0F3A|VexWIG|No_bSuf|No_=
wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM=
, RegXMM }
>  vperm2f128, 0x6606, None, CpuAVX, Modrm|Vex=3D2|Space0F3A|VexVVVV=3D1|Ve=
xW=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecifie=
d|BaseIndex|RegYMM, RegYMM, RegYMM }
> -vpermilpd, 0x660d, None, CpuAVX, Modrm|Vex|Space0F38|VexVVVV=3D1|VexW=3D=
1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecif=
ied|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vpermilpd, 0x6605, None, CpuAVX, Modrm|Vex|Space0F3A|VexW=3D1|CheckRegSi=
ze|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|Ba=
seIndex|RegXMM|RegYMM, RegXMM|RegYMM }
> -vpermilps, 0x660c, None, CpuAVX, Modrm|Vex|Space0F38|VexVVVV=3D1|VexW=3D=
1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecif=
ied|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vpermilps, 0x6604, None, CpuAVX, Modrm|Vex|Space0F3A|VexW=3D1|CheckRegSi=
ze|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|Ba=
seIndex|RegXMM|RegYMM, RegXMM|RegYMM }
> +vpermilp<sd>, 0x660c | <sd:opc>, None, CpuAVX, Modrm|Vex|Space0F38|VexVV=
VV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { U=
nspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> +vpermilp<sd>, 0x6604 | <sd:opc>, None, CpuAVX, Modrm|Vex|Space0F3A|VexW0=
|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Uns=
pecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
>  vpextrb, 0x6614, None, CpuAVX, RegMem|Vex|Space0F3A|VexWIG|No_bSuf|No_wS=
uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64 }
>  vpextrb, 0x6614, None, CpuAVX, Modrm|Vex|Space0F3A|VexWIG|No_bSuf|No_wSu=
f|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Byte|Unspecified|BaseIn=
dex }
>  vpextrd, 0x6616, None, CpuAVX, Modrm|Vex|Space0F3A|IgnoreSize|No_bSuf|No=
_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Dword|Unspeci=
fied|BaseIndex }
> @@ -1754,33 +1711,21 @@ vpunpcklwd, 0x6661, None, CpuAVX|CpuAVX2
>  vpxor, 0x66ef, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|=
CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { U=
nspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
>  vrcpps, 0x53, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|No_bSu=
f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|=
RegYMM, RegXMM|RegYMM }
>  vrcpss, 0xf353, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexVVVV|VexWIG|No_bS=
uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|=
RegXMM, RegXMM, RegXMM }
> -vroundpd, 0x6609, None, CpuAVX, Modrm|Vex|Space0F3A|VexWIG|CheckRegSize|=
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseI=
ndex|RegXMM|RegYMM, RegXMM|RegYMM }
> -vroundps, 0x6608, None, CpuAVX, Modrm|Vex|Space0F3A|VexWIG|CheckRegSize|=
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseI=
ndex|RegXMM|RegYMM, RegXMM|RegYMM }
> -vroundsd, 0x660b, None, CpuAVX, Modrm|Vex=3D3|Space0F3A|VexVVVV|VexWIG|N=
o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Qword|Unspecified|=
BaseIndex|RegXMM, RegXMM, RegXMM }
> -vroundss, 0x660a, None, CpuAVX, Modrm|Vex=3D3|Space0F3A|VexVVVV|VexWIG|N=
o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|Unspecified|=
BaseIndex|RegXMM, RegXMM, RegXMM }
> +vroundp<sd>, 0x6608 | <sd:opc>, None, CpuAVX, Modrm|Vex|Space0F3A|VexWIG=
|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Uns=
pecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
> +vrounds<sd>, 0x660a | <sd:opc>, None, CpuAVX, Modrm|VexLIG|Space0F3A|Vex=
VVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, <sd:e=
lem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
>  vrsqrtps, 0x52, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|No_b=
Suf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXM=
M|RegYMM, RegXMM|RegYMM }
>  vrsqrtss, 0xf352, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexVVVV|VexWIG|No_=
bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseInde=
x|RegXMM, RegXMM, RegXMM }
> -vshufpd, 0x66c6, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|Chec=
kRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecif=
ied|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vshufps, 0xc6, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|CheckR=
egSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecifie=
d|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vsqrtpd, 0x6651, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|No_=
bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegX=
MM|RegYMM, RegXMM|RegYMM }
> -vsqrtps, 0x51, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|No_bS=
uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM=
|RegYMM, RegXMM|RegYMM }
> -vsqrtsd, 0xf251, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexVVVV|VexWIG|No_b=
Suf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex=
|RegXMM, RegXMM, RegXMM }
> -vsqrtss, 0xf351, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexVVVV|VexWIG|No_b=
Suf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex=
|RegXMM, RegXMM, RegXMM }
> +vshufp<sd>, 0x<sd:ppfx>c6, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWI=
G|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Un=
specified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> +vsqrtp<sd>, 0x<sd:ppfx>51, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckR=
egSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|Base=
Index|RegXMM|RegYMM, RegXMM|RegYMM }
> +vsqrts<sd>, 0x<sd:spfx>51, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|Ve=
xWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <sd:elem>|Unspecif=
ied|BaseIndex|RegXMM, RegXMM, RegXMM }
>  vstmxcsr, 0xae, 3, CpuAVX, Modrm|Vex128|Space0F|VexWIG|IgnoreSize|No_bSu=
f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex }
> -vsubpd, 0x665c, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|Check=
RegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|Bas=
eIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vsubps, 0x5c, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|CheckRe=
gSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseI=
ndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vsubsd, 0xf25c, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexVVVV|VexWIG|No_bS=
uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|=
RegXMM, RegXMM, RegXMM }
> -vsubss, 0xf35c, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexVVVV|VexWIG|No_bS=
uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|=
RegXMM, RegXMM, RegXMM }
> -vtestpd, 0x660f, None, CpuAVX, Modrm|Vex|Space0F38|VexW=3D1|CheckRegSize=
|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|=
RegXMM|RegYMM, RegXMM|RegYMM }
> -vtestps, 0x660e, None, CpuAVX, Modrm|Vex|Space0F38|VexW=3D1|CheckRegSize=
|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|=
RegXMM|RegYMM, RegXMM|RegYMM }
> -vucomisd, 0x662e, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexWIG|No_bSuf|No_=
wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM=
, RegXMM }
> -vucomiss, 0x2e, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexWIG|No_bSuf|No_wS=
uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, =
RegXMM }
> -vunpckhpd, 0x6615, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|Ch=
eckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|=
BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vunpckhps, 0x15, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|Chec=
kRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|Ba=
seIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vunpcklpd, 0x6614, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|Ch=
eckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|=
BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vunpcklps, 0x14, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|Chec=
kRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|Ba=
seIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vxorpd, 0x6657, None, CpuAVX, Modrm|C|Vex|Space0F|VexVVVV=3D1|VexWIG|Che=
ckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Unsp=
ecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vxorps, 0x57, None, CpuAVX, Modrm|C|Vex|Space0F|VexVVVV=3D1|VexWIG|Check=
RegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Unspec=
ified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> +vsubp<sd>, 0x<sd:ppfx>5c, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG=
|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecifi=
ed|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> +vsubs<sd>, 0x<sd:spfx>5c, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|Vex=
WIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <sd:elem>|Unspecifi=
ed|BaseIndex|RegXMM, RegXMM, RegXMM }
> +vtestp<sd>, 0x660e | <sd:opc>, None, CpuAVX, Modrm|Vex|Space0F38|VexW0|C=
heckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified=
|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
> +vucomis<sd>, 0x<sd:ppfx>2e, None, CpuAVX, Modrm|VexLIG|Space0F|VexWIG|No=
_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <sd:elem>|Unspecified|Bas=
eIndex|RegXMM, RegXMM }
> +vunpckhp<sd>, 0x<sd:ppfx>15, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|Vex=
WIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspec=
ified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> +vunpcklp<sd>, 0x<sd:ppfx>14, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|Vex=
WIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspec=
ified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> +vxorp<sd>, 0x<sd:ppfx>57, None, CpuAVX, Modrm|C|Vex|Space0F|VexVVVV|VexW=
IG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, =
{ Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
>  vzeroall, 0x77, None, CpuAVX, Vex=3D2|Space0F|VexWIG|No_bSuf|No_wSuf|No_=
lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
>  vzeroupper, 0x77, None, CpuAVX, Vex|Space0F|VexWIG|No_bSuf|No_wSuf|No_lS=
uf|No_sSuf|No_qSuf|No_ldSuf, {}
>
> @@ -1830,9 +1775,8 @@ vpsrlvq, 0x6645, None, CpuAVX2, Modrm|Ve
>  vgatherdpd, 0x6692, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW1|Che=
ckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { Reg=
XMM|RegYMM, Qword|Unspecified|BaseIndex, RegXMM|RegYMM }
>  vgatherdps, 0x6692, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW0|No_=
bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { RegXMM, Dword|Un=
specified|BaseIndex, RegXMM }
>  vgatherdps, 0x6692, None, CpuAVX2, Modrm|Vex=3D2|Space0F38|VexVVVV|VexW0=
|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB256, { RegYMM, Dwor=
d|Unspecified|BaseIndex, RegYMM }
> -vgatherqpd, 0x6693, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW1|No_=
bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { RegXMM, Qword|Un=
specified|BaseIndex, RegXMM }
> +vgatherqp<sd>, 0x6693, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|<sd:ve=
xw>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { RegXMM, <=
sd:elem>|Unspecified|BaseIndex, RegXMM }
>  vgatherqpd, 0x6693, None, CpuAVX2, Modrm|Vex=3D2|Space0F38|VexVVVV|VexW1=
|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB256, { RegYMM, Qwor=
d|Unspecified|BaseIndex, RegYMM }
> -vgatherqps, 0x6693, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW0|No_=
bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { RegXMM, Dword|Un=
specified|BaseIndex, RegXMM }
>  vgatherqps, 0x6693, None, CpuAVX2, Modrm|Vex=3D2|Space0F38|VexVVVV|VexW0=
|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB256, { RegXMM, Dwor=
d|Unspecified|BaseIndex, RegXMM }
>  vpgatherdd, 0x6690, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW0|No_=
bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { RegXMM, Dword|Un=
specified|BaseIndex, RegXMM }
>  vpgatherdd, 0x6690, None, CpuAVX2, Modrm|Vex=3D2|Space0F38|VexVVVV|VexW0=
|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB256, { RegYMM, Dwor=
d|Unspecified|BaseIndex, RegYMM }
> @@ -1881,26 +1825,16 @@ vcvtps2ph, 0x661d, None, CpuF16C, Modrm|
>
>  <fma:opc, 132:10, 213:20, 231:30>
>
> -vfmadd<fma>pd, 0x6688 | 0x<fma:opc>, None, CpuFMA, Modrm|Vex|Space0F38|V=
exVVVV|VexW1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,=
 { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vfmadd<fma>ps, 0x6688 | 0x<fma:opc>, None, CpuFMA, Modrm|Vex|Space0F38|V=
exVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,=
 { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vfmadd<fma>sd, 0x6689 | 0x<fma:opc>, None, CpuFMA, Modrm|VexLIG|Space0F3=
8|VexVVVV|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|U=
nspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
> -vfmadd<fma>ss, 0x6689 | 0x<fma:opc>, None, CpuFMA, Modrm|VexLIG|Space0F3=
8|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|U=
nspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
> -vfmaddsub<fma>pd, 0x6686 | 0x<fma:opc>, None, CpuFMA, Modrm|Vex|Space0F3=
8|VexVVVV|VexW1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS=
uf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vfmaddsub<fma>ps, 0x6686 | 0x<fma:opc>, None, CpuFMA, Modrm|Vex|Space0F3=
8|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS=
uf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vfmsub<fma>pd, 0x668a | 0x<fma:opc>, None, CpuFMA, Modrm|Vex|Space0F38|V=
exVVVV|VexW1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,=
 { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vfmsub<fma>ps, 0x668a | 0x<fma:opc>, None, CpuFMA, Modrm|Vex|Space0F38|V=
exVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,=
 { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vfmsub<fma>sd, 0x668b | 0x<fma:opc>, None, CpuFMA, Modrm|VexLIG|Space0F3=
8|VexVVVV|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|U=
nspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
> -vfmsub<fma>ss, 0x668b | 0x<fma:opc>, None, CpuFMA, Modrm|VexLIG|Space0F3=
8|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|U=
nspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
> -vfmsubadd<fma>pd, 0x6687 | 0x<fma:opc>, None, CpuFMA, Modrm|Vex|Space0F3=
8|VexVVVV|VexW1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS=
uf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vfmsubadd<fma>ps, 0x6687 | 0x<fma:opc>, None, CpuFMA, Modrm|Vex|Space0F3=
8|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS=
uf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vfnmadd<fma>pd, 0x668c | 0x<fma:opc>, None, CpuFMA, Modrm|Vex|Space0F38|=
VexVVVV|VexW1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf=
, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vfnmadd<fma>ps, 0x668c | 0x<fma:opc>, None, CpuFMA, Modrm|Vex|Space0F38|=
VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf=
, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vfnmadd<fma>sd, 0x668d | 0x<fma:opc>, None, CpuFMA, Modrm|VexLIG|Space0F=
38|VexVVVV|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|=
Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
> -vfnmadd<fma>ss, 0x668d | 0x<fma:opc>, None, CpuFMA, Modrm|VexLIG|Space0F=
38|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|=
Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
> -vfnmsub<fma>pd, 0x668e | 0x<fma:opc>, None, CpuFMA, Modrm|Vex|Space0F38|=
VexVVVV|VexW1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf=
, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vfnmsub<fma>ps, 0x668e | 0x<fma:opc>, None, CpuFMA, Modrm|Vex|Space0F38|=
VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf=
, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vfnmsub<fma>sd, 0x668f | 0x<fma:opc>, None, CpuFMA, Modrm|VexLIG|Space0F=
38|VexVVVV|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|=
Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
> -vfnmsub<fma>ss, 0x668f | 0x<fma:opc>, None, CpuFMA, Modrm|VexLIG|Space0F=
38|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|=
Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
> +vfmadd<fma>p<sd>, 0x6688 | 0x<fma:opc>, None, CpuFMA, Modrm|Vex|Space0F3=
8|VexVVVV|<sd:vexw>|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No=
_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM=
 }
> +vfmadd<fma>s<sd>, 0x6689 | 0x<fma:opc>, None, CpuFMA, Modrm|VexLIG|Space=
0F38|VexVVVV|<sd:vexw>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { =
<sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
> +vfmaddsub<fma>p<sd>, 0x6686 | 0x<fma:opc>, None, CpuFMA, Modrm|Vex|Space=
0F38|VexVVVV|<sd:vexw>|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf=
|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|Reg=
YMM }
> +vfmsub<fma>p<sd>, 0x668a | 0x<fma:opc>, None, CpuFMA, Modrm|Vex|Space0F3=
8|VexVVVV|<sd:vexw>|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No=
_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM=
 }
> +vfmsub<fma>s<sd>, 0x668b | 0x<fma:opc>, None, CpuFMA, Modrm|VexLIG|Space=
0F38|VexVVVV|<sd:vexw>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { =
<sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
> +vfmsubadd<fma>p<sd>, 0x6687 | 0x<fma:opc>, None, CpuFMA, Modrm|Vex|Space=
0F38|VexVVVV|<sd:vexw>|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf=
|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|Reg=
YMM }
> +vfnmadd<fma>p<sd>, 0x668c | 0x<fma:opc>, None, CpuFMA, Modrm|Vex|Space0F=
38|VexVVVV|<sd:vexw>|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N=
o_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYM=
M }
> +vfnmadd<fma>s<sd>, 0x668d | 0x<fma:opc>, None, CpuFMA, Modrm|VexLIG|Spac=
e0F38|VexVVVV|<sd:vexw>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {=
 <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
> +vfnmsub<fma>p<sd>, 0x668e | 0x<fma:opc>, None, CpuFMA, Modrm|Vex|Space0F=
38|VexVVVV|<sd:vexw>|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N=
o_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYM=
M }
> +vfnmsub<fma>s<sd>, 0x668f | 0x<fma:opc>, None, CpuFMA, Modrm|VexLIG|Spac=
e0F38|VexVVVV|<sd:vexw>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {=
 <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
>
>  // HLE prefixes
>
> @@ -1925,26 +1859,16 @@ shrx, 0xf2f7, None, CpuBMI2, Modrm|Check
>
>  // FMA4 instructions
>
> -vfmaddpd, 0x6669, None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|Vex=
Sources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, =
{Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|=
RegYMM }
> -vfmaddps, 0x6668, None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|Vex=
Sources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, =
{Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|=
RegYMM }
> -vfmaddsd, 0x666b, None, CpuFMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|=
VexSources=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Un=
specified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
> -vfmaddss, 0x666a, None, CpuFMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|=
VexSources=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Un=
specified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
> -vfmaddsubpd, 0x665d, None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|=
VexSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSu=
f, {Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegX=
MM|RegYMM }
> -vfmaddsubps, 0x665c, None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|=
VexSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSu=
f, {Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegX=
MM|RegYMM }
> -vfmsubaddpd, 0x665f, None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|=
VexSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSu=
f, {Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegX=
MM|RegYMM }
> -vfmsubaddps, 0x665e, None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|=
VexSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSu=
f, {Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegX=
MM|RegYMM }
> -vfmsubpd, 0x666d, None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|Vex=
Sources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, =
{Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|=
RegYMM }
> -vfmsubps, 0x666c, None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|Vex=
Sources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, =
{Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|=
RegYMM }
> -vfmsubsd, 0x666f, None, CpuFMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|=
VexSources=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Un=
specified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
> -vfmsubss, 0x666e, None, CpuFMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|=
VexSources=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Un=
specified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
> -vfnmaddpd, 0x6679, None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|Ve=
xSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,=
 {Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM=
|RegYMM }
> -vfnmaddps, 0x6678, None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|Ve=
xSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,=
 {Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM=
|RegYMM }
> -vfnmaddsd, 0x667b, None, CpuFMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1=
|VexSources=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|U=
nspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
> -vfnmaddss, 0x667a, None, CpuFMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1=
|VexSources=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|U=
nspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
> -vfnmsubpd, 0x667d, None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|Ve=
xSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,=
 {Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM=
|RegYMM }
> -vfnmsubps, 0x667c, None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|Ve=
xSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,=
 {Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM=
|RegYMM }
> -vfnmsubsd, 0x667f, None, CpuFMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1=
|VexSources=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|U=
nspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
> -vfnmsubss, 0x667e, None, CpuFMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1=
|VexSources=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|U=
nspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
> +vfmaddp<sd>, 0x6668 | <sd:opc>, None, CpuFMA4, D|Modrm|Vex|Space0F3A|Vex=
VVVV|VexW1|VexSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_q=
Suf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|=
RegYMM, RegXMM|RegYMM }
> +vfmadds<sd>, 0x666a | <sd:opc>, None, CpuFMA4, D|Modrm|VexLIG|Space0F3A|=
VexVVVV|VexW1|VexSources=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS=
uf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
> +vfmaddsubp<sd>, 0x665c | <sd:opc>, None, CpuFMA4, D|Modrm|Vex|Space0F3A|=
VexVVVV|VexW1|VexSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N=
o_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegX=
MM|RegYMM, RegXMM|RegYMM }
> +vfmsubaddp<sd>, 0x665e | <sd:opc>, None, CpuFMA4, D|Modrm|Vex|Space0F3A|=
VexVVVV|VexW1|VexSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N=
o_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegX=
MM|RegYMM, RegXMM|RegYMM }
> +vfmsubp<sd>, 0x666c | <sd:opc>, None, CpuFMA4, D|Modrm|Vex|Space0F3A|Vex=
VVVV|VexW1|VexSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_q=
Suf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|=
RegYMM, RegXMM|RegYMM }
> +vfmsubs<sd>, 0x666e | <sd:opc>, None, CpuFMA4, D|Modrm|VexLIG|Space0F3A|=
VexVVVV|VexW1|VexSources=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS=
uf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
> +vfnmaddp<sd>, 0x6678 | <sd:opc>, None, CpuFMA4, D|Modrm|Vex|Space0F3A|Ve=
xVVVV|VexW1|VexSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_=
qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM=
|RegYMM, RegXMM|RegYMM }
> +vfnmadds<sd>, 0x667a | <sd:opc>, None, CpuFMA4, D|Modrm|VexLIG|Space0F3A=
|VexVVVV|VexW1|VexSources=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ld=
Suf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
> +vfnmsubp<sd>, 0x667c | <sd:opc>, None, CpuFMA4, D|Modrm|Vex|Space0F3A|Ve=
xVVVV|VexW1|VexSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_=
qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM=
|RegYMM, RegXMM|RegYMM }
> +vfnmsubs<sd>, 0x667e | <sd:opc>, None, CpuFMA4, D|Modrm|VexLIG|Space0F3A=
|VexVVVV|VexW1|VexSources=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ld=
Suf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
>
>  // XOP instructions
>
> @@ -1952,17 +1876,13 @@ vfnmsubss, 0x667e, None, CpuFMA4, D|Modr
>  <xop_irel:imm, lt:0, le:1, gt:2, ge:3, eq:4, neq:5, false:6, true:7>
>  <xop_sign:opc, :00, u:20>
>
> -vfrczpd, 0x81, None, CpuXOP, Modrm|SpaceXOP09|VexW=3D1|CheckRegSize|No_b=
Suf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Unspecified|BaseIndex|R=
egXMM|RegYMM, RegXMM|RegYMM }
> -vfrczps, 0x80, None, CpuXOP, Modrm|SpaceXOP09|VexW=3D1|CheckRegSize|No_b=
Suf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Unspecified|BaseIndex|R=
egXMM|RegYMM, RegXMM|RegYMM }
> -vfrczsd, 0x83, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|No_wSuf|No_l=
Suf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Qword|RegXMM|Unspecified|BaseIndex, Reg=
XMM }
> -vfrczss, 0x82, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|No_wSuf|No_l=
Suf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Dword|RegXMM|Unspecified|BaseIndex, Reg=
XMM }
> +vfrczp<sd>, 0x80 | <sd:opc>, None, CpuXOP, Modrm|SpaceXOP09|VexW0|CheckR=
egSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Unspecified|=
BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
> +vfrczs<sd>, 0x82 | <sd:opc>, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSu=
f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { <sd:elem>|RegXMM|Unspecif=
ied|BaseIndex, RegXMM }
>  vpcmov, 0xa2, None, CpuXOP, D|Modrm|SpaceXOP08|VexSources=3D2|VexVVVV|Ve=
xW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Re=
gXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|Reg=
YMM }
>  vpcom<xop_sign><xop_elem>, 0xcc | 0x<xop_sign:opc> | <xop_elem:opc>, Non=
e, CpuXOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No=
_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM, RegXM=
M }
>  vpcom<xop_irel><xop_sign><xop_elem>, 0xcc | 0x<xop_sign:opc> | <xop_elem=
:opc>, <xop_irel:imm>, CpuXOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|No_bSu=
f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Unspecified|Bas=
eIndex, RegXMM, RegXMM }
> -vpermil2pd, 0x6649, None, CpuXOP, Modrm|Space0F3A|VexVVVV=3D1|VexW=3D1|V=
ex|VexSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_l=
dSuf, { Imm8, RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|Re=
gYMM, RegXMM|RegYMM }
> -vpermil2pd, 0x6649, None, CpuXOP, Modrm|Space0F3A|VexVVVV=3D1|VexW=3D2|V=
ex|VexSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_l=
dSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|Re=
gYMM, RegXMM|RegYMM }
> -vpermil2ps, 0x6648, None, CpuXOP, Modrm|Space0F3A|VexVVVV=3D1|VexW=3D1|V=
ex|VexSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_l=
dSuf, { Imm8, RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|Re=
gYMM, RegXMM|RegYMM }
> -vpermil2ps, 0x6648, None, CpuXOP, Modrm|Space0F3A|VexVVVV=3D1|VexW=3D2|V=
ex|VexSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_l=
dSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|Re=
gYMM, RegXMM|RegYMM }
> +vpermil2p<sd>, 0x6648 | <sd:opc>, None, CpuXOP, Modrm|Space0F3A|VexVVVV|=
VexW0|Vex|VexSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS=
uf|No_ldSuf, { Imm8, RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, Re=
gXMM|RegYMM, RegXMM|RegYMM }
> +vpermil2p<sd>, 0x6648 | <sd:opc>, None, CpuXOP, Modrm|Space0F3A|VexVVVV|=
VexW1|Vex|VexSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS=
uf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, Re=
gXMM|RegYMM, RegXMM|RegYMM }
>  vphaddbd, 0xc2, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|No_wSuf|No_=
lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM }
>  vphaddbq, 0xc3, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|No_wSuf|No_=
lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM }
>  vphaddbw, 0xc1, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|No_wSuf|No_=
lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM }
> @@ -2160,6 +2080,11 @@ vpclmulhqhqdq, 0x6644, 0x11, CpuVPCLMULQ
>  #define Disp8ShiftVL Disp8MemShift=3DDISP8_SHIFT_VL
>  #define MaskingMorZ  Masking=3DDYNAMIC_MASKING
>
> +<sdh:cpu:cpudq:ppfx:spfx:pfx:spc1:spc2:opc:vexw:elem, +
> +    s:CpuAVX512F:CpuAVX512DQ::f3:66:Space0F:Space0F38:0:VexW0:Dword, +
> +    d:CpuAVX512F:CpuAVX512DQ:66:f2:66:Space0F:Space0F38:1:VexW1:Qword, +
> +    h:CpuAVX512_FP16:CpuAVX512_FP16::f3::EVexMap5:EVexMap6:0:VexW0:Word>
> +
>  kandnw, 0x42, None, CpuAVX512F, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|VexW=
=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, =
RegMask }
>  kandw, 0x41, None, CpuAVX512F, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|VexW=3D=
1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, Reg=
Mask }
>  korw, 0x45, None, CpuAVX512F, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|VexW=3D1=
|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegM=
ask }
> @@ -2178,27 +2103,17 @@ kshiftrw, 0x6630, None, CpuAVX512F, Modr
>
>  kunpckbw, 0x664B, None, CpuAVX512F, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|Ve=
xW=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask=
, RegMask }
>
> -vaddpd, 0x6658, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV|VexW=
1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS=
uf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|Ba=
seIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> -vdivpd, 0x665E, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV|VexW=
1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS=
uf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|Ba=
seIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> -vmulpd, 0x6659, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV|VexW=
1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS=
uf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|Ba=
seIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> -vsubpd, 0x665C, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV|VexW=
1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS=
uf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|Ba=
seIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> -
> -vaddps, 0x58, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV|VexW0|=
Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf=
|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|Base=
Index, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> -vdivps, 0x5E, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV|VexW0|=
Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf=
|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|Base=
Index, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> -vmulps, 0x59, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV|VexW0|=
Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf=
|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|Base=
Index, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> -vsubps, 0x5C, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV|VexW0|=
Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf=
|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|Base=
Index, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> -
> -vaddsd, 0xF258, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0F|VexV=
VVV|VexW1|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSu=
f|StaticRounding|SAE, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM =
}
> -vdivsd, 0xF25E, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0F|VexV=
VVV|VexW1|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSu=
f|StaticRounding|SAE, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM =
}
> -vmulsd, 0xF259, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0F|VexV=
VVV|VexW1|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSu=
f|StaticRounding|SAE, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM =
}
> -vsqrtsd, 0xF251, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0F|Vex=
VVVV|VexW1|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS=
uf|StaticRounding|SAE, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM=
 }
> -vsubsd, 0xF25C, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0F|VexV=
VVV|VexW1|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSu=
f|StaticRounding|SAE, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM =
}
> +vaddp<sdh>, 0x<sdh:ppfx>58, None, <sdh:cpu>, Modrm|Masking=3D3|<sdh:spc1=
>|VexVVVV|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No=
_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|<=
sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM=
 }
> +vdivp<sdh>, 0x<sdh:ppfx>5e, None, <sdh:cpu>, Modrm|Masking=3D3|<sdh:spc1=
>|VexVVVV|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No=
_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|<=
sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM=
 }
> +vmulp<sdh>, 0x<sdh:ppfx>59, None, <sdh:cpu>, Modrm|Masking=3D3|<sdh:spc1=
>|VexVVVV|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No=
_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|<=
sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM=
 }
> +vsqrtp<sdh>, 0x<sdh:ppfx>51, None, <sdh:cpu>, Modrm|Masking=3D3|<sdh:spc=
1>|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N=
o_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|<sdh:ele=
m>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
> +vsubp<sdh>, 0x<sdh:ppfx>5c, None, <sdh:cpu>, Modrm|Masking=3D3|<sdh:spc1=
>|VexVVVV|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No=
_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|<=
sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM=
 }
>
> -vaddss, 0xF358, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0F|VexV=
VVV|VexW0|Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSu=
f|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM =
}
> -vdivss, 0xF35E, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0F|VexV=
VVV|VexW0|Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSu=
f|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM =
}
> -vmulss, 0xF359, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0F|VexV=
VVV|VexW0|Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSu=
f|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM =
}
> -vsqrtss, 0xF351, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0F|Vex=
VVVV|VexW0|Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS=
uf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM=
 }
> -vsubss, 0xF35C, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0F|VexV=
VVV|VexW0|Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSu=
f|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM =
}
> +vadds<sdh>, 0x<sdh:spfx>58, None, <sdh:cpu>, Modrm|EVexLIG|Masking=3D3|<=
sdh:spc1>|VexVVVV|<sdh:vexw>|Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|=
No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIn=
dex, RegXMM, RegXMM }
> +vdivs<sdh>, 0x<sdh:spfx>5e, None, <sdh:cpu>, Modrm|EVexLIG|Masking=3D3|<=
sdh:spc1>|VexVVVV|<sdh:vexw>|Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|=
No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIn=
dex, RegXMM, RegXMM }
> +vmuls<sdh>, 0x<sdh:spfx>59, None, <sdh:cpu>, Modrm|EVexLIG|Masking=3D3|<=
sdh:spc1>|VexVVVV|<sdh:vexw>|Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|=
No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIn=
dex, RegXMM, RegXMM }
> +vsqrts<sdh>, 0x<sdh:spfx>51, None, <sdh:cpu>, Modrm|EVexLIG|Masking=3D3|=
<sdh:spc1>|VexVVVV|<sdh:vexw>|Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf=
|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseI=
ndex, RegXMM, RegXMM }
> +vsubs<sdh>, 0x<sdh:spfx>5C, None, <sdh:cpu>, Modrm|EVexLIG|Masking=3D3|<=
sdh:spc1>|VexVVVV|<sdh:vexw>|Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|=
No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIn=
dex, RegXMM, RegXMM }
>
>  valignd, 0x6603, None, CpuAVX512F, Modrm|Masking=3D3|Space0F3A|VexVVVV=
=3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N=
o_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|Bas=
eIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
>  vpternlogd, 0x6625, None, CpuAVX512F, Modrm|Masking=3D3|Space0F3A|VexVVV=
V=3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|=
No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|Ba=
seIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> @@ -2206,11 +2121,11 @@ vpternlogd, 0x6625, None, CpuAVX512F, Mo
>  valignq, 0x6603, None, CpuAVX512F, Modrm|Masking=3D3|Space0F3A|VexVVVV=
=3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N=
o_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|Bas=
eIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
>  vpternlogq, 0x6625, None, CpuAVX512F, Modrm|Masking=3D3|Space0F3A|VexVVV=
V=3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|=
No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|Ba=
seIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
>
> -vblendmpd, 0x6665, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=
=3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N=
o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex=
, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> +vblendmp<sd>, 0x6665, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexV=
VVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N=
o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseI=
ndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
>  vpblendmq, 0x6664, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=
=3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N=
o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex=
, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> -vpermi2pd, 0x6677, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=
=3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N=
o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex=
, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> +vpermi2p<sd>, 0x6677, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexV=
VVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N=
o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseI=
ndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
>  vpermi2q, 0x6676, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=
=3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N=
o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex=
, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> -vpermt2pd, 0x667F, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=
=3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N=
o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex=
, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> +vpermt2p<sd>, 0x667F, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexV=
VVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N=
o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseI=
ndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
>  vpermt2q, 0x667E, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=
=3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N=
o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex=
, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
>  vpmaxsq, 0x663D, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=
=3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N=
o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex=
, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
>  vpmaxuq, 0x663F, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=
=3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N=
o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex=
, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> @@ -2223,12 +2138,9 @@ vpsllvq, 0x6647, None, CpuAVX512F, Modrm
>  vpsravq, 0x6646, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=
=3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N=
o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex=
, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
>  vpsrlvq, 0x6645, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=
=3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N=
o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex=
, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
>
> -vblendmps, 0x6665, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=
=3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N=
o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex=
, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
>  vpblendmd, 0x6664, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=
=3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N=
o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex=
, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
>  vpermi2d, 0x6676, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=
=3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N=
o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex=
, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> -vpermi2ps, 0x6677, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=
=3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N=
o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex=
, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
>  vpermt2d, 0x667E, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=
=3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N=
o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex=
, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> -vpermt2ps, 0x667F, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=
=3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N=
o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex=
, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
>  vpmaxsd, 0x663D, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=
=3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N=
o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex=
, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
>  vpmaxud, 0x663F, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=
=3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N=
o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex=
, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
>  vpminsd, 0x6639, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=
=3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N=
o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex=
, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> @@ -2252,23 +2164,14 @@ vbroadcastsd, 0x6619, None, CpuAVX512F,
>  vpbroadcastd, 0x6658, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexW=
0|Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg=
XMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
>  vpbroadcastd, 0x667C, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|No_b=
Suf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, RegXMM|RegYMM|RegZMM=
 }
>
> -vcmp<avx_frel>pd, 0x66C2, 0x<avx_frel:imm>, CpuAVX512F, Modrm|Masking=3D=
2|Space0F|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf=
|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE|ImmExt, { RegXMM|RegYMM|RegZMM|Qword|=
Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
> -vcmppd, 0x66C2, None, CpuAVX512F, Modrm|Masking=3D2|Space0F|VexVVVV=3D1|=
VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N=
o_qSuf|No_ldSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseInd=
ex, RegXMM|RegYMM|RegZMM, RegMask }
> -
> -vcmp<avx_frel>ps, 0xC2, 0x<avx_frel:imm>, CpuAVX512F, Modrm|Masking=3D2|=
Space0F|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|N=
o_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, { RegXMM|RegYMM|RegZMM|Dword|Un=
specified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
> -vcmpps, 0xC2, None, CpuAVX512F, Modrm|Masking=3D2|Space0F|VexVVVV=3D1|Ve=
xW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_=
qSuf|No_ldSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex=
, RegXMM|RegYMM|RegZMM, RegMask }
> -
> -vcmp<avx_frel>sd, 0xF2C2, 0x<avx_frel:imm>, CpuAVX512F, Modrm|EVexLIG|Ma=
sking=3D2|Space0F|VexVVVV|VexW1|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|N=
o_sSuf|No_qSuf|No_ldSuf|SAE|ImmExt, { RegXMM|Qword|Unspecified|BaseIndex, R=
egXMM, RegMask }
> -vcmpsd, 0xF2C2, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D2|Space0F|VexV=
VVV|VexW1|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSu=
f|SAE, { Imm8, RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegMask }
> -
> -vcmp<avx_frel>ss, 0xF3C2, 0x<avx_frel:imm>, CpuAVX512F, Modrm|EVexLIG|Ma=
sking=3D2|Space0F|VexVVVV|VexW0|Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|N=
o_sSuf|No_qSuf|No_ldSuf|SAE|ImmExt, { RegXMM|Dword|Unspecified|BaseIndex, R=
egXMM, RegMask }
> -vcmpss, 0xF3C2, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D2|Space0F|VexV=
VVV|VexW0|Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSu=
f|SAE, { Imm8, RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegMask }
> +vcmp<avx_frel>p<sd>, 0x<sd:ppfx>C2, 0x<avx_frel:imm>, CpuAVX512F, Modrm|=
Masking=3D2|Space0F|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|N=
o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, { RegXMM|RegYMM=
|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
> +vcmpp<sd>, 0x<sd:ppfx>C2, None, CpuAVX512F, Modrm|Masking=3D2|Space0F|Ve=
xVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf=
|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|<sd:elem>|Unspe=
cified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
>
> -vcomisd, 0x662F, None, CpuAVX512F, Modrm|EVexLIG|Space0F|VexW1|Disp8MemS=
hift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegXMM|Qwo=
rd|Unspecified|BaseIndex, RegXMM }
> -vucomisd, 0x662E, None, CpuAVX512F, Modrm|EVexLIG|Space0F|VexW1|Disp8Mem=
Shift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegXMM|Qw=
ord|Unspecified|BaseIndex, RegXMM }
> +vcmp<avx_frel>s<sd>, 0x<sd:spfx>C2, 0x<avx_frel:imm>, CpuAVX512F, Modrm|=
EVexLIG|Masking=3D2|Space0F|VexVVVV|<sd:vexw>|Disp8MemShift|No_bSuf|No_wSuf=
|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE|ImmExt, { RegXMM|<sd:elem>|Unspecifie=
d|BaseIndex, RegXMM, RegMask }
> +vcmps<sd>, 0x<sd:spfx>C2, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D2|Sp=
ace0F|VexVVVV|<sd:vexw>|Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS=
uf|No_ldSuf|SAE, { Imm8, RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, Re=
gMask }
>
> -vcomiss, 0x2F, None, CpuAVX512F, Modrm|EVexLIG|Space0F|VexW0|Disp8MemShi=
ft=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegXMM|Dword=
|Unspecified|BaseIndex, RegXMM }
> -vucomiss, 0x2E, None, CpuAVX512F, Modrm|EVexLIG|Space0F|VexW0|Disp8MemSh=
ift=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegXMM|Dwor=
d|Unspecified|BaseIndex, RegXMM }
> +vcomis<sdh>, 0x<sdh:ppfx>2f, None, <sdh:cpu>, Modrm|EVexLIG|<sdh:spc1>|<=
sdh:vexw>|Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SA=
E, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM }
> +vucomis<sdh>, 0x<sdh:ppfx>2e, None, <sdh:cpu>, Modrm|EVexLIG|<sdh:spc1>|=
<sdh:vexw>|Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|S=
AE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM }
>
>  vcompresspd, 0x668A, None, CpuAVX512F, Modrm|MaskingMorZ|Space0F38|VexW=
=3D2|Disp8MemShift=3D3|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf=
|No_ldSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseInd=
ex }
>  vcompressps, 0x668A, None, CpuAVX512F, Modrm|MaskingMorZ|Space0F38|VexW=
=3D1|Disp8MemShift=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf=
|No_ldSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseInd=
ex }
> @@ -2288,7 +2191,6 @@ vcvtudq2pd, 0xF37A, None, CpuAVX512F, Mo
>
>  vcvtdq2ps, 0x5B, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexW0|Broad=
cast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_l=
dSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex=
, RegXMM|RegYMM|RegZMM }
>  vcvtps2udq, 0x79, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexW0|Broa=
dcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_=
ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseInde=
x, RegXMM|RegYMM|RegZMM }
> -vsqrtps, 0x51, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexW0|Broadca=
st|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS=
uf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, =
RegXMM|RegYMM|RegZMM }
>
>  vcvtpd2dq, 0xF2E6, None, CpuAVX512F, Modrm|EVex512|Masking=3D3|Space0F|V=
exW1|Broadcast|Disp8MemShift=3D6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No=
_ldSuf|StaticRounding|SAE, { RegZMM|Qword|Unspecified|BaseIndex, RegYMM }
>
> @@ -2357,42 +2259,28 @@ vextracti64x4, 0x663B, None, CpuAVX512F,
>  vextractps, 0x6617, None, CpuAVX512F, Modrm|EVex128|Space0F3A|VexWIG|Dis=
p8MemShift=3D2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,=
 { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex }
>  vextractps, 0x6617, None, CpuAVX512F|Cpu64, RegMem|EVex128|Space0F3A|Vex=
WIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg64=
 }
>
> -vfixupimmpd, 0x6654, None, CpuAVX512F, Modrm|Masking=3D3|Space0F3A|VexVV=
VV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSu=
f|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|Base=
Index, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> -vfixupimmps, 0x6654, None, CpuAVX512F, Modrm|Masking=3D3|Space0F3A|VexVV=
VV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSu=
f|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|Base=
Index, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> +vfixupimmp<sd>, 0x6654, None, CpuAVX512F, Modrm|Masking=3D3|Space0F3A|Ve=
xVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf=
|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|<sd:elem>|Unspe=
cified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> +vfixupimms<sd>, 0x6655, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Spac=
e0F3A|VexVVVV|<sd:vexw>|Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS=
uf|No_ldSuf|SAE, { Imm8, RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, Re=
gXMM }
>
> -vfixupimmsd, 0x6655, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0F=
3A|VexVVVV|VexW1|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|=
No_ldSuf|SAE, { Imm8, RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
> -vgetmantsd, 0x6627, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0F3=
A|VexVVVV|VexW1|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N=
o_ldSuf|SAE, { Imm8, RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
> -vrndscalesd, 0x660B, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0F=
3A|VexVVVV|VexW1|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|=
No_ldSuf|SAE, { Imm8, RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
> +vgetmantp<sdh>, 0x<sdh:pfx>26, None, <sdh:cpu>, Modrm|Masking=3D3|Space0=
F3A|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|=
No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspe=
cified|BaseIndex, RegXMM|RegYMM|RegZMM }
> +vgetmants<sdh>, 0x<sdh:pfx>27, None, <sdh:cpu>, Modrm|EVexLIG|Masking=3D=
3|Space0F3A|VexVVVV|<sdh:vexw>|Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSu=
f|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM|<sdh:elem>|Unspecified|BaseIndex, Re=
gXMM, RegXMM }
>
> -vfixupimmss, 0x6655, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0F=
3A|VexVVVV|VexW0|Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|=
No_ldSuf|SAE, { Imm8, RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
> -vgetmantss, 0x6627, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0F3=
A|VexVVVV|VexW0|Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N=
o_ldSuf|SAE, { Imm8, RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
> -vrndscaless, 0x660A, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0F=
3A|VexVVVV|VexW0|Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|=
No_ldSuf|SAE, { Imm8, RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
> +vrndscalep<sdh>, 0x<sdh:pfx>08 | <sdh:opc>, None, <sdh:cpu>, Modrm|Maski=
ng=3D3|Space0F3A|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_=
wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|<sd=
h:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
> +vrndscales<sdh>, 0x<sdh:pfx>0a | <sdh:opc>, None, <sdh:cpu>, Modrm|EVexL=
IG|Masking=3D3|Space0F3A|VexVVVV|<sdh:vexw>|Disp8MemShift|No_bSuf|No_wSuf|N=
o_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM|<sdh:elem>|Unspecified|=
BaseIndex, RegXMM, RegXMM }
>
> -vfmadd<fma>pd, 0x6688 | 0x<fma:opc>, None, CpuAVX512F, Modrm|Masking=3D3=
|Space0F38|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSu=
f|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZ=
MM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM =
}
> -vfmadd<fma>ps, 0x6688 | 0x<fma:opc>, None, CpuAVX512F, Modrm|Masking=3D3=
|Space0F38|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSu=
f|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZ=
MM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM =
}
> -vfmadd<fma>sd, 0x6689 | 0x<fma:opc>, None, CpuAVX512F, Modrm|EVexLIG|Mas=
king=3D3|Space0F38|VexVVVV|VexW1|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|=
No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|Qword|Unspecified|Bas=
eIndex, RegXMM, RegXMM }
> -vfmadd<fma>ss, 0x6689 | 0x<fma:opc>, None, CpuAVX512F, Modrm|EVexLIG|Mas=
king=3D3|Space0F38|VexVVVV|VexW0|Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|=
No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|Bas=
eIndex, RegXMM, RegXMM }
> -vfmaddsub<fma>pd, 0x6686 | 0x<fma:opc>, None, CpuAVX512F, Modrm|Masking=
=3D3|Space0F38|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No=
_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|=
RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|Reg=
ZMM }
> -vfmaddsub<fma>ps, 0x6686 | 0x<fma:opc>, None, CpuAVX512F, Modrm|Masking=
=3D3|Space0F38|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No=
_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|=
RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|Reg=
ZMM }
> -vfmsub<fma>pd, 0x668A | 0x<fma:opc>, None, CpuAVX512F, Modrm|Masking=3D3=
|Space0F38|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSu=
f|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZ=
MM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM =
}
> -vfmsub<fma>ps, 0x668A | 0x<fma:opc>, None, CpuAVX512F, Modrm|Masking=3D3=
|Space0F38|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSu=
f|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZ=
MM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM =
}
> -vfmsub<fma>sd, 0x668B | 0x<fma:opc>, None, CpuAVX512F, Modrm|EVexLIG|Mas=
king=3D3|Space0F38|VexVVVV|VexW1|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|=
No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|Qword|Unspecified|Bas=
eIndex, RegXMM, RegXMM }
> -vfmsub<fma>ss, 0x668B | 0x<fma:opc>, None, CpuAVX512F, Modrm|EVexLIG|Mas=
king=3D3|Space0F38|VexVVVV|VexW0|Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|=
No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|Bas=
eIndex, RegXMM, RegXMM }
> -vfmsubadd<fma>pd, 0x6687 | 0x<fma:opc>, None, CpuAVX512F, Modrm|Masking=
=3D3|Space0F38|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No=
_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|=
RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|Reg=
ZMM }
> -vfmsubadd<fma>ps, 0x6687 | 0x<fma:opc>, None, CpuAVX512F, Modrm|Masking=
=3D3|Space0F38|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No=
_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|=
RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|Reg=
ZMM }
> -vfnmadd<fma>pd, 0x668C | 0x<fma:opc>, None, CpuAVX512F, Modrm|Masking=3D=
3|Space0F38|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wS=
uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|Reg=
ZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM=
 }
> -vfnmadd<fma>ps, 0x668C | 0x<fma:opc>, None, CpuAVX512F, Modrm|Masking=3D=
3|Space0F38|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wS=
uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|Reg=
ZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM=
 }
> -vfnmadd<fma>sd, 0x668D | 0x<fma:opc>, None, CpuAVX512F, Modrm|EVexLIG|Ma=
sking=3D3|Space0F38|VexVVVV|VexW1|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf=
|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|Qword|Unspecified|Ba=
seIndex, RegXMM, RegXMM }
> -vfnmadd<fma>ss, 0x668D | 0x<fma:opc>, None, CpuAVX512F, Modrm|EVexLIG|Ma=
sking=3D3|Space0F38|VexVVVV|VexW0|Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf=
|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|Ba=
seIndex, RegXMM, RegXMM }
> -vfnmsub<fma>pd, 0x668E | 0x<fma:opc>, None, CpuAVX512F, Modrm|Masking=3D=
3|Space0F38|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wS=
uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|Reg=
ZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM=
 }
> -vfnmsub<fma>ps, 0x668E | 0x<fma:opc>, None, CpuAVX512F, Modrm|Masking=3D=
3|Space0F38|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wS=
uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|Reg=
ZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM=
 }
> -vfnmsub<fma>sd, 0x668F | 0x<fma:opc>, None, CpuAVX512F, Modrm|EVexLIG|Ma=
sking=3D3|Space0F38|VexVVVV|VexW1|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf=
|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|Qword|Unspecified|Ba=
seIndex, RegXMM, RegXMM }
> -vfnmsub<fma>ss, 0x668F | 0x<fma:opc>, None, CpuAVX512F, Modrm|EVexLIG|Ma=
sking=3D3|Space0F38|VexVVVV|VexW0|Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf=
|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|Ba=
seIndex, RegXMM, RegXMM }
> +vfmadd<fma>p<sdh>, 0x6688 | 0x<fma:opc>, None, <sdh:cpu>, Modrm|Masking=
=3D3|<sdh:spc2>|VexVVVV|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_b=
Suf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|R=
egYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM=
|RegYMM|RegZMM }
> +vfmadd<fma>s<sdh>, 0x6689 | 0x<fma:opc>, None, <sdh:cpu>, Modrm|EVexLIG|=
Masking=3D3|<sdh:spc2>|VexVVVV|<sdh:vexw>|Disp8MemShift|No_bSuf|No_wSuf|No_=
lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|<sdh:elem>|Unspe=
cified|BaseIndex, RegXMM, RegXMM }
> +vfmaddsub<fma>p<sdh>, 0x6686 | 0x<fma:opc>, None, <sdh:cpu>, Modrm|Maski=
ng=3D3|<sdh:spc2>|VexVVVV|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No=
_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM=
|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegX=
MM|RegYMM|RegZMM }
> +vfmsub<fma>p<sdh>, 0x668a | 0x<fma:opc>, None, <sdh:cpu>, Modrm|Masking=
=3D3|<sdh:spc2>|VexVVVV|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_b=
Suf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|R=
egYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM=
|RegYMM|RegZMM }
> +vfmsub<fma>s<sdh>, 0x668b | 0x<fma:opc>, None, <sdh:cpu>, Modrm|EVexLIG|=
Masking=3D3|<sdh:spc2>|VexVVVV|<sdh:vexw>|Disp8MemShift|No_bSuf|No_wSuf|No_=
lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|<sdh:elem>|Unspe=
cified|BaseIndex, RegXMM, RegXMM }
> +vfmsubadd<fma>p<sdh>, 0x6687 | 0x<fma:opc>, None, <sdh:cpu>, Modrm|Maski=
ng=3D3|<sdh:spc2>|VexVVVV|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No=
_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM=
|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegX=
MM|RegYMM|RegZMM }
> +vfnmadd<fma>p<sdh>, 0x668c | 0x<fma:opc>, None, <sdh:cpu>, Modrm|Masking=
=3D3|<sdh:spc2>|VexVVVV|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_b=
Suf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|R=
egYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM=
|RegYMM|RegZMM }
> +vfnmadd<fma>s<sdh>, 0x668d | 0x<fma:opc>, None, <sdh:cpu>, Modrm|EVexLIG=
|Masking=3D3|<sdh:spc2>|VexVVVV|<sdh:vexw>|Disp8MemShift|No_bSuf|No_wSuf|No=
_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|<sdh:elem>|Unsp=
ecified|BaseIndex, RegXMM, RegXMM }
> +vfnmsub<fma>p<sdh>, 0x668e | 0x<fma:opc>, None, <sdh:cpu>, Modrm|Masking=
=3D3|<sdh:spc2>|VexVVVV|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_b=
Suf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|R=
egYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM=
|RegYMM|RegZMM }
> +vfnmsub<fma>s<sdh>, 0x668f | 0x<fma:opc>, None, <sdh:cpu>, Modrm|EVexLIG=
|Masking=3D3|<sdh:spc2>|VexVVVV|<sdh:vexw>|Disp8MemShift|No_bSuf|No_wSuf|No=
_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|<sdh:elem>|Unsp=
ecified|BaseIndex, RegXMM, RegXMM }
>
> -vscalefpd, 0x662C, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=
|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|=
No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecifi=
ed|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> -vscalefps, 0x662C, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=
|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|=
No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecifi=
ed|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> -vscalefsd, 0x662D, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0F38=
|VexVVVV|VexW1|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No=
_ldSuf|StaticRounding|SAE, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, Re=
gXMM }
> -vscalefss, 0x662D, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0F38=
|VexVVVV|VexW0|Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No=
_ldSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, Re=
gXMM }
> +vscalefp<sdh>, 0x662c, None, <sdh:cpu>, Modrm|Masking=3D3|<sdh:spc2>|Vex=
VVVV|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf=
|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|<sdh:e=
lem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> +vscalefs<sdh>, 0x662d, None, <sdh:cpu>, Modrm|EVexLIG|Masking=3D3|<sdh:s=
pc2>|VexVVVV|<sdh:vexw>|Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS=
uf|No_ldSuf|StaticRounding|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, =
RegXMM, RegXMM }
>
>  vgatherdpd, 0x6692, None, CpuAVX512F, Modrm|EVex=3D1|Masking=3D2|NoDefMa=
sk|Space0F38|VexW1|Disp8MemShift=3D3|VecSIB256|No_bSuf|No_wSuf|No_lSuf|No_s=
Suf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegZMM }
>  vgatherqpd, 0x6693, None, CpuAVX512F, Modrm|EVex=3D1|Masking=3D2|NoDefMa=
sk|Space0F38|VexW1|Disp8MemShift=3D3|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_s=
Suf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegZMM }
> @@ -2406,16 +2294,8 @@ vpgatherdd, 0x6690, None, CpuAVX512F, Mo
>  vgatherqps, 0x6693, None, CpuAVX512F, Modrm|EVex=3D1|Masking=3D2|NoDefMa=
sk|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_s=
Suf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegYMM }
>  vpgatherqd, 0x6691, None, CpuAVX512F, Modrm|EVex=3D1|Masking=3D2|NoDefMa=
sk|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_s=
Suf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegYMM }
>
> -vgetexppd, 0x6642, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexW1|B=
roadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|=
No_ldSuf|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|Re=
gYMM|RegZMM }
> -vgetexpps, 0x6642, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexW0|B=
roadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|=
No_ldSuf|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|Re=
gYMM|RegZMM }
> -vgetexpsd, 0x6643, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0F38=
|VexVVVV|VexW1|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No=
_ldSuf|SAE, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
> -vgetexpss, 0x6643, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0F38=
|VexVVVV|VexW0|Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No=
_ldSuf|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
> -
> -vgetmantpd, 0x6626, None, CpuAVX512F, Modrm|Masking=3D3|Space0F3A|VexW1|=
Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf=
|No_ldSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, Re=
gXMM|RegYMM|RegZMM }
> -vrndscalepd, 0x6609, None, CpuAVX512F, Modrm|Masking=3D3|Space0F3A|VexW1=
|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu=
f|No_ldSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, R=
egXMM|RegYMM|RegZMM }
> -
> -vgetmantps, 0x6626, None, CpuAVX512F, Modrm|Masking=3D3|Space0F3A|VexW0|=
Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf=
|No_ldSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, Re=
gXMM|RegYMM|RegZMM }
> -vrndscaleps, 0x6608, None, CpuAVX512F, Modrm|Masking=3D3|Space0F3A|VexW0=
|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu=
f|No_ldSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, R=
egXMM|RegYMM|RegZMM }
> +vgetexpp<sdh>, 0x6642, None, <sdh:cpu>, Modrm|Masking=3D3|<sdh:spc2>|<sd=
h:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf=
|No_qSuf|No_ldSuf|SAE, { RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIn=
dex, RegXMM|RegYMM|RegZMM }
> +vgetexps<sdh>, 0x6643, None, <sdh:cpu>, Modrm|EVexLIG|Masking=3D3|<sdh:s=
pc2>|VexVVVV|<sdh:vexw>|Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS=
uf|No_ldSuf|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM, RegXMM =
}
>
>  vinsertf32x4, 0x6618, None, CpuAVX512F, Modrm|Masking=3D3|Space0F3A|VexV=
VVV=3D1|VexW=3D1|Disp8MemShift=3D4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_=
sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|XMMword|Unspecified|BaseIndex, RegYMM=
|RegZMM, RegYMM|RegZMM }
>  vinserti32x4, 0x6638, None, CpuAVX512F, Modrm|Masking=3D3|Space0F3A|VexV=
VVV=3D1|VexW=3D1|Disp8MemShift=3D4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_=
sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|XMMword|Unspecified|BaseIndex, RegYMM=
|RegZMM, RegYMM|RegZMM }
> @@ -2425,25 +2305,15 @@ vinserti64x4, 0x663A, None, CpuAVX512F,
>
>  vinsertps, 0x6621, None, CpuAVX512F, Modrm|EVex128|Space0F3A|VexVVVV|Vex=
W0|Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Im=
m8, RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
>
> -vmaxpd, 0x665F, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV|VexW=
1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS=
uf|No_ldSuf|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM=
|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> -vminpd, 0x665D, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV|VexW=
1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS=
uf|No_ldSuf|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM=
|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> -
> -vmaxps, 0x5F, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV|VexW0|=
Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf=
|No_ldSuf|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|R=
egYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> -vminps, 0x5D, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV|VexW0|=
Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf=
|No_ldSuf|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|R=
egYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> -
> -vmaxsd, 0xF25F, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0F|VexV=
VVV|VexW1|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSu=
f|SAE, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
> -vminsd, 0xF25D, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0F|VexV=
VVV|VexW1|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSu=
f|SAE, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
> -
> -vmaxss, 0xF35F, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0F|VexV=
VVV|VexW0|Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSu=
f|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
> -vminss, 0xF35D, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0F|VexV=
VVV|VexW0|Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSu=
f|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
> +vmaxp<sdh>, 0x<sdh:ppfx>5f, None, <sdh:cpu>, Modrm|Masking=3D3|<sdh:spc1=
>|VexVVVV|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No=
_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspe=
cified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> +vmaxs<sdh>, 0x<sdh:spfx>5f, None, <sdh:cpu>, Modrm|EVexLIG|Masking=3D3|<=
sdh:spc1>|VexVVVV|<sdh:vexw>|Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|=
No_qSuf|No_ldSuf|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM, Re=
gXMM }
>
> -vmovapd, 0x6628, None, CpuAVX512F, D|Modrm|MaskingMorZ|Space0F|VexW=3D2|=
Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,=
 { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
> -vmovntpd, 0x662B, None, CpuAVX512F, Modrm|Space0F|VexW=3D2|Disp8ShiftVL|=
CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Reg=
YMM|RegZMM, XMMword|YMMword|ZMMword|Unspecified|BaseIndex }
> -vmovupd, 0x6610, None, CpuAVX512F, D|Modrm|Load|MaskingMorZ|Space0F|VexW=
=3D2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_l=
dSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
> +vminp<sdh>, 0x<sdh:ppfx>5d, None, <sdh:cpu>, Modrm|Masking=3D3|<sdh:spc1=
>|VexVVVV|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No=
_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspe=
cified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> +vmins<sdh>, 0x<sdh:spfx>5d, None, <sdh:cpu>, Modrm|EVexLIG|Masking=3D3|<=
sdh:spc1>|VexVVVV|<sdh:vexw>|Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|=
No_qSuf|No_ldSuf|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM, Re=
gXMM }
>
> -vmovaps, 0x28, None, CpuAVX512F, D|Modrm|MaskingMorZ|Space0F|VexW=3D1|Di=
sp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {=
 RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
> -vmovntps, 0x2B, None, CpuAVX512F, Modrm|Space0F|VexW=3D1|Disp8ShiftVL|Ch=
eckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYM=
M|RegZMM, XMMword|YMMword|ZMMword|Unspecified|BaseIndex }
> -vmovups, 0x10, None, CpuAVX512F, D|Modrm|MaskingMorZ|Space0F|VexW=3D1|Di=
sp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {=
 RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
> +vmovap<sd>, 0x<sd:ppfx>28, None, CpuAVX512F, D|Modrm|MaskingMorZ|Space0F=
|<sd:vexw>|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu=
f|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|Reg=
ZMM }
> +vmovntp<sd>, 0x<sd:ppfx>2B, None, CpuAVX512F, Modrm|Space0F|<sd:vexw>|Di=
sp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {=
 RegXMM|RegYMM|RegZMM, XMMword|YMMword|ZMMword|Unspecified|BaseIndex }
> +vmovup<sd>, 0x<sd:ppfx>10, None, CpuAVX512F, D|Modrm|MaskingMorZ|Space0F=
|<sd:vexw>|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu=
f|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|Reg=
ZMM }
>
>  vmovd, 0x666E, None, CpuAVX512F, D|Modrm|EVex=3D2|Space0F|Disp8MemShift=
=3D2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|U=
nspecified|BaseIndex, RegXMM }
>
> @@ -2458,36 +2328,23 @@ vmovdqu64, 0xF36F, None, CpuAVX512F, D|M
>  vmovhlps, 0x12, None, CpuAVX512F, Modrm|EVex=3D4|Space0F|VexVVVV=3D1|Vex=
W=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, R=
egXMM }
>  vmovlhps, 0x16, None, CpuAVX512F, Modrm|EVex=3D4|Space0F|VexVVVV=3D1|Vex=
W=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, R=
egXMM }
>
> -vmovhpd, 0x6616, None, CpuAVX512F, Modrm|EVex=3D4|Space0F|VexVVVV=3D1|Ve=
xW=3D2|Disp8MemShift=3D3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf=
|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
> -vmovhpd, 0x6617, None, CpuAVX512F, Modrm|EVex=3D4|Space0F|VexW=3D2|Disp8=
MemShift=3D3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {=
 RegXMM, Qword|Unspecified|BaseIndex }
> -vmovlpd, 0x6612, None, CpuAVX512F, Modrm|EVex=3D4|Space0F|VexVVVV=3D1|Ve=
xW=3D2|Disp8MemShift=3D3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf=
|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
> -vmovlpd, 0x6613, None, CpuAVX512F, Modrm|EVex=3D4|Space0F|VexW=3D2|Disp8=
MemShift=3D3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {=
 RegXMM, Qword|Unspecified|BaseIndex }
> -
> -vmovhps, 0x16, None, CpuAVX512F, Modrm|EVex=3D4|Space0F|VexVVVV=3D1|VexW=
=3D1|Disp8MemShift=3D3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N=
o_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
> -vmovhps, 0x17, None, CpuAVX512F, Modrm|EVex=3D4|Space0F|VexW=3D1|Disp8Me=
mShift=3D3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { R=
egXMM, Qword|Unspecified|BaseIndex }
> -vmovlps, 0x12, None, CpuAVX512F, Modrm|EVex=3D4|Space0F|VexVVVV=3D1|VexW=
=3D1|Disp8MemShift=3D3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N=
o_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
> -vmovlps, 0x13, None, CpuAVX512F, Modrm|EVex=3D4|Space0F|VexW=3D1|Disp8Me=
mShift=3D3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { R=
egXMM, Qword|Unspecified|BaseIndex }
> +vmovhp<sd>, 0x<sd:ppfx>16, None, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVV=
VV|<sd:vexw>|Disp8MemShift=3D3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N=
o_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
> +vmovhp<sd>, 0x<sd:ppfx>17, None, CpuAVX512F, Modrm|EVexLIG|Space0F|<sd:v=
exw>|Disp8MemShift=3D3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N=
o_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex }
> +vmovlp<sd>, 0x<sd:ppfx>12, None, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVV=
VV|<sd:vexw>|Disp8MemShift=3D3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N=
o_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
> +vmovlp<sd>, 0x<sd:ppfx>13, None, CpuAVX512F, Modrm|EVexLIG|Space0F|<sd:v=
exw>|Disp8MemShift=3D3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N=
o_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex }
>
>  vmovq, 0x666E, None, CpuAVX512F|Cpu64, D|Modrm|EVex=3D2|Space0F|VexW=3D2=
|Disp8MemShift=3D3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ld=
Suf, { Reg64|Unspecified|BaseIndex, RegXMM }
>  vmovq, 0xF37E, None, CpuAVX512F, Load|Modrm|EVex=3D2|Space0F|VexW1|Disp8=
MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unsp=
ecified|BaseIndex|RegXMM, RegXMM }
>  vmovq, 0x66D6, None, CpuAVX512F, Modrm|EVex=3D2|Space0F|VexW1|Disp8MemSh=
ift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|U=
nspecified|BaseIndex|RegXMM }
>
> -vmovsd, 0xF210, None, CpuAVX512F, D|Modrm|EVex=3D4|MaskingMorZ|Space0F|V=
exW=3D2|Disp8MemShift=3D3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu=
f|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
> -vmovsd, 0xF210, None, CpuAVX512F, D|Modrm|EVex=3D4|Masking=3D3|Space0F|V=
exVVVV=3D1|VexW=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg=
XMM, RegXMM, RegXMM }
> +vmovs<sdh>, 0x<sdh:spfx>10, None, <sdh:cpu>, D|Modrm|EVexLIG|MaskingMorZ=
|<sdh:spc1>|<sdh:vexw>|Disp8MemShift|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_=
sSuf|No_qSuf|No_ldSuf, { <sdh:elem>|Unspecified|BaseIndex, RegXMM }
> +vmovs<sdh>, 0x<sdh:spfx>10, None, <sdh:cpu>, D|Modrm|EVexLIG|Masking=3D3=
|<sdh:spc1>|VexVVVV|<sdh:vexw>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_l=
dSuf, { RegXMM, RegXMM, RegXMM }
>
>  vmovshdup, 0xF316, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexW=3D1|=
Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,=
 { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
>  vmovsldup, 0xF312, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexW=3D1|=
Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,=
 { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
>
> -vmovss, 0xF310, None, CpuAVX512F, D|Modrm|EVex=3D4|MaskingMorZ|Space0F|V=
exW=3D1|Disp8MemShift=3D2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu=
f|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM }
> -vmovss, 0xF310, None, CpuAVX512F, D|Modrm|EVex=3D4|Masking=3D3|Space0F|V=
exVVVV=3D1|VexW=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg=
XMM, RegXMM, RegXMM }
> -
>  vpabsd, 0x661E, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexW=3D1|B=
roadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|=
No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM=
|RegZMM }
> -vrcp14ps, 0x664C, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexW=3D1=
|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu=
f|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegY=
MM|RegZMM }
> -vrsqrt14ps, 0x664E, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexW=
=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No=
_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|=
RegYMM|RegZMM }
> -
>  vpabsq, 0x661F, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexW=3D2|B=
roadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|=
No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM=
|RegZMM }
> -vrcp14pd, 0x664C, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexW=3D2=
|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu=
f|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegY=
MM|RegZMM }
> -vrsqrt14pd, 0x664E, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexW=
=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No=
_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|=
RegYMM|RegZMM }
>
>  vpaddd, 0x66FE, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D1|=
VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSu=
f|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, Reg=
XMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
>  vpandd, 0x66DB, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D1|=
VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSu=
f|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseI=
ndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> @@ -2507,8 +2364,6 @@ vpsubq, 0x66FB, None, CpuAVX512F, Modrm|
>  vpunpckhqdq, 0x666D, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=
=3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N=
o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex=
, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
>  vpunpcklqdq, 0x666C, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=
=3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N=
o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex=
, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
>  vpxorq, 0x66EF, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D1|=
VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSu=
f|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseI=
ndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> -vunpckhpd, 0x6615, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=
=3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N=
o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex=
, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> -vunpcklpd, 0x6614, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=
=3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N=
o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex=
, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
>
>  vpbroadcastq, 0x6659, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexW=
1|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg=
XMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
>  vpbroadcastq, 0x667C, None, CpuAVX512F|Cpu64, Modrm|Masking=3D3|Space0F3=
8|VexW=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg64, RegXM=
M|RegYMM|RegZMM }
> @@ -2538,11 +2393,8 @@ vptestnmq, 0xF327, None, CpuAVX512F, Mod
>  vpermd, 0x6636, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=3D=
1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_s=
Suf|No_qSuf|No_ldSuf, { RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|R=
egZMM, RegYMM|RegZMM }
>  vpermps, 0x6616, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=
=3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N=
o_sSuf|No_qSuf|No_ldSuf, { RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYM=
M|RegZMM, RegYMM|RegZMM }
>
> -vpermilpd, 0x6605, None, CpuAVX512F, Modrm|Masking=3D3|Space0F3A|VexW=3D=
2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS=
uf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegX=
MM|RegYMM|RegZMM }
> -vpermilpd, 0x660D, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=
=3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N=
o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex=
, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> -
> -vpermilps, 0x6604, None, CpuAVX512F, Modrm|Masking=3D3|Space0F3A|VexW=3D=
1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS=
uf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegX=
MM|RegYMM|RegZMM }
> -vpermilps, 0x660C, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=
=3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N=
o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex=
, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> +vpermilp<sd>, 0x6604 | <sd:opc>, None, CpuAVX512F, Modrm|Masking=3D3|Spa=
ce0F3A|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSu=
f|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecif=
ied|BaseIndex, RegXMM|RegYMM|RegZMM }
> +vpermilp<sd>, 0x660C | <sd:opc>, None, CpuAVX512F, Modrm|Masking=3D3|Spa=
ce0F38|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSu=
f|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspec=
ified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
>
>  vpermpd, 0x6601, None, CpuAVX512F, Modrm|Masking=3D3|Space0F3A|VexW=3D2|=
Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf=
|No_ldSuf, { Imm8, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM=
 }
>  vpermpd, 0x6616, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=
=3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N=
o_sSuf|No_qSuf|No_ldSuf, { RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYM=
M|RegZMM, RegYMM|RegZMM }
> @@ -2609,11 +2461,11 @@ vpsraq, 0x6672, 4, CpuAVX512F, Modrm|Mas
>  vpsrlq, 0x66D3, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D1|=
VexW=3D2|Disp8MemShift=3D4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_=
qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM=
|RegYMM|RegZMM }
>  vpsrlq, 0x6673, 2, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D2|Vex=
W=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N=
o_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, =
RegXMM|RegYMM|RegZMM }
>
> -vrcp14sd, 0x664D, None, CpuAVX512F, Modrm|EVex=3D4|Masking=3D3|Space0F38=
|VexVVVV|VexW1|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No=
_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
> -vrsqrt14sd, 0x664F, None, CpuAVX512F, Modrm|EVex=3D4|Masking=3D3|Space0F=
38|VexVVVV|VexW1|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|=
No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
> +vrcp14p<sd>, 0x664C, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|<sd:v=
exw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No=
_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, Reg=
XMM|RegYMM|RegZMM }
> +vrcp14s<sd>, 0x664D, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0F=
38|VexVVVV|<sd:vexw>|Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|=
No_ldSuf, { RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegXMM }
>
> -vrcp14ss, 0x664D, None, CpuAVX512F, Modrm|EVex=3D4|Masking=3D3|Space0F38=
|VexVVVV|VexW0|Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No=
_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
> -vrsqrt14ss, 0x664F, None, CpuAVX512F, Modrm|EVex=3D4|Masking=3D3|Space0F=
38|VexVVVV|VexW0|Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|=
No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
> +vrsqrt14p<sd>, 0x664E, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|<sd=
:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|=
No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, R=
egXMM|RegYMM|RegZMM }
> +vrsqrt14s<sd>, 0x664F, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space=
0F38|VexVVVV|<sd:vexw>|Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu=
f|No_ldSuf, { RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegXMM }
>
>  vshuff32x4, 0x6623, None, CpuAVX512F, Modrm|Masking=3D3|Space0F3A|VexVVV=
V=3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|=
No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|RegZMM|Dword|Unspecified|BaseIndex=
, RegYMM|RegZMM, RegYMM|RegZMM }
>  vshufi32x4, 0x6643, None, CpuAVX512F, Modrm|Masking=3D3|Space0F3A|VexVVV=
V=3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|=
No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|RegZMM|Dword|Unspecified|BaseIndex=
, RegYMM|RegZMM, RegYMM|RegZMM }
> @@ -2621,14 +2473,10 @@ vshufi32x4, 0x6643, None, CpuAVX512F, Mo
>  vshuff64x2, 0x6623, None, CpuAVX512F, Modrm|Masking=3D3|Space0F3A|VexVVV=
V=3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|=
No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|RegZMM|Qword|Unspecified|BaseIndex=
, RegYMM|RegZMM, RegYMM|RegZMM }
>  vshufi64x2, 0x6643, None, CpuAVX512F, Modrm|Masking=3D3|Space0F3A|VexVVV=
V=3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|=
No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|RegZMM|Qword|Unspecified|BaseIndex=
, RegYMM|RegZMM, RegYMM|RegZMM }
>
> -vshufpd, 0x66C6, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D1=
|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS=
uf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseInd=
ex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> -
> -vshufps, 0xC6, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D1|V=
exW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf=
|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex=
, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> -
> -vsqrtpd, 0x6651, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexW1|Broad=
cast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_l=
dSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex=
, RegXMM|RegYMM|RegZMM }
> +vshufp<sd>, 0x<sd:ppfx>C6, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|V=
exVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSu=
f|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecif=
ied|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
>
> -vunpckhps, 0x15, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D1=
|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS=
uf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, Re=
gXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> -vunpcklps, 0x14, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D1=
|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS=
uf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, Re=
gXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> +vunpckhp<sd>, 0x<sd:ppfx>15, None, CpuAVX512F, Modrm|Masking=3D3|Space0F=
|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_l=
Suf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|=
BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> +vunpcklp<sd>, 0x<sd:ppfx>14, None, CpuAVX512F, Modrm|Masking=3D3|Space0F=
|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_l=
Suf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|=
BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
>
>  // AVX512F instructions end.
>
> @@ -2647,42 +2495,31 @@ vplzcntq, 0x6644, None, CpuAVX512CD, Mod
>
>  // AVX512ER instructions.
>
> -vexp2pd, 0x66C8, None, CpuAVX512ER, Modrm|EVex512|Masking=3D3|Space0F38|=
VexW1|Broadcast|Disp8MemShift=3D6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N=
o_ldSuf|SAE, { RegZMM|Qword|Unspecified|BaseIndex, RegZMM }
> -vexp2ps, 0x66C8, None, CpuAVX512ER, Modrm|EVex512|Masking=3D3|Space0F38|=
VexW0|Broadcast|Disp8MemShift=3D6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N=
o_ldSuf|SAE, { RegZMM|Dword|Unspecified|BaseIndex, RegZMM }
> -
> -vrcp28pd, 0x66CA, None, CpuAVX512ER, Modrm|EVex512|Masking=3D3|Space0F38=
|VexW1|Broadcast|Disp8MemShift=3D6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|=
No_ldSuf|SAE, { RegZMM|Qword|Unspecified|BaseIndex, RegZMM }
> -vrsqrt28pd, 0x66CC, None, CpuAVX512ER, Modrm|EVex512|Masking=3D3|Space0F=
38|VexW1|Broadcast|Disp8MemShift=3D6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu=
f|No_ldSuf|SAE, { RegZMM|Qword|Unspecified|BaseIndex, RegZMM }
> -
> -vrcp28ps, 0x66CA, None, CpuAVX512ER, Modrm|EVex512|Masking=3D3|Space0F38=
|VexW0|Broadcast|Disp8MemShift=3D6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|=
No_ldSuf|SAE, { RegZMM|Dword|Unspecified|BaseIndex, RegZMM }
> -vrsqrt28ps, 0x66CC, None, CpuAVX512ER, Modrm|EVex512|Masking=3D3|Space0F=
38|VexW0|Broadcast|Disp8MemShift=3D6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu=
f|No_ldSuf|SAE, { RegZMM|Dword|Unspecified|BaseIndex, RegZMM }
> +vexp2p<sd>, 0x66C8, None, CpuAVX512ER, Modrm|EVex512|Masking=3D3|Space0F=
38|<sd:vexw>|Broadcast|Disp8MemShift=3D6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No=
_qSuf|No_ldSuf|SAE, { RegZMM|<sd:elem>|Unspecified|BaseIndex, RegZMM }
>
> -vrcp28sd, 0x66CB, None, CpuAVX512ER, Modrm|EVexLIG|Masking=3D3|Space0F38=
|VexVVVV|VexW1|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No=
_ldSuf|SAE, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
> -vrsqrt28sd, 0x66CD, None, CpuAVX512ER, Modrm|EVexLIG|Masking=3D3|Space0F=
38|VexVVVV|VexW1|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|=
No_ldSuf|SAE, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
> +vrcp28p<sd>, 0x66CA, None, CpuAVX512ER, Modrm|EVex512|Masking=3D3|Space0=
F38|<sd:vexw>|Broadcast|Disp8MemShift=3D6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N=
o_qSuf|No_ldSuf|SAE, { RegZMM|<sd:elem>|Unspecified|BaseIndex, RegZMM }
> +vrcp28s<sd>, 0x66CB, None, CpuAVX512ER, Modrm|EVexLIG|Masking=3D3|Space0=
F38|VexVVVV|<sd:vexw>|Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf=
|No_ldSuf|SAE, { RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegXMM }
>
> -vrcp28ss, 0x66CB, None, CpuAVX512ER, Modrm|EVexLIG|Masking=3D3|Space0F38=
|VexVVVV|VexW0|Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No=
_ldSuf|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
> -vrsqrt28ss, 0x66CD, None, CpuAVX512ER, Modrm|EVexLIG|Masking=3D3|Space0F=
38|VexVVVV|VexW0|Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|=
No_ldSuf|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
> +vrsqrt28p<sd>, 0x66CC, None, CpuAVX512ER, Modrm|EVex512|Masking=3D3|Spac=
e0F38|<sd:vexw>|Broadcast|Disp8MemShift=3D6|No_bSuf|No_wSuf|No_lSuf|No_sSuf=
|No_qSuf|No_ldSuf|SAE, { RegZMM|<sd:elem>|Unspecified|BaseIndex, RegZMM }
> +vrsqrt28s<sd>, 0x66CD, None, CpuAVX512ER, Modrm|EVexLIG|Masking=3D3|Spac=
e0F38|VexVVVV|<sd:vexw>|Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS=
uf|No_ldSuf|SAE, { RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegXMM }
>
>  // AVX512ER instructions end.
>
>  // AVX512PF instructions.
>
>  vgatherpf0dpd, 0x66C6, 1, CpuAVX512PF, Modrm|EVex=3D1|Masking=3D2|NoDefM=
ask|Space0F38|VexW1|Disp8MemShift=3D3|VecSIB256|No_bSuf|No_wSuf|No_lSuf|No_=
sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex }
> -vgatherpf0qpd, 0x66C7, 1, CpuAVX512PF, Modrm|EVex=3D1|Masking=3D2|NoDefM=
ask|Space0F38|VexW1|Disp8MemShift=3D3|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_=
sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex }
> +vgatherpf0qp<sd>, 0x66C7, 1, CpuAVX512PF, Modrm|EVex512|Masking=3D2|NoDe=
fMask|Space0F38|<sd:vexw>|Disp8MemShift|VecSIB512|No_bSuf|No_wSuf|No_lSuf|N=
o_sSuf|No_qSuf|No_ldSuf, { <sd:elem>|Unspecified|BaseIndex }
>  vgatherpf1dpd, 0x66C6, 2, CpuAVX512PF, Modrm|EVex=3D1|Masking=3D2|NoDefM=
ask|Space0F38|VexW1|Disp8MemShift=3D3|VecSIB256|No_bSuf|No_wSuf|No_lSuf|No_=
sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex }
> -vgatherpf1qpd, 0x66C7, 2, CpuAVX512PF, Modrm|EVex=3D1|Masking=3D2|NoDefM=
ask|Space0F38|VexW1|Disp8MemShift=3D3|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_=
sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex }
> +vgatherpf1qp<sd>, 0x66C7, 2, CpuAVX512PF, Modrm|EVex512|Masking=3D2|NoDe=
fMask|Space0F38|<sd:vexw>|Disp8MemShift|VecSIB512|No_bSuf|No_wSuf|No_lSuf|N=
o_sSuf|No_qSuf|No_ldSuf, { <sd:elem>|Unspecified|BaseIndex }
>  vscatterpf0dpd, 0x66C6, 5, CpuAVX512PF, Modrm|EVex=3D1|Masking=3D2|NoDef=
Mask|Space0F38|VexW1|Disp8MemShift=3D3|VecSIB256|No_bSuf|No_wSuf|No_lSuf|No=
_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex }
> -vscatterpf0qpd, 0x66C7, 5, CpuAVX512PF, Modrm|EVex=3D1|Masking=3D2|NoDef=
Mask|Space0F38|VexW1|Disp8MemShift=3D3|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No=
_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex }
> +vscatterpf0qp<sd>, 0x66C7, 5, CpuAVX512PF, Modrm|EVex512|Masking=3D2|NoD=
efMask|Space0F38|<sd:vexw>|Disp8MemShift|VecSIB512|No_bSuf|No_wSuf|No_lSuf|=
No_sSuf|No_qSuf|No_ldSuf, { <sd:elem>|Unspecified|BaseIndex }
>  vscatterpf1dpd, 0x66C6, 6, CpuAVX512PF, Modrm|EVex=3D1|Masking=3D2|NoDef=
Mask|Space0F38|VexW1|Disp8MemShift=3D3|VecSIB256|No_bSuf|No_wSuf|No_lSuf|No=
_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex }
> -vscatterpf1qpd, 0x66C7, 6, CpuAVX512PF, Modrm|EVex=3D1|Masking=3D2|NoDef=
Mask|Space0F38|VexW1|Disp8MemShift=3D3|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No=
_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex }
> +vscatterpf1qp<sd>, 0x66C7, 6, CpuAVX512PF, Modrm|EVex512|Masking=3D2|NoD=
efMask|Space0F38|<sd:vexw>|Disp8MemShift|VecSIB512|No_bSuf|No_wSuf|No_lSuf|=
No_sSuf|No_qSuf|No_ldSuf, { <sd:elem>|Unspecified|BaseIndex }
>
>  vgatherpf0dps, 0x66C6, 1, CpuAVX512PF, Modrm|EVex=3D1|Masking=3D2|NoDefM=
ask|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_=
sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex }
> -vgatherpf0qps, 0x66C7, 1, CpuAVX512PF, Modrm|EVex=3D1|Masking=3D2|NoDefM=
ask|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_=
sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex }
>  vgatherpf1dps, 0x66C6, 2, CpuAVX512PF, Modrm|EVex=3D1|Masking=3D2|NoDefM=
ask|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_=
sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex }
> -vgatherpf1qps, 0x66C7, 2, CpuAVX512PF, Modrm|EVex=3D1|Masking=3D2|NoDefM=
ask|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_=
sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex }
>  vscatterpf0dps, 0x66C6, 5, CpuAVX512PF, Modrm|EVex=3D1|Masking=3D2|NoDef=
Mask|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No=
_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex }
> -vscatterpf0qps, 0x66C7, 5, CpuAVX512PF, Modrm|EVex=3D1|Masking=3D2|NoDef=
Mask|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No=
_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex }
>  vscatterpf1dps, 0x66C6, 6, CpuAVX512PF, Modrm|EVex=3D1|Masking=3D2|NoDef=
Mask|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No=
_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex }
> -vscatterpf1qps, 0x66C7, 6, CpuAVX512PF, Modrm|EVex=3D1|Masking=3D2|NoDef=
Mask|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No=
_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex }
>
>  // AVX512PF instructions end.
>
> @@ -2725,7 +2562,7 @@ enclv, 0xf01c0, None, CpuSE1, No_bSuf|No
>  // AVX512VL instructions.
>
>  vgatherdpd, 0x6692, None, CpuAVX512F|CpuAVX512VL, Modrm|Masking=3D2|NoDe=
fMask|Space0F38|VexW1|Disp8MemShift=3D3|VecSIB128|No_bSuf|No_wSuf|No_lSuf|N=
o_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM|RegYMM }
> -vgatherqpd, 0x6693, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D2|Masking=
=3D2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3D3|VecSIB128|No_bSuf|No_wSuf|=
No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
> +vgatherqp<sd>, 0x6693, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Maski=
ng=3D2|NoDefMask|Space0F38|<sd:vexw>|Disp8MemShift|VecSIB128|No_bSuf|No_wSu=
f|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <sd:elem>|Unspecified|BaseIndex, RegX=
MM }
>  vgatherqpd, 0x6693, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D3|Masking=
=3D2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3D3|VecSIB256|No_bSuf|No_wSuf|=
No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegYMM }
>  vpgatherdq, 0x6690, None, CpuAVX512F|CpuAVX512VL, Modrm|Masking=3D2|NoDe=
fMask|Space0F38|VexW1|Disp8MemShift=3D3|VecSIB128|No_bSuf|No_wSuf|No_lSuf|N=
o_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM|RegYMM }
>  vpgatherqq, 0x6691, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D2|Masking=
=3D2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3D3|VecSIB128|No_bSuf|No_wSuf|=
No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
> @@ -2734,12 +2571,11 @@ vpscatterdq, 0x66A0, None, CpuAVX512F|Cp
>  vpscatterqq, 0x66A1, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D2|Maskin=
g=3D2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3D3|VecSIB128|No_bSuf|No_wSuf=
|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex }
>  vpscatterqq, 0x66A1, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D3|Maskin=
g=3D2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3D3|VecSIB256|No_bSuf|No_wSuf=
|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Qword|Unspecified|BaseIndex }
>  vscatterdpd, 0x66A2, None, CpuAVX512F|CpuAVX512VL, Modrm|Masking=3D2|NoD=
efMask|Space0F38|VexW1|Disp8MemShift=3D3|VecSIB128|No_bSuf|No_wSuf|No_lSuf|=
No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex }
> -vscatterqpd, 0x66A3, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D2|Maskin=
g=3D2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3D3|VecSIB128|No_bSuf|No_wSuf=
|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex }
> +vscatterqp<sd>, 0x66A3, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Mask=
ing=3D2|NoDefMask|Space0F38|<sd:vexw>|Disp8MemShift|VecSIB128|No_bSuf|No_wS=
uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, <sd:elem>|Unspecified|BaseIn=
dex }
>  vscatterqpd, 0x66A3, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D3|Maskin=
g=3D2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3D3|VecSIB256|No_bSuf|No_wSuf=
|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Qword|Unspecified|BaseIndex }
>
>  vgatherdps, 0x6692, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D2|Masking=
=3D2|NoDefMask|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB128|No_bSuf|No_wSuf|=
No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM }
>  vgatherdps, 0x6692, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D3|Masking=
=3D2|NoDefMask|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB256|No_bSuf|No_wSuf|=
No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegYMM }
> -vgatherqps, 0x6693, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D2|Masking=
=3D2|NoDefMask|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB128|No_bSuf|No_wSuf|=
No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM }
>  vgatherqps, 0x6693, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D3|Masking=
=3D2|NoDefMask|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB256|No_bSuf|No_wSuf|=
No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM }
>  vpgatherdd, 0x6690, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D2|Masking=
=3D2|NoDefMask|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB128|No_bSuf|No_wSuf|=
No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM }
>  vpgatherdd, 0x6690, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D3|Masking=
=3D2|NoDefMask|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB256|No_bSuf|No_wSuf|=
No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegYMM }
> @@ -2751,7 +2587,6 @@ vpscatterqd, 0x66A1, None, CpuAVX512F|Cp
>  vpscatterqd, 0x66A1, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D3|Maskin=
g=3D2|NoDefMask|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB256|No_bSuf|No_wSuf=
|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex }
>  vscatterdps, 0x66A2, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D2|Maskin=
g=3D2|NoDefMask|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB128|No_bSuf|No_wSuf=
|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex }
>  vscatterdps, 0x66A2, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D3|Maskin=
g=3D2|NoDefMask|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB256|No_bSuf|No_wSuf=
|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Dword|Unspecified|BaseIndex }
> -vscatterqps, 0x66A3, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D2|Maskin=
g=3D2|NoDefMask|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB128|No_bSuf|No_wSuf=
|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex }
>  vscatterqps, 0x66A3, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D3|Maskin=
g=3D2|NoDefMask|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB256|No_bSuf|No_wSuf=
|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex }
>
>  vcvtdq2pd, 0xF3E6, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=
=3D3|Space0F|VexW0|Broadcast|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_s=
Suf|No_qSuf|No_ldSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM }
> @@ -3052,15 +2887,10 @@ ktestw, 0x99, None, CpuAVX512DQ, Modrm|V
>  kshiftlb, 0x6632, None, CpuAVX512DQ, Modrm|Vex=3D1|Space0F3A|VexW=3D1|No=
_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMask, RegMask }
>  kshiftrb, 0x6630, None, CpuAVX512DQ, Modrm|Vex=3D1|Space0F3A|VexW=3D1|No=
_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMask, RegMask }
>
> -vandnpd, 0x6655, None, CpuAVX512DQ, Modrm|Masking=3D3|Space0F|VexVVVV=3D=
1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_s=
Suf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|Bas=
eIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> -vandpd, 0x6654, None, CpuAVX512DQ, Modrm|Masking=3D3|Space0F|VexVVVV=3D1=
|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS=
uf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, Re=
gXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> -vorpd, 0x6656, None, CpuAVX512DQ, Modrm|Masking=3D3|Space0F|VexVVVV=3D1|=
VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSu=
f|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, Reg=
XMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> -vxorpd, 0x6657, None, CpuAVX512DQ, Modrm|Masking=3D3|Space0F|VexVVVV=3D1=
|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS=
uf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|Base=
Index, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> -
> -vandnps, 0x55, None, CpuAVX512DQ, Modrm|Masking=3D3|Space0F|VexVVVV=3D1|=
VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSu=
f|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseI=
ndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> -vandps, 0x54, None, CpuAVX512DQ, Modrm|Masking=3D3|Space0F|VexVVVV=3D1|V=
exW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf=
|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegX=
MM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> -vorps, 0x56, None, CpuAVX512DQ, Modrm|Masking=3D3|Space0F|VexVVVV=3D1|Ve=
xW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|=
No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXM=
M|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> -vxorps, 0x57, None, CpuAVX512DQ, Modrm|Masking=3D3|Space0F|VexVVVV=3D1|V=
exW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf=
|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIn=
dex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> +vandnp<sd>, 0x<sd:ppfx>55, None, CpuAVX512DQ, Modrm|Masking=3D3|Space0F|=
VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lS=
uf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unsp=
ecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> +vandp<sd>, 0x<sd:ppfx>54, None, CpuAVX512DQ, Modrm|Masking=3D3|Space0F|V=
exVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSu=
f|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|Ba=
seIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> +vorp<sd>, 0x<sd:ppfx>56, None, CpuAVX512DQ, Modrm|Masking=3D3|Space0F|Ve=
xVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf=
|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|Bas=
eIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> +vxorp<sd>, 0x<sd:ppfx>57, None, CpuAVX512DQ, Modrm|Masking=3D3|Space0F|V=
exVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSu=
f|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspe=
cified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
>
>  vbroadcastf32x2, 0x6619, None, CpuAVX512DQ, Modrm|Masking=3D3|Space0F38|=
VexW0|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {=
 RegXMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM }
>  vbroadcastf32x8, 0x661B, None, CpuAVX512DQ, Modrm|EVex=3D1|Masking=3D3|S=
pace0F38|VexW=3D1|Disp8MemShift=3D5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf=
|No_ldSuf, { YMMword|Unspecified|BaseIndex, RegZMM }
> @@ -3110,11 +2940,9 @@ vextracti32x8, 0x663B, None, CpuAVX512DQ
>  vinsertf32x8, 0x661A, None, CpuAVX512DQ, Modrm|EVex=3D1|Masking=3D3|Spac=
e0F3A|VexVVVV=3D1|VexW=3D1|Disp8MemShift=3D5|No_bSuf|No_wSuf|No_lSuf|No_sSu=
f|No_qSuf|No_ldSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM }
>  vinserti32x8, 0x663A, None, CpuAVX512DQ, Modrm|EVex=3D1|Masking=3D3|Spac=
e0F3A|VexVVVV=3D1|VexW=3D1|Disp8MemShift=3D5|No_bSuf|No_wSuf|No_lSuf|No_sSu=
f|No_qSuf|No_ldSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM }
>
> -vfpclassss, 0x6667, None, CpuAVX512DQ, Modrm|EVex=3D4|Masking=3D2|Space0=
F3A|VexW0|Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSu=
f, { Imm8, RegXMM|Dword|Unspecified|BaseIndex, RegMask }
>  vpextrd, 0x6616, None, CpuAVX512DQ, Modrm|EVex128|Space0F3A|Disp8MemShif=
t=3D2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, =
RegXMM, Reg32|Dword|Unspecified|BaseIndex }
>  vpinsrd, 0x6622, None, CpuAVX512DQ, Modrm|EVex128|Space0F3A|VexVVVV=3D1|=
Disp8MemShift=3D2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS=
uf, { Imm8, Reg32|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
>
> -vfpclasssd, 0x6667, None, CpuAVX512DQ, Modrm|EVex=3D4|Masking=3D2|Space0=
F3A|VexW1|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSu=
f, { Imm8, RegXMM|Qword|Unspecified|BaseIndex, RegMask }
>  vpextrq, 0x6616, None, CpuAVX512DQ|Cpu64, Modrm|EVex128|Space0F3A|VexW1|=
Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8,=
 RegXMM, Reg64|Unspecified|BaseIndex }
>  vpinsrq, 0x6622, None, CpuAVX512DQ|Cpu64, Modrm|EVex128|Space0F3A|VexVVV=
V=3D1|VexW1|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ld=
Suf, { Imm8, Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
>
> @@ -3123,17 +2951,12 @@ vextracti64x2, 0x6639, None, CpuAVX512DQ
>  vinsertf64x2, 0x6618, None, CpuAVX512DQ, Modrm|Masking=3D3|Space0F3A|Vex=
VVVV=3D1|VexW=3D2|Disp8MemShift=3D4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No=
_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM=
, RegYMM|RegZMM }
>  vinserti64x2, 0x6638, None, CpuAVX512DQ, Modrm|Masking=3D3|Space0F3A|Vex=
VVVV=3D1|VexW=3D2|Disp8MemShift=3D4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No=
_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM=
, RegYMM|RegZMM }
>
> -vfpclasspd, 0x6666, None, CpuAVX512DQ, Modrm|Masking=3D2|Space0F3A|VexW=
=3D2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSu=
f|ATTSyntax, { Imm8, RegXMM|RegYMM|RegZMM|Qword|BaseIndex, RegMask }
> -vfpclasspd, 0x6666, None, CpuAVX512DQ, Modrm|Masking=3D2|Space0F3A|VexW=
=3D2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSu=
f|IntelSyntax, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, Re=
gMask }
> -vfpclasspdz, 0x6666, None, CpuAVX512DQ, Modrm|EVex=3D1|Masking=3D2|Space=
0F3A|VexW=3D2|Broadcast|Disp8MemShift=3D6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N=
o_qSuf|No_ldSuf, { Imm8, RegZMM|Qword|Unspecified|BaseIndex, RegMask }
> -vfpclasspdx, 0x6666, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex=3D2|Maski=
ng=3D2|Space0F3A|VexW=3D2|Broadcast|Disp8MemShift=3D4|No_bSuf|No_wSuf|No_lS=
uf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Qword|Unspecified|BaseIndex, Re=
gMask }
> -vfpclasspdy, 0x6666, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex=3D3|Maski=
ng=3D2|Space0F3A|VexW=3D2|Broadcast|Disp8MemShift=3D5|No_bSuf|No_wSuf|No_lS=
uf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Qword|Unspecified|BaseIndex, Re=
gMask }
> -
> -vfpclassps, 0x6666, None, CpuAVX512DQ, Modrm|Masking=3D2|Space0F3A|VexW=
=3D1|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSu=
f|ATTSyntax, { Imm8, RegXMM|RegYMM|RegZMM|Dword|BaseIndex, RegMask }
> -vfpclassps, 0x6666, None, CpuAVX512DQ, Modrm|Masking=3D2|Space0F3A|VexW=
=3D1|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSu=
f|IntelSyntax, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, Re=
gMask }
> -vfpclasspsz, 0x6666, None, CpuAVX512DQ, Modrm|EVex=3D1|Masking=3D2|Space=
0F3A|VexW=3D1|Broadcast|Disp8MemShift=3D6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N=
o_qSuf|No_ldSuf, { Imm8, RegZMM|Dword|Unspecified|BaseIndex, RegMask }
> -vfpclasspsx, 0x6666, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex=3D2|Maski=
ng=3D2|Space0F3A|VexW=3D1|Broadcast|Disp8MemShift=3D4|No_bSuf|No_wSuf|No_lS=
uf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Dword|Unspecified|BaseIndex, Re=
gMask }
> -vfpclasspsy, 0x6666, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex=3D3|Maski=
ng=3D2|Space0F3A|VexW=3D1|Broadcast|Disp8MemShift=3D5|No_bSuf|No_wSuf|No_lS=
uf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Dword|Unspecified|BaseIndex, Re=
gMask }
> +vfpclassp<sd>, 0x6666, None, CpuAVX512DQ, Modrm|Masking=3D2|Space0F3A|<s=
d:vexw>|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_l=
dSuf|ATTSyntax, { Imm8, RegXMM|RegYMM|RegZMM|<sd:elem>|BaseIndex, RegMask }
> +vfpclassp<sd>, 0x6666, None, CpuAVX512DQ, Modrm|Masking=3D2|Space0F3A|<s=
d:vexw>|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_l=
dSuf|IntelSyntax, { Imm8, RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIn=
dex, RegMask }
> +vfpclassp<sd>z, 0x6666, None, CpuAVX512DQ, Modrm|EVex512|Masking=3D2|Spa=
ce0F3A|<sd:vexw>|Broadcast|Disp8MemShift=3D6|No_bSuf|No_wSuf|No_lSuf|No_sSu=
f|No_qSuf|No_ldSuf, { Imm8, RegZMM|<sd:elem>|Unspecified|BaseIndex, RegMask=
 }
> +vfpclassp<sd>x, 0x6666, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex128|Mas=
king=3D2|Space0F3A|<sd:vexw>|Broadcast|Disp8MemShift=3D4|No_bSuf|No_wSuf|No=
_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|<sd:elem>|Unspecified|BaseIn=
dex, RegMask }
> +vfpclassp<sd>y, 0x6666, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex256|Mas=
king=3D2|Space0F3A|<sd:vexw>|Broadcast|Disp8MemShift=3D5|No_bSuf|No_wSuf|No=
_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|<sd:elem>|Unspecified|BaseIn=
dex, RegMask }
> +vfpclasss<sdh>, 0x<sdh:pfx>67, None, <sdh:cpudq>, Modrm|EVexLIG|Masking=
=3D2|Space0F3A|<sdh:vexw>|Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_=
qSuf|No_ldSuf, { Imm8, RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegMask }
>
>  vpmovd2m, 0xF339, None, CpuAVX512DQ, Modrm|EVex=3D5|Space0F38|VexW=3D1|N=
o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, Re=
gMask }
>  vpmovq2m, 0xF339, None, CpuAVX512DQ, Modrm|EVex=3D5|Space0F38|VexW=3D2|N=
o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, Re=
gMask }
> @@ -3143,17 +2966,11 @@ vpmovm2q, 0xF338, None, CpuAVX512DQ, Mod
>
>  vpmullq, 0x6640, None, CpuAVX512DQ, Modrm|Masking=3D3|Space0F38|VexVVVV=
=3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N=
o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex=
, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
>
> -vrangepd, 0x6650, None, CpuAVX512DQ, Modrm|Masking=3D3|Space0F3A|VexVVVV=
|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|=
No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIn=
dex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> -vreducepd, 0x6656, None, CpuAVX512DQ, Modrm|Masking=3D3|Space0F3A|VexW1|=
Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf=
|No_ldSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, Re=
gXMM|RegYMM|RegZMM }
> -
> -vrangeps, 0x6650, None, CpuAVX512DQ, Modrm|Masking=3D3|Space0F3A|VexVVVV=
|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|=
No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIn=
dex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> -vreduceps, 0x6656, None, CpuAVX512DQ, Modrm|Masking=3D3|Space0F3A|VexW0|=
Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf=
|No_ldSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, Re=
gXMM|RegYMM|RegZMM }
> -
> -vrangesd, 0x6651, None, CpuAVX512DQ, Modrm|EVexLIG|Masking=3D3|Space0F3A=
|VexVVVV|VexW1|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No=
_ldSuf|SAE, { Imm8, RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
> -vreducesd, 0x6657, None, CpuAVX512DQ, Modrm|EVexLIG|Masking=3D3|Space0F3=
A|VexVVVV|VexW1|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N=
o_ldSuf|SAE, { Imm8, RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
> +vrangep<sd>, 0x6650, None, CpuAVX512DQ, Modrm|Masking=3D3|Space0F3A|VexV=
VVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N=
o_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|<sd:elem>|Unspeci=
fied|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> +vranges<sd>, 0x6651, None, CpuAVX512DQ, Modrm|EVexLIG|Masking=3D3|Space0=
F3A|VexVVVV|<sd:vexw>|Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf=
|No_ldSuf|SAE, { Imm8, RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegX=
MM }
>
> -vrangess, 0x6651, None, CpuAVX512DQ, Modrm|EVexLIG|Masking=3D3|Space0F3A=
|VexVVVV|VexW0|Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No=
_ldSuf|SAE, { Imm8, RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
> -vreducess, 0x6657, None, CpuAVX512DQ, Modrm|EVexLIG|Masking=3D3|Space0F3=
A|VexVVVV|VexW0|Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N=
o_ldSuf|SAE, { Imm8, RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
> +vreducep<sdh>, 0x<sdh:pfx>56, None, <sdh:cpudq>, Modrm|Masking=3D3|Space=
0F3A|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf=
|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|<sdh:elem>|Unsp=
ecified|BaseIndex, RegXMM|RegYMM|RegZMM }
> +vreduces<sdh>, 0x<sdh:pfx>57, None, <sdh:cpudq>, Modrm|EVexLIG|Masking=
=3D3|Space0F3A|VexVVVV|<sdh:vexw>|Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_=
sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM|<sdh:elem>|Unspecified|BaseIndex,=
 RegXMM, RegXMM }
>
>  // AVX512DQ instructions end.
>
> @@ -3531,9 +3348,6 @@ hreset, 0xf30f3af0c0, None, CpuHRESET, N
>
>  // FP16 (HFNI) instructions.
>
> -vaddph, 0x58, None, CpuAVX512_FP16, Modrm|VexVVVV|Masking=3D3|EVexMap5|V=
exW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No=
_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|=
BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> -vaddsh, 0xf358, None, CpuAVX512_FP16, Modrm|EVexLIG|VexVVVV|Masking=3D3|=
EVexMap5|VexW0|Disp8MemShift=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No=
_ldSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, Reg=
XMM }
> -
>  vfcmaddcph, 0xf256, None, CpuAVX512_FP16, Modrm|VexVVVV|Masking=3D3|EVex=
Map6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|DistinctDest|No_bSuf|No_wSuf=
|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZM=
M|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
>  vfcmaddcsh, 0xf257, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3D3|EVex=
Map6|VexVVVV|VexW0|Disp8MemShift=3D2|DistinctDest|No_bSuf|No_wSuf|No_lSuf|N=
o_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|Base=
Index, RegXMM, RegXMM }
>
> @@ -3552,9 +3366,6 @@ vcmpph, 0xc2, None, CpuAVX512_FP16, Modr
>  vcmp<avx_frel>sh, 0xf3c2, 0x<avx_frel:imm>, CpuAVX512_FP16, Modrm|EVexLI=
G|Masking=3D2|Space0F3A|VexVVVV|VexW0|Disp8MemShift=3D1|No_bSuf|No_wSuf|No_=
lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, { RegXMM|Word|Unspecified|BaseInd=
ex, RegXMM, RegMask }
>  vcmpsh, 0xf3c2, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3D2|Space0F3=
A|VexVVVV|VexW0|Disp8MemShift=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N=
o_ldSuf|SAE, { Imm8, RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegMask }
>
> -vcomish, 0x2f, None, CpuAVX512_FP16, Modrm|EVexLIG|EVexMap5|VexW0|Disp8M=
emShift=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegXMM|=
Word|Unspecified|BaseIndex, RegXMM }
> -vucomish, 0x2e, None, CpuAVX512_FP16, Modrm|EVexLIG|EVexMap5|VexW0|Disp8=
MemShift=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegXMM=
|Word|Unspecified|BaseIndex, RegXMM }
> -
>  vcvtdq2ph, 0x5b, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3D3|EVexMap=
5|VexW0|Broadcast|Disp8MemShift=3D6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf=
|No_ldSuf|StaticRounding|SAE, { RegZMM|Dword|Unspecified|BaseIndex, RegYMM =
}
>  vcvtdq2ph, 0x5b, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|Masking=3D3|EVe=
xMap5|VexW0|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|=
No_ldSuf|IntelSyntax, { RegXMM|RegYMM|Dword|Unspecified|BaseIndex, RegXMM }
>  vcvtdq2ph, 0x5b, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|Masking=3D3|EVe=
xMap5|VexW0|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|=
No_ldSuf|ATTSyntax, { RegXMM|RegYMM|Dword|BaseIndex, RegXMM }
> @@ -3658,53 +3469,14 @@ vcvttph2uw, 0x7c, None, CpuAVX512_FP16,
>  vcvttsh2si, 0xf32c, None, CpuAVX512_FP16, Modrm|EVexLIG|EVexMap5|Disp8Me=
mShift=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ToQword|SAE, { =
RegXMM|Word|Unspecified|BaseIndex, Reg32|Reg64 }
>  vcvttsh2usi, 0xf378, None, CpuAVX512_FP16, Modrm|EVexLIG|EVexMap5|Disp8M=
emShift=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ToQword|SAE, {=
 RegXMM|Word|Unspecified|BaseIndex, Reg32|Reg64 }
>
> -vdivph, 0x5e, None, CpuAVX512_FP16, Modrm|VexVVVV|Masking=3D3|EVexMap5|V=
exW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No=
_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|=
BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> -vdivsh, 0xf35e, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3D3|EVexMap5=
|VexVVVV|VexW0|Disp8MemShift=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No=
_ldSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, Reg=
XMM }
> -
> -vfmadd<fma>ph, 0x6688 | 0x<fma:opc>, None, CpuAVX512_FP16, Modrm|VexVVVV=
|Masking=3D3|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_=
wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|R=
egZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZM=
M }
> -vfmadd<fma>sh, 0x6689 | 0x<fma:opc>, None, CpuAVX512_FP16, Modrm|EVexLIG=
|VexVVVV|Masking=3D3|EVexMap6|VexW0|Disp8MemShift=3D1|No_bSuf|No_wSuf|No_lS=
uf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|B=
aseIndex, RegXMM, RegXMM }
> -vfmaddsub<fma>ph, 0x6686 | 0x<fma:opc>, None, CpuAVX512_FP16, Modrm|VexV=
VVV|Masking=3D3|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|=
No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYM=
M|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|Re=
gZMM }
> -vfmsub<fma>ph, 0x668a | 0x<fma:opc>, None, CpuAVX512_FP16, Modrm|VexVVVV=
|Masking=3D3|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_=
wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|R=
egZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZM=
M }
> -vfmsub<fma>sh, 0x668b | 0x<fma:opc>, None, CpuAVX512_FP16, Modrm|EVexLIG=
|VexVVVV|Masking=3D3|EVexMap6|VexW0|Disp8MemShift=3D1|No_bSuf|No_wSuf|No_lS=
uf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|B=
aseIndex, RegXMM, RegXMM }
> -vfmsubadd<fma>ph, 0x6687 | 0x<fma:opc>, None, CpuAVX512_FP16, Modrm|VexV=
VVV|Masking=3D3|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|=
No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYM=
M|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|Re=
gZMM }
> -vfnmadd<fma>ph, 0x668c | 0x<fma:opc>, None, CpuAVX512_FP16, Modrm|VexVVV=
V|Masking=3D3|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No=
_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|=
RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZ=
MM }
> -vfnmadd<fma>sh, 0x668d | 0x<fma:opc>, None, CpuAVX512_FP16, Modrm|EVexLI=
G|VexVVVV|Masking=3D3|EVexMap6|VexW0|Disp8MemShift=3D1|No_bSuf|No_wSuf|No_l=
Suf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|=
BaseIndex, RegXMM, RegXMM }
> -vfnmsub<fma>ph, 0x668e | 0x<fma:opc>, None, CpuAVX512_FP16, Modrm|VexVVV=
V|Masking=3D3|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No=
_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|=
RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZ=
MM }
> -vfnmsub<fma>sh, 0x668f | 0x<fma:opc>, None, CpuAVX512_FP16, Modrm|EVexLI=
G|VexVVVV|Masking=3D3|EVexMap6|VexW0|Disp8MemShift=3D1|No_bSuf|No_wSuf|No_l=
Suf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|=
BaseIndex, RegXMM, RegXMM }
> -
>  vfpclassph, 0x66, None, CpuAVX512_FP16, Modrm|Masking=3D2|Space0F3A|VexW=
0|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, =
{ Imm8, RegXMM|RegYMM|RegZMM|Word|BaseIndex, RegMask }
>  vfpclassphz, 0x66, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3D2|Space=
0F3A|VexW0|Broadcast|Disp8MemShift=3D6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_q=
Suf|No_ldSuf|ATTSyntax, { Imm8, RegZMM|Word|Unspecified|BaseIndex, RegMask =
}
>  vfpclassphx, 0x66, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Maski=
ng=3D2|Space0F3A|VexW0|Broadcast|Disp8MemShift=3D4|No_bSuf|No_wSuf|No_lSuf|=
No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Imm8, RegXMM|Word|Unspecified|BaseInd=
ex, RegMask }
>  vfpclassphy, 0x66, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Maski=
ng=3D2|Space0F3A|VexW0|Broadcast|Disp8MemShift=3D5|No_bSuf|No_wSuf|No_lSuf|=
No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Imm8, RegYMM|Word|Unspecified|BaseInd=
ex, RegMask }
> -vfpclasssh, 0x67, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3D2|Space0=
F3A|VexW0|Disp8MemShift=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSu=
f, { Imm8, RegXMM|Word|Unspecified|BaseIndex, RegMask }
> -
> -vgetmantph, 0x26, None, CpuAVX512_FP16, Modrm|Masking=3D3|Space0F3A|VexW=
0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS=
uf|No_ldSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, R=
egXMM|RegYMM|RegZMM }
> -vgetmantsh, 0x27, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3D3|Space0=
F3A|VexVVVV|VexW0|Disp8MemShift=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf=
|No_ldSuf|SAE, { Imm8, RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM }
> -
> -vmaxph, 0x5f, None, CpuAVX512_FP16, Modrm|VexVVVV|Masking=3D3|EVexMap5|V=
exW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No=
_qSuf|No_ldSuf|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegX=
MM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> -vmaxsh, 0xf35f, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3D3|EVexMap5=
|VexVVVV|VexW0|Disp8MemShift=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No=
_ldSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM }
> -
> -vminph, 0x5d, None, CpuAVX512_FP16, Modrm|VexVVVV|Masking=3D3|EVexMap5|V=
exW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No=
_qSuf|No_ldSuf|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegX=
MM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> -vminsh, 0xf35d, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3D3|EVexMap5=
|VexVVVV|VexW0|Disp8MemShift=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No=
_ldSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM }
> -
> -vmovsh, 0xf310, None, CpuAVX512_FP16, D|Modrm|EVexLIG|MaskingMorZ|EVexMa=
p5|VexW0|Disp8MemShift=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf=
, { Word|Unspecified|BaseIndex, RegXMM }
> -vmovsh, 0xf310, None, CpuAVX512_FP16, D|Modrm|EVexLIG|Masking=3D3|EVexMa=
p5|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM=
, RegXMM, RegXMM }
>
>  vmovw, 0x666e, None, CpuAVX512_FP16, D|Modrm|EVex128|VexWIG|EVexMap5|Dis=
p8MemShift=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Uns=
pecified|BaseIndex, RegXMM }
>  vmovw, 0x667e, None, CpuAVX512_FP16, D|RegMem|EVex128|VexWIG|EVexMap5|No=
_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Reg32 }
>
> -vgetexpph, 0x6642, None, CpuAVX512_FP16, Modrm|Masking=3D3|EVexMap6|VexW=
0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS=
uf|No_ldSuf|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|=
RegYMM|RegZMM }
> -vgetexpsh, 0x6643, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3D3|EVexM=
ap6|VexVVVV|VexW0|Disp8MemShift=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf=
|No_ldSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM }
> -
> -vmulph, 0x59, None, CpuAVX512_FP16, Modrm|VexVVVV|Masking=3D3|EVexMap5|V=
exW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No=
_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|=
BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> -vmulsh, 0xf359, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3D3|EVexMap5=
|VexVVVV|VexW0|Disp8MemShift=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No=
_ldSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, Reg=
XMM }
> -
> -vreduceph, 0x56, None, CpuAVX512_FP16, Modrm|Masking=3D3|Space0F3A|VexW0=
|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu=
f|No_ldSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, Re=
gXMM|RegYMM|RegZMM }
> -vreducesh, 0x57, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3D3|Space0F=
3A|VexVVVV|VexW0|Disp8MemShift=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|=
No_ldSuf|SAE, { Imm8, RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM }
> -
> -vrndscaleph, 0x08, None, CpuAVX512_FP16, Modrm|Masking=3D3|Space0F3A|Vex=
W0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_q=
Suf|No_ldSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, =
RegXMM|RegYMM|RegZMM }
> -vrndscalesh, 0x0a, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3D3|Space=
0F3A|VexVVVV|VexW0|Disp8MemShift=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu=
f|No_ldSuf|SAE, { Imm8, RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM }
> -
>  vrcpph, 0x664c, None, CpuAVX512_FP16, Modrm|Masking=3D3|EVexMap6|VexW0|B=
roadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|=
No_ldSuf, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|=
RegZMM }
>
>  vrcpsh, 0x664d, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3D3|EVexMap6=
|VexVVVV|VexW0|Disp8MemShift=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No=
_ldSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM }
> @@ -3713,13 +3485,4 @@ vrsqrtph, 0x664e, None, CpuAVX512_FP16,
>
>  vrsqrtsh, 0x664f, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3D3|EVexMa=
p6|VexVVVV|VexW0|Disp8MemShift=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|=
No_ldSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM }
>
> -vscalefph, 0x662c, None, CpuAVX512_FP16, Modrm|VexVVVV|Masking=3D3|EVexM=
ap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS=
uf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspeci=
fied|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> -vscalefsh, 0x662d, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3D3|EVexM=
ap6|VexVVVV|VexW0|Disp8MemShift=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf=
|No_ldSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, =
RegXMM }
> -
> -vsqrtph, 0x51, None, CpuAVX512_FP16, Modrm|Masking=3D3|EVexMap5|VexW0|Br=
oadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N=
o_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseInd=
ex, RegXMM|RegYMM|RegZMM }
> -vsqrtsh, 0xf351, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3D3|EVexMap=
5|VexVVVV|VexW0|Disp8MemShift=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N=
o_ldSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, Re=
gXMM }
> -
> -vsubph, 0x5c, None, CpuAVX512_FP16, Modrm|VexVVVV|Masking=3D3|EVexMap5|V=
exW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No=
_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|=
BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> -vsubsh, 0xf35c, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3D3|EVexMap5=
|VexVVVV|VexW0|Disp8MemShift=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No=
_ldSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, Reg=
XMM }
> -
>  // FP16 (HFNI) instructions end.
>

Lili, Hongchen, do you have any comments?  Will this make future changes
difficult?

--=20
H.J.