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From: "H.J. Lu" <hjl.tools@gmail.com>
Date: Thu, 11 Aug 2022 10:38:09 -0700
Message-ID: <CAMe9rOoM_vpxyscznNLwNaJgpgxFQ2LSUKVvVeXSwW660heNSQ@mail.gmail.com>
Subject: Re: [PATCH 10/12] x86: template-ize vector packed byte/word integer
 insns
To: Jan Beulich <jbeulich@suse.com>
Cc: Binutils <binutils@sourceware.org>
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On Fri, Aug 5, 2022 at 5:27 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> Many of the vector integer insns come in byte/word element pairs. Most
> of these pairs follow certain encoding patterns. Introduce a "bw"
> template to reduce redundancy.
>
> Note that in the course of the conversion
> - the AVX VPEXTRW template which is not being touched needs to remain
>   ahead of the new "combined" ones, as (a) this should be tried first
>   when matching insns against templates and (b) its Load attributes
>   requires it to be first,
> - this add a benign/meaningless IgnoreSize attribute to the memory form
>   of PEXTRB; it didn't seem worth avoiding this.
> ---
> For VPCOMPRESS{B,W} and VPEXPAND{B,W} the conversion could only be done
> if we allowed Byte/Word on the memory operands. Imo permitting this
> makes sense anyway (as the memory operands aren't full [XYZ]mmword
> ones), but such a functional change should probably be a separate patch.
>
> It might even be worth having a separate bwd template, but the (further)
> gains there won't be as high.
>
> --- a/opcodes/i386-opc.tbl
> +++ b/opcodes/i386-opc.tbl
> @@ -971,6 +971,10 @@ pause, 0xf390, None, Cpu186, No_bSuf|No_
>      $avx:CpuAVX:Vex128|VexW0|SSE2AVX:VexLIG|VexW0|SSE2AVX:VexVVVV:Vex128=
|VexVVVV=3D2|VexW0|SSE2AVX, +
>      $sse:CpuSSE2::NoRex64::>
>
> +<bw:opc:vexw:elem:kcpu:kpfx:cpubmi, +
> +    b:0:VexW0:Byte:CpuAVX512DQ:66:CpuAVX512VBMI, +
> +    w:1:VexW1:Word:CpuAVX512F::CpuAVX512BW>
> +
>  <dq:opc:vexw:vexw64:elem:cpu64:gpr:kpfx, +
>      d:0:VexW0:IgnoreSize:Dword::Reg32:66, +
>      q:1:VexW1:VexW1:Qword:Cpu64:Reg64:>
> @@ -997,22 +1001,17 @@ movq, 0xf6e, None, CpuMMX|Cpu64, D|Modrm
>  packssdw<mmx>, 0x<mmx:pfx>0f6b, None, <mmx:cpu>, Modrm|<mmx:attr>|No_bSu=
f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <mmx:reg>|<mmx:mem>|Unspecifi=
ed|BaseIndex, <mmx:reg> }
>  packsswb<mmx>, 0x<mmx:pfx>0f63, None, <mmx:cpu>, Modrm|<mmx:attr>|No_bSu=
f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <mmx:reg>|<mmx:mem>|Unspecifi=
ed|BaseIndex, <mmx:reg> }
>  packuswb<mmx>, 0x<mmx:pfx>0f67, None, <mmx:cpu>, Modrm|<mmx:attr>|No_bSu=
f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <mmx:reg>|<mmx:mem>|Unspecifi=
ed|BaseIndex, <mmx:reg> }
> -paddb<mmx>, 0x<mmx:pfx>0ffc, None, <mmx:cpu>, Modrm|<mmx:attr>|C|No_bSuf=
|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <mmx:reg>|<mmx:mem>|Unspecifie=
d|BaseIndex, <mmx:reg> }
> -paddw<mmx>, 0x<mmx:pfx>0ffd, None, <mmx:cpu>, Modrm|<mmx:attr>|C|No_bSuf=
|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <mmx:reg>|<mmx:mem>|Unspecifie=
d|BaseIndex, <mmx:reg> }
> +padd<bw><mmx>, 0x<mmx:pfx>0ffc | <bw:opc>, None, <mmx:cpu>, Modrm|<mmx:a=
ttr>|C|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <mmx:reg>|<mmx:m=
em>|Unspecified|BaseIndex, <mmx:reg> }
>  paddd<mmx>, 0x<mmx:pfx>0ffe, None, <mmx:cpu>, Modrm|<mmx:attr>|C|No_bSuf=
|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <mmx:reg>|<mmx:mem>|Unspecifie=
d|BaseIndex, <mmx:reg> }
>  paddq<sse2>, 0x660fd4, None, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|C=
|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|Bas=
eIndex, RegXMM }
>  paddq, 0xfd4, None, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS=
uf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
> -paddsb<mmx>, 0x<mmx:pfx>0fec, None, <mmx:cpu>, Modrm|<mmx:attr>|C|No_bSu=
f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <mmx:reg>|<mmx:mem>|Unspecifi=
ed|BaseIndex, <mmx:reg> }
> -paddsw<mmx>, 0x<mmx:pfx>0fed, None, <mmx:cpu>, Modrm|<mmx:attr>|C|No_bSu=
f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <mmx:reg>|<mmx:mem>|Unspecifi=
ed|BaseIndex, <mmx:reg> }
> -paddusb<mmx>, 0x<mmx:pfx>0fdc, None, <mmx:cpu>, Modrm|<mmx:attr>|C|No_bS=
uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <mmx:reg>|<mmx:mem>|Unspecif=
ied|BaseIndex, <mmx:reg> }
> -paddusw<mmx>, 0x<mmx:pfx>0fdd, None, <mmx:cpu>, Modrm|<mmx:attr>|C|No_bS=
uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <mmx:reg>|<mmx:mem>|Unspecif=
ied|BaseIndex, <mmx:reg> }
> +padds<bw><mmx>, 0x<mmx:pfx>0fec | <bw:opc>, None, <mmx:cpu>, Modrm|<mmx:=
attr>|C|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <mmx:reg>|<mmx:=
mem>|Unspecified|BaseIndex, <mmx:reg> }
> +paddus<bw><mmx>, 0x<mmx:pfx>0fdc | <bw:opc>, None, <mmx:cpu>, Modrm|<mmx=
:attr>|C|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <mmx:reg>|<mmx=
:mem>|Unspecified|BaseIndex, <mmx:reg> }
>  pand<mmx>, 0x<mmx:pfx>0fdb, None, <mmx:cpu>, Modrm|<mmx:attr>|C|No_bSuf|=
No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <mmx:reg>|<mmx:mem>|Unspecified=
|BaseIndex, <mmx:reg> }
>  pandn<mmx>, 0x<mmx:pfx>0fdf, None, <mmx:cpu>, Modrm|<mmx:attr>|No_bSuf|N=
o_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <mmx:reg>|<mmx:mem>|Unspecified|=
BaseIndex, <mmx:reg> }
> -pcmpeqb<mmx>, 0x<mmx:pfx>0f74, None, <mmx:cpu>, Modrm|<mmx:attr>|C|No_bS=
uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <mmx:reg>|<mmx:mem>|Unspecif=
ied|BaseIndex, <mmx:reg> }
> -pcmpeqw<mmx>, 0x<mmx:pfx>0f75, None, <mmx:cpu>, Modrm|<mmx:attr>|C|No_bS=
uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <mmx:reg>|<mmx:mem>|Unspecif=
ied|BaseIndex, <mmx:reg> }
> +pcmpeq<bw><mmx>, 0x<mmx:pfx>0f74 | <bw:opc>, None, <mmx:cpu>, Modrm|<mmx=
:attr>|C|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <mmx:reg>|<mmx=
:mem>|Unspecified|BaseIndex, <mmx:reg> }
>  pcmpeqd<mmx>, 0x<mmx:pfx>0f76, None, <mmx:cpu>, Modrm|<mmx:attr>|C|No_bS=
uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <mmx:reg>|<mmx:mem>|Unspecif=
ied|BaseIndex, <mmx:reg> }
> -pcmpgtb<mmx>, 0x<mmx:pfx>0f64, None, <mmx:cpu>, Modrm|<mmx:attr>|No_bSuf=
|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <mmx:reg>|<mmx:mem>|Unspecifie=
d|BaseIndex, <mmx:reg> }
> -pcmpgtw<mmx>, 0x<mmx:pfx>0f65, None, <mmx:cpu>, Modrm|<mmx:attr>|No_bSuf=
|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <mmx:reg>|<mmx:mem>|Unspecifie=
d|BaseIndex, <mmx:reg> }
> +pcmpgt<bw><mmx>, 0x<mmx:pfx>0f64 | <bw:opc>, None, <mmx:cpu>, Modrm|<mmx=
:attr>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <mmx:reg>|<mmx:m=
em>|Unspecified|BaseIndex, <mmx:reg> }
>  pcmpgtd<mmx>, 0x<mmx:pfx>0f66, None, <mmx:cpu>, Modrm|<mmx:attr>|No_bSuf=
|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <mmx:reg>|<mmx:mem>|Unspecifie=
d|BaseIndex, <mmx:reg> }
>  pmaddwd<mmx>, 0x<mmx:pfx>0ff5, None, <mmx:cpu>, Modrm|<mmx:attr>|C|No_bS=
uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <mmx:reg>|<mmx:mem>|Unspecif=
ied|BaseIndex, <mmx:reg> }
>  pmulhw<mmx>, 0x<mmx:pfx>0fe5, None, <mmx:cpu>, Modrm|<mmx:attr>|C|No_bSu=
f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <mmx:reg>|<mmx:mem>|Unspecifi=
ed|BaseIndex, <mmx:reg> }
> @@ -1030,15 +1029,12 @@ psrlw<mmx>, 0x<mmx:pfx>0fd1, None, <mmx:
>  psrlw<mmx>, 0x<mmx:pfx>0f71, 2, <mmx:cpu>, Modrm|<mmx:shimm>|No_bSuf|No_=
wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, <mmx:reg> }
>  psrl<dq><mmx>, 0x<mmx:pfx>0fd2 | <dq:opc>, None, <mmx:cpu>, Modrm|<mmx:a=
ttr>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <mmx:reg>|<mmx:mem=
>|Unspecified|BaseIndex, <mmx:reg> }
>  psrl<dq><mmx>, 0x<mmx:pfx>0f72 | <dq:opc>, 2, <mmx:cpu>, Modrm|<mmx:shim=
m>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, <mmx:reg> }
> -psubb<mmx>, 0x<mmx:pfx>0ff8, None, <mmx:cpu>, Modrm|<mmx:attr>|No_bSuf|N=
o_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <mmx:reg>|<mmx:mem>|Unspecified|=
BaseIndex, <mmx:reg> }
> -psubw<mmx>, 0x<mmx:pfx>0ff9, None, <mmx:cpu>, Modrm|<mmx:attr>|No_bSuf|N=
o_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <mmx:reg>|<mmx:mem>|Unspecified|=
BaseIndex, <mmx:reg> }
> +psub<bw><mmx>, 0x<mmx:pfx>0ff8 | <bw:opc>, None, <mmx:cpu>, Modrm|<mmx:a=
ttr>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <mmx:reg>|<mmx:mem=
>|Unspecified|BaseIndex, <mmx:reg> }
>  psubd<mmx>, 0x<mmx:pfx>0ffa, None, <mmx:cpu>, Modrm|<mmx:attr>|No_bSuf|N=
o_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <mmx:reg>|<mmx:mem>|Unspecified|=
BaseIndex, <mmx:reg> }
>  psubq<sse2>, 0x660ffb, None, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|N=
o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseI=
ndex, RegXMM }
>  psubq, 0xffb, None, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS=
uf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
> -psubsb<mmx>, 0x<mmx:pfx>0fe8, None, <mmx:cpu>, Modrm|<mmx:attr>|No_bSuf|=
No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <mmx:reg>|<mmx:mem>|Unspecified=
|BaseIndex, <mmx:reg> }
> -psubsw<mmx>, 0x<mmx:pfx>0fe9, None, <mmx:cpu>, Modrm|<mmx:attr>|No_bSuf|=
No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <mmx:reg>|<mmx:mem>|Unspecified=
|BaseIndex, <mmx:reg> }
> -psubusb<mmx>, 0x<mmx:pfx>0fd8, None, <mmx:cpu>, Modrm|<mmx:attr>|No_bSuf=
|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <mmx:reg>|<mmx:mem>|Unspecifie=
d|BaseIndex, <mmx:reg> }
> -psubusw<mmx>, 0x<mmx:pfx>0fd9, None, <mmx:cpu>, Modrm|<mmx:attr>|No_bSuf=
|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <mmx:reg>|<mmx:mem>|Unspecifie=
d|BaseIndex, <mmx:reg> }
> +psubs<bw><mmx>, 0x<mmx:pfx>0fe8 | <bw:opc>, None, <mmx:cpu>, Modrm|<mmx:=
attr>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <mmx:reg>|<mmx:me=
m>|Unspecified|BaseIndex, <mmx:reg> }
> +psubus<bw><mmx>, 0x<mmx:pfx>0fd8 | <bw:opc>, None, <mmx:cpu>, Modrm|<mmx=
:attr>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <mmx:reg>|<mmx:m=
em>|Unspecified|BaseIndex, <mmx:reg> }
>  punpckhbw<mmx>, 0x<mmx:pfx>0f68, None, <mmx:cpu>, Modrm|<mmx:attr>|No_bS=
uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <mmx:reg>|<mmx:mem>|Unspecif=
ied|BaseIndex, <mmx:reg> }
>  punpckhwd<mmx>, 0x<mmx:pfx>0f69, None, <mmx:cpu>, Modrm|<mmx:attr>|No_bS=
uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <mmx:reg>|<mmx:mem>|Unspecif=
ied|BaseIndex, <mmx:reg> }
>  punpckhdq<mmx>, 0x<mmx:pfx>0f6a, None, <mmx:cpu>, Modrm|<mmx:attr>|No_bS=
uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <mmx:reg>|<mmx:mem>|Unspecif=
ied|BaseIndex, <mmx:reg> }
> @@ -1106,10 +1102,8 @@ movups<sse>, 0x0f10, None, <sse:cpu>, D|
>  mulps<sse>, 0x0f59, None, <sse:cpu>, Modrm|<sse:attr>|<sse:vvvv>|No_bSuf=
|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, =
RegXMM }
>  mulss<sse>, 0xf30f59, None, <sse:cpu>, Modrm|<sse:scal>|<sse:vvvv>|No_bS=
uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|=
RegXMM, RegXMM }
>  orps<sse>, 0x0f56, None, <sse:cpu>, Modrm|<sse:attr>|<sse:vvvv>|C|No_bSu=
f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex,=
 RegXMM }
> -pavgb, 0xfe0, None, CpuSSE|Cpu3dnowA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_s=
Suf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX =
}
> -pavgb<sse2>, 0x660fe0, None, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|C=
|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|Bas=
eIndex, RegXMM }
> -pavgw, 0xfe3, None, CpuSSE|Cpu3dnowA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_s=
Suf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX =
}
> -pavgw<sse2>, 0x660fe3, None, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|C=
|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|Bas=
eIndex, RegXMM }
> +pavg<bw>, 0xfe0 | (3 * <bw:opc>), None, CpuSSE|Cpu3dnowA, Modrm|No_bSuf|=
No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseI=
ndex|RegMMX, RegMMX }
> +pavg<bw><sse2>, 0x660fe0 | (3 * <bw:opc>), None, <sse2:cpu>, Modrm|<sse2=
:attr>|<sse2:vvvv>|C|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Re=
gXMM|Unspecified|BaseIndex, RegXMM }
>  pextrw<sse2>, 0x660fc5, None, <sse2:cpu>, Load|Modrm|<sse2:attr>|No_bSuf=
|No_wSuf|No_sSuf|No_ldSuf|IgnoreSize|NoRex64, { Imm8, RegXMM, Reg32|Reg64 }
>  pextrw, 0xfc5, None, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|=
No_sSuf|No_ldSuf|NoRex64, { Imm8, RegMMX, Reg32|Reg64 }
>  pinsrw<sse2>, 0x660fc4, None, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|=
No_bSuf|No_wSuf|No_sSuf|No_ldSuf|IgnoreSize|NoRex64, { Imm8, Reg32|Reg64, R=
egXMM }
> @@ -1323,12 +1317,10 @@ phsubsw<ssse3>, 0x<ssse3:pfx>0f3807, Non
>  pmaddubsw<ssse3>, 0x<ssse3:pfx>0f3804, None, <ssse3:cpu>, Modrm|<ssse3:a=
ttr>|<ssse3:vvvv>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <ssse=
3:reg>|<ssse3:mem>|Unspecified|BaseIndex, <ssse3:reg> }
>  pmulhrsw<ssse3>, 0x<ssse3:pfx>0f380b, None, <ssse3:cpu>, Modrm|<ssse3:at=
tr>|<ssse3:vvvv>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <ssse3=
:reg>|<ssse3:mem>|Unspecified|BaseIndex, <ssse3:reg> }
>  pshufb<ssse3>, 0x<ssse3:pfx>0f3800, None, <ssse3:cpu>, Modrm|<ssse3:attr=
>|<ssse3:vvvv>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <ssse3:r=
eg>|<ssse3:mem>|Unspecified|BaseIndex, <ssse3:reg> }
> -psignb<ssse3>, 0x<ssse3:pfx>0f3808, None, <ssse3:cpu>, Modrm|<ssse3:attr=
>|<ssse3:vvvv>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <ssse3:r=
eg>|<ssse3:mem>|Unspecified|BaseIndex, <ssse3:reg> }
> -psignw<ssse3>, 0x<ssse3:pfx>0f3809, None, <ssse3:cpu>, Modrm|<ssse3:attr=
>|<ssse3:vvvv>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <ssse3:r=
eg>|<ssse3:mem>|Unspecified|BaseIndex, <ssse3:reg> }
> +psign<bw><ssse3>, 0x<ssse3:pfx>0f3808 | <bw:opc>, None, <ssse3:cpu>, Mod=
rm|<ssse3:attr>|<ssse3:vvvv>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS=
uf, { <ssse3:reg>|<ssse3:mem>|Unspecified|BaseIndex, <ssse3:reg> }
>  psignd<ssse3>, 0x<ssse3:pfx>0f380a, None, <ssse3:cpu>, Modrm|<ssse3:attr=
>|<ssse3:vvvv>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <ssse3:r=
eg>|<ssse3:mem>|Unspecified|BaseIndex, <ssse3:reg> }
>  palignr<ssse3>, 0x<ssse3:pfx>0f3a0f, None, <ssse3:cpu>, Modrm|<ssse3:att=
r>|<ssse3:vvvv>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, <=
ssse3:reg>|<ssse3:mem>|Unspecified|BaseIndex, <ssse3:reg> }
> -pabsb<ssse3>, 0x<ssse3:pfx>0f381c, None, <ssse3:cpu>, Modrm|<ssse3:attr>=
|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <ssse3:reg>|<ssse3:mem=
>|Unspecified|BaseIndex, <ssse3:reg> }
> -pabsw<ssse3>, 0x<ssse3:pfx>0f381d, None, <ssse3:cpu>, Modrm|<ssse3:attr>=
|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <ssse3:reg>|<ssse3:mem=
>|Unspecified|BaseIndex, <ssse3:reg> }
> +pabs<bw><ssse3>, 0x<ssse3:pfx>0f381c | <bw:opc>, None, <ssse3:cpu>, Modr=
m|<ssse3:attr>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <ssse3:r=
eg>|<ssse3:mem>|Unspecified|BaseIndex, <ssse3:reg> }
>  pabsd<ssse3>, 0x<ssse3:pfx>0f381e, None, <ssse3:cpu>, Modrm|<ssse3:attr>=
|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <ssse3:reg>|<ssse3:mem=
>|Unspecified|BaseIndex, <ssse3:reg> }
>
>  // SSE4.1 instructions.
> @@ -1356,10 +1348,8 @@ pblendvb, 0x660f3810, None, CpuSSE4_1, M
>  pblendvb, 0x660f3810, None, CpuSSE4_1, Modrm|No_bSuf|No_wSuf|No_lSuf|No_=
sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
>  pblendw<sse41>, 0x660f3a0e, None, <sse41:cpu>, Modrm|<sse41:attr>|<sse41=
:vvvv>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Uns=
pecified|BaseIndex, RegXMM }
>  pcmpeqq<sse41>, 0x660f3829, None, <sse41:cpu>, Modrm|<sse41:attr>|<sse41=
:vvvv>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecifi=
ed|BaseIndex, RegXMM }
> -pextrb<sse41>, 0x660f3a14, None, <sse41:cpu>, RegMem|<sse41:attr>|No_bSu=
f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IgnoreSize|NoRex64, { Imm8, RegX=
MM, Reg32|Reg64 }
> -pextrb<sse41>, 0x660f3a14, None, <sse41:cpu>, Modrm|<sse41:attr>|No_bSuf=
|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Byte|Unspecified=
|BaseIndex }
> -pextrw<sse41>, 0x660f3a15, None, <sse41:cpu>, RegMem|<sse41:attr>|No_bSu=
f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IgnoreSize|NoRex64, { Imm8, RegX=
MM, Reg32|Reg64 }
> -pextrw<sse41>, 0x660f3a15, None, <sse41:cpu>, Modrm|<sse41:attr>|No_bSuf=
|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IgnoreSize, { Imm8, RegXMM, Word|=
Unspecified|BaseIndex }
> +pextr<bw><sse41>, 0x660f3a14 | <bw:opc>, None, <sse41:cpu>, RegMem|<sse4=
1:attr>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IgnoreSize|NoRex64=
, { Imm8, RegXMM, Reg32|Reg64 }
> +pextr<bw><sse41>, 0x660f3a14 | <bw:opc>, None, <sse41:cpu>, Modrm|<sse41=
:attr>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IgnoreSize, { Imm8,=
 RegXMM, <bw:elem>|Unspecified|BaseIndex }
>  pextrd<sse41>, 0x660f3a16, None, <sse41:cpu>, Modrm|<sse41:attr>|No_bSuf=
|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IgnoreSize, { Imm8, RegXMM, Reg32=
|Unspecified|BaseIndex }
>  pextrq, 0x6616, None, CpuAVX|Cpu64, Modrm|Vex|Space0F3A|VexW1|No_bSuf|No=
_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM, Reg64|Unspe=
cified|BaseIndex }
>  pextrq, 0x660f3a16, None, CpuSSE4_1|Cpu64, Modrm|Size64|No_bSuf|No_wSuf|=
No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg64|Unspecified|BaseInd=
ex }
> @@ -1571,51 +1561,42 @@ vmpsadbw, 0x6642, None, CpuAVX|CpuAVX2,
>  vmulp<sd>, 0x<sd:ppfx>59, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG=
|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecifi=
ed|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
>  vmuls<sd>, 0x<sd:spfx>59, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|Vex=
WIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <sd:elem>|Unspecifi=
ed|BaseIndex|RegXMM, RegXMM, RegXMM }
>  vorp<sd>, 0x<sd:ppfx>56, None, CpuAVX, Modrm|C|Vex|Space0F|VexVVVV|VexWI=
G|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecif=
ied|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vpabsb, 0x661c, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexWIG|CheckRe=
gSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseI=
ndex|RegXMM|RegYMM, RegXMM|RegYMM }
> +vpabs<bw>, 0x661c | <bw:opc>, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|=
VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Uns=
pecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
>  vpabsd, 0x661e, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexWIG|CheckRe=
gSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseI=
ndex|RegXMM|RegYMM, RegXMM|RegYMM }
> -vpabsw, 0x661d, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexWIG|CheckRe=
gSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseI=
ndex|RegXMM|RegYMM, RegXMM|RegYMM }
>  vpackssdw, 0x666b, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWI=
G|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecif=
ied|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
>  vpacksswb, 0x6663, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWI=
G|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecif=
ied|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
>  vpackusdw, 0x662b, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|Vex=
WIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspec=
ified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
>  vpackuswb, 0x6667, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWI=
G|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecif=
ied|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vpaddsb, 0x66ec, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWI=
G|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecif=
ied|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vpaddsw, 0x66ed, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWI=
G|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecif=
ied|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vpaddb, 0x66fc, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG=
|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecifi=
ed|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> +vpadds<bw>, 0x66ec | <bw:opc>, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F=
|VexVVVV|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS=
uf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> +vpadd<bw>, 0x66fc | <bw:opc>, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|=
VexVVVV|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSu=
f, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
>  vpaddd, 0x66fe, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG=
|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecifi=
ed|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
>  vpaddq, 0x66d4, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG=
|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecifi=
ed|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vpaddw, 0x66fd, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG=
|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecifi=
ed|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vpaddusb, 0x66dc, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexW=
IG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspeci=
fied|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vpaddusw, 0x66dd, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexW=
IG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspeci=
fied|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> +vpaddus<bw>, 0x66dc | <bw:opc>, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0=
F|VexVVVV|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ld=
Suf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
>  vpalignr, 0x660f, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F3A|VexVVVV|VexW=
IG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, U=
nspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
>  vpand, 0x66db, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|=
CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecifie=
d|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
>  vpandn, 0x66df, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|C=
heckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Un=
specified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vpavgb, 0x66e0, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG=
|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecifi=
ed|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vpavgw, 0x66e3, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG=
|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecifi=
ed|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> +vpavg<bw>, 0x66e0 | (3 * <bw:opc>), None, CpuAVX|CpuAVX2, Modrm|C|Vex|Sp=
ace0F|VexVVVV|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N=
o_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYM=
M }
>  vpblendvb, 0x664c, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F3A|VexVVVV|Vex=
WIG|CheckRegSize|VexSources=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_=
ldSuf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM,=
 RegXMM|RegYMM }
>  vpblendw, 0x660e, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F3A|VexVVVV|VexW=
IG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, U=
nspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vpcmpeqb, 0x6674, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexW=
IG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspeci=
fied|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> +vpcmpeq<bw>, 0x6674 | <bw:opc>, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0=
F|VexVVVV|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ld=
Suf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
>  vpcmpeqd, 0x6676, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexW=
IG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspeci=
fied|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
>  vpcmpeqq, 0x6629, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW=
IG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspeci=
fied|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vpcmpeqw, 0x6675, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexW=
IG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspeci=
fied|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
>  vpcmpestri, 0x6661, None, CpuAVX|CpuNo64, Modrm|Vex|Space0F3A|No_bSuf|No=
_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXM=
M, RegXMM }
>  vpcmpestri, 0x6661, None, CpuAVX|Cpu64, Modrm|Vex|Space0F3A|IgnoreSize|N=
o_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegX=
MM, RegXMM }
>  vpcmpestrm, 0x6660, None, CpuAVX|CpuNo64, Modrm|Vex|Space0F3A|No_bSuf|No=
_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXM=
M, RegXMM }
>  vpcmpestrm, 0x6660, None, CpuAVX|Cpu64, Modrm|Vex|Space0F3A|IgnoreSize|N=
o_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegX=
MM, RegXMM }
> -vpcmpgtb, 0x6664, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG=
|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecifi=
ed|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> +vpcmpgt<bw>, 0x6664 | <bw:opc>, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|=
VexVVVV|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSu=
f, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
>  vpcmpgtd, 0x6666, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG=
|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecifi=
ed|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
>  vpcmpgtq, 0x6637, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW=
IG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspeci=
fied|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vpcmpgtw, 0x6665, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG=
|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecifi=
ed|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
>  vpcmpistri, 0x6663, None, CpuAVX, Modrm|Vex|Space0F3A|VexWIG|No_bSuf|No_=
wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM=
, RegXMM }
>  vpcmpistrm, 0x6662, None, CpuAVX, Modrm|Vex|Space0F3A|VexWIG|No_bSuf|No_=
wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM=
, RegXMM }
>  vperm2f128, 0x6606, None, CpuAVX, Modrm|Vex=3D2|Space0F3A|VexVVVV=3D1|Ve=
xW=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecifie=
d|BaseIndex|RegYMM, RegYMM, RegYMM }
>  vpermilp<sd>, 0x660c | <sd:opc>, None, CpuAVX, Modrm|Vex|Space0F38|VexVV=
VV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { U=
nspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
>  vpermilp<sd>, 0x6604 | <sd:opc>, None, CpuAVX, Modrm|Vex|Space0F3A|VexW0=
|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Uns=
pecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
> -vpextrb, 0x6614, None, CpuAVX, RegMem|Vex|Space0F3A|VexWIG|No_bSuf|No_wS=
uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64 }
> -vpextrb, 0x6614, None, CpuAVX, Modrm|Vex|Space0F3A|VexWIG|No_bSuf|No_wSu=
f|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Byte|Unspecified|BaseIn=
dex }
>  vpextr<dq>, 0x6616, None, CpuAVX|<dq:cpu64>, Modrm|Vex|Space0F3A|<dq:vex=
w64>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, <dq:=
gpr>|Unspecified|BaseIndex }
>  vpextrw, 0x66c5, None, CpuAVX, Load|Modrm|Vex|Space0F|VexWIG|No_bSuf|No_=
wSuf|No_sSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64 }
> -vpextrw, 0x6615, None, CpuAVX, RegMem|Vex|Space0F3A|VexWIG|No_bSuf|No_wS=
uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64 }
> -vpextrw, 0x6615, None, CpuAVX, Modrm|Vex|Space0F3A|VexWIG|No_bSuf|No_wSu=
f|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Word|Unspecified|BaseIn=
dex }
> +vpextr<bw>, 0x6614 | <bw:opc>, None, CpuAVX, RegMem|Vex|Space0F3A|VexWIG=
|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Re=
g64 }
> +vpextr<bw>, 0x6614 | <bw:opc>, None, CpuAVX, Modrm|Vex|Space0F3A|VexWIG|=
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, <bw:elem>=
|Unspecified|BaseIndex }
>  vphaddd, 0x6602, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWI=
G|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecif=
ied|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
>  vphaddsw, 0x6603, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW=
IG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspeci=
fied|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
>  vphaddw, 0x6601, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWI=
G|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecif=
ied|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> @@ -1668,9 +1649,8 @@ vpshufb, 0x6600, None, CpuAVX|CpuAVX2, M
>  vpshufd, 0x6670, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexWIG|CheckReg=
Size|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|=
BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
>  vpshufhw, 0xf370, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexWIG|CheckRe=
gSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified=
|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
>  vpshuflw, 0xf270, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexWIG|CheckRe=
gSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified=
|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
> -vpsignb, 0x6608, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWI=
G|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecif=
ied|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> +vpsign<bw>, 0x6608 | <bw:opc>, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38=
|VexVVVV|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS=
uf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
>  vpsignd, 0x660a, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWI=
G|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecif=
ied|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vpsignw, 0x6609, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWI=
G|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecif=
ied|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
>  vpsll<dq>, 0x6672 | <dq:opc>, 6, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVV=
VV=3D2|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf=
, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM }
>  vpsll<dq>, 0x66f2 | <dq:opc>, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|Ve=
xVVVV|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,=
 { Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM }
>  vpslldq, 0x6673, 7, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=3D2|VexWIG=
|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg=
XMM|RegYMM, RegXMM|RegYMM }
> @@ -1685,13 +1665,10 @@ vpsrl<dq>, 0x66d2 | <dq:opc>, None, CpuA
>  vpsrldq, 0x6673, 3, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=3D2|VexWIG=
|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg=
XMM|RegYMM, RegXMM|RegYMM }
>  vpsrlw, 0x6671, 2, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=3D2|VexWIG|=
CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegX=
MM|RegYMM, RegXMM|RegYMM }
>  vpsrlw, 0x66d1, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|C=
heckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified=
|BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vpsubb, 0x66f8, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|C=
heckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Un=
specified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> +vpsub<bw>, 0x66f8 | <bw:opc>, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|Ve=
xVVVV|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|=
Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegY=
MM }
>  vpsub<dq>, 0x66fa | <dq:opc>, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|Ve=
xVVVV|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|=
Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegY=
MM }
> -vpsubsb, 0x66e8, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|=
CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecifie=
d|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vpsubsw, 0x66e9, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|=
CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecifie=
d|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vpsubusb, 0x66d8, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG=
|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecifi=
ed|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vpsubusw, 0x66d9, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG=
|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecifi=
ed|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vpsubw, 0x66f9, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|C=
heckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Un=
specified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> +vpsubs<bw>, 0x66e8 | <bw:opc>, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|V=
exVVVV|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf=
, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> +vpsubus<bw>, 0x66d8 | <bw:opc>, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|=
VexVVVV|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSu=
f, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
>  vptest, 0x6617, None, CpuAVX, Modrm|Vex|Space0F38|VexWIG|CheckRegSize|No=
_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|Reg=
XMM|RegYMM, RegXMM|RegYMM }
>  vpunpckhbw, 0x6668, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexW=
IG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspeci=
fied|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
>  vpunpckhdq, 0x666a, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexW=
IG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspeci=
fied|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> @@ -1743,9 +1720,8 @@ vbroadcasti128, 0x665A, None, CpuAVX2, M
>  vbroadcastsd, 0x6619, None, CpuAVX2, Modrm|Vex=3D2|Space0F38|VexW=3D1|No=
_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegYMM }
>  vbroadcastss, 0x6618, None, CpuAVX2, Modrm|Vex|Space0F38|VexW=3D1|No_bSu=
f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|RegYMM }
>  vpblendd, 0x6602, None, CpuAVX2, Modrm|Vex|Space0F3A|VexVVVV=3D1|VexW=3D=
1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Un=
specified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
> -vpbroadcastb, 0x6678, None, CpuAVX2, Modrm|Vex=3D1|Space0F38|VexW0|No_bS=
uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Byte|Unspecified|BaseIndex|R=
egXMM, RegXMM|RegYMM }
> +vpbroadcast<bw>, 0x6678 | <bw:opc>, None, CpuAVX2, Modrm|Vex|Space0F38|V=
exW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <bw:elem>|Unspecif=
ied|BaseIndex|RegXMM, RegXMM|RegYMM }
>  vpbroadcast<dq>, 0x6658 | <dq:opc>, None, CpuAVX2, Modrm|Vex|Space0F38|V=
exW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <dq:elem>|Unspecif=
ied|BaseIndex|RegXMM, RegXMM|RegYMM }
> -vpbroadcastw, 0x6679, None, CpuAVX2, Modrm|Vex=3D1|Space0F38|VexW0|No_bS=
uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex|R=
egXMM, RegXMM|RegYMM }
>  vperm2i128, 0x6646, None, CpuAVX2, Modrm|Vex=3D2|Space0F3A|VexVVVV=3D1|V=
exW=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecifi=
ed|BaseIndex|RegYMM, RegYMM, RegYMM }
>  vpermd, 0x6636, None, CpuAVX2, Modrm|Vex=3D2|Space0F38|VexVVVV=3D1|VexW=
=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIn=
dex|RegYMM, RegYMM, RegYMM }
>  vpermpd, 0x6601, None, CpuAVX2, Modrm|Vex=3D2|Space0F3A|VexW=3D2|No_bSuf=
|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|Re=
gYMM, RegYMM }
> @@ -2068,21 +2044,21 @@ vpclmulhqhqdq, 0x6644, 0x11, CpuVPCLMULQ
>      d:CpuAVX512F:CpuAVX512DQ:66:f2:66:Space0F:Space0F38:1:VexW1:Qword, +
>      h:CpuAVX512_FP16:CpuAVX512_FP16::f3::EVexMap5:EVexMap6:0:VexW0:Word>
>
> -kandnw, 0x42, None, CpuAVX512F, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|VexW=
=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, =
RegMask }
> -kandw, 0x41, None, CpuAVX512F, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|VexW=3D=
1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, Reg=
Mask }
> -korw, 0x45, None, CpuAVX512F, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|VexW=3D1=
|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegM=
ask }
> -kxnorw, 0x46, None, CpuAVX512F, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|VexW=
=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, =
RegMask }
> -kxorw, 0x47, None, CpuAVX512F, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|VexW=3D=
1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, Reg=
Mask }
> -
> -kmovw, 0x90, None, CpuAVX512F, Modrm|Vex=3D1|Space0F|VexW0|No_bSuf|No_wS=
uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask|Word|Unspecified|BaseIndex, =
RegMask }
> -kmovw, 0x91, None, CpuAVX512F, Modrm|Vex=3D1|Space0F|VexW0|No_bSuf|No_wS=
uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, Word|Unspecified|BaseIndex =
}
> -kmovw, 0x92, None, CpuAVX512F, D|Modrm|Vex=3D1|Space0F|VexW=3D1|No_bSuf|=
No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, RegMask }
> +kand<bw>, 0x<bw:kpfx>41, None, <bw:kcpu>, Modrm|Vex256|Space0F|VexVVVV|V=
exW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, =
RegMask }
> +kandn<bw>, 0x<bw:kpfx>42, None, <bw:kcpu>, Modrm|Vex256|Space0F|VexVVVV|=
VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask,=
 RegMask }
> +kor<bw>, 0x<bw:kpfx>45, None, <bw:kcpu>, Modrm|Vex256|Space0F|VexVVVV|Ve=
xW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, R=
egMask }
> +kxnor<bw>, 0x<bw:kpfx>46, None, <bw:kcpu>, Modrm|Vex256|Space0F|VexVVVV|=
VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask,=
 RegMask }
> +kxor<bw>, 0x<bw:kpfx>47, None, <bw:kcpu>, Modrm|Vex256|Space0F|VexVVVV|V=
exW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, =
RegMask }
> +
> +kmov<bw>, 0x<bw:kpfx>90, None, <bw:kcpu>, Modrm|Vex128|Space0F|VexW0|No_=
bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask|<bw:elem>|Unspecif=
ied|BaseIndex, RegMask }
> +kmov<bw>, 0x<bw:kpfx>91, None, <bw:kcpu>, Modrm|Vex128|Space0F|VexW0|No_=
bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, <bw:elem>|Unspeci=
fied|BaseIndex }
> +kmov<bw>, 0x<bw:kpfx>92, None, <bw:kcpu>, D|Modrm|Vex128|Space0F|VexW0|N=
o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, RegMask }
>
> -knotw, 0x44, None, CpuAVX512F, Modrm|Vex=3D1|Space0F|VexW=3D1|No_bSuf|No=
_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
> -kortestw, 0x98, None, CpuAVX512F, Modrm|Vex=3D1|Space0F|VexW=3D1|No_bSuf=
|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
> +knot<bw>, 0x<bw:kpfx>44, None, <bw:kcpu>, Modrm|Vex128|Space0F|VexW0|No_=
bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
> +kortest<bw>, 0x<bw:kpfx>98, None, <bw:kcpu>, Modrm|Vex128|Space0F|VexW0|=
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
>
> -kshiftlw, 0x6632, None, CpuAVX512F, Modrm|Vex=3D1|Space0F3A|VexW=3D2|No_=
bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMask, RegMask }
> -kshiftrw, 0x6630, None, CpuAVX512F, Modrm|Vex=3D1|Space0F3A|VexW=3D2|No_=
bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMask, RegMask }
> +kshiftl<bw>, 0x6632, None, <bw:kcpu>, Modrm|Vex128|Space0F3A|<bw:vexw>|N=
o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMask, RegMask }
> +kshiftr<bw>, 0x6630, None, <bw:kcpu>, Modrm|Vex128|Space0F3A|<bw:vexw>|N=
o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMask, RegMask }
>
>  kunpckbw, 0x664B, None, CpuAVX512F, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|Ve=
xW=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask=
, RegMask }
>
> @@ -2646,12 +2622,11 @@ vdbpsadbw, 0x6642, None, CpuAVX512BW, Mo
>  vmovdqu8, 0xF26F, None, CpuAVX512BW, D|Modrm|MaskingMorZ|Space0F|VexW=3D=
1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSu=
f|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|Reg=
ZMM }
>  vmovdqu16, 0xF26F, None, CpuAVX512BW, D|Modrm|MaskingMorZ|Space0F|VexW=
=3D2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_l=
dSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|=
RegZMM }
>
> -vpabsb, 0x661C, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F38|VexWIG|Di=
sp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {=
 RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
> +vpabs<bw>, 0x661c | <bw:opc>, None, CpuAVX512BW, Modrm|Masking=3D3|Space=
0F38|VexWIG|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS=
uf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|Re=
gZMM }
>  vpmaxsb, 0x663C, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F38|VexWIG|V=
exVVVV=3D1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu=
f|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|Reg=
ZMM, RegXMM|RegYMM|RegZMM }
>  vpminsb, 0x6638, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F38|VexWIG|V=
exVVVV=3D1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu=
f|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|Reg=
ZMM, RegXMM|RegYMM|RegZMM }
>  vpshufb, 0x6600, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F38|VexWIG|V=
exVVVV=3D1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu=
f|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|Reg=
ZMM, RegXMM|RegYMM|RegZMM }
>
> -vpabsw, 0x661D, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F38|VexWIG|Di=
sp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {=
 RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
>  vpmaddubsw, 0x6604, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F38|VexWI=
G|VexVVVV=3D1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_=
qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|=
RegZMM, RegXMM|RegYMM|RegZMM }
>  vpmaxuw, 0x663E, None, CpuAVX512BW, Modrm|Masking=3D3|VexWIG|Space0F38|V=
exVVVV=3D1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu=
f|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|Reg=
ZMM, RegXMM|RegYMM|RegZMM }
>  vpminuw, 0x663A, None, CpuAVX512BW, Modrm|Masking=3D3|VexWIG|Space0F38|V=
exVVVV=3D1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu=
f|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|Reg=
ZMM, RegXMM|RegYMM|RegZMM }
> @@ -2662,22 +2637,18 @@ vpacksswb, 0x6663, None, CpuAVX512BW, Mo
>  vpackuswb, 0x6667, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F|VexWIG|V=
exVVVV=3D1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu=
f|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|Reg=
ZMM, RegXMM|RegYMM|RegZMM }
>  vpackusdw, 0x662B, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F38|VexVVV=
V=3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|=
No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseInde=
x, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
>
> -vpaddb, 0x66FC, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F|VexWIG|VexV=
VVV=3D1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N=
o_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM=
, RegXMM|RegYMM|RegZMM }
> -vpaddsb, 0x66EC, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F|VexWIG|Vex=
VVVV=3D1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|=
No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZM=
M, RegXMM|RegYMM|RegZMM }
> -vpaddusb, 0x66DC, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F|VexWIG|Ve=
xVVVV=3D1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf=
|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZ=
MM, RegXMM|RegYMM|RegZMM }
> -vpavgb, 0x66E0, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F|VexWIG|VexV=
VVV=3D1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N=
o_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM=
, RegXMM|RegYMM|RegZMM }
> +vpadd<bw>, 0x66fc | <bw:opc>, None, CpuAVX512BW, Modrm|Masking=3D3|Space=
0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf=
|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|Reg=
YMM|RegZMM, RegXMM|RegYMM|RegZMM }
> +vpadds<bw>, 0x66ec | <bw:opc>, None, CpuAVX512BW, Modrm|Masking=3D3|Spac=
e0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSu=
f|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|Re=
gYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> +vpaddus<bw>, 0x66dc | <bw:opc>, None, CpuAVX512BW, Modrm|Masking=3D3|Spa=
ce0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS=
uf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|R=
egYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> +vpavg<bw>, 0x66e0 | (3 * <bw:opc>), None, CpuAVX512BW, Modrm|Masking=3D3=
|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N=
o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegX=
MM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
>  vpmaxub, 0x66DE, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F|VexWIG|Vex=
VVVV=3D1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|=
No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZM=
M, RegXMM|RegYMM|RegZMM }
>  vpminub, 0x66DA, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F|VexWIG|Vex=
VVVV=3D1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|=
No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZM=
M, RegXMM|RegYMM|RegZMM }
> -vpsubb, 0x66F8, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F|VexWIG|VexV=
VVV=3D1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N=
o_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegY=
MM|RegZMM, RegXMM|RegYMM|RegZMM }
> -vpsubsb, 0x66E8, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F|VexWIG|Vex=
VVVV=3D1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|=
No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZM=
M, RegXMM|RegYMM|RegZMM }
> -vpsubusb, 0x66D8, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F|VexWIG|Ve=
xVVVV=3D1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf=
|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZ=
MM, RegXMM|RegYMM|RegZMM }
> +vpsub<bw>, 0x66f8 | <bw:opc>, None, CpuAVX512BW, Modrm|Masking=3D3|Space=
0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf=
|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, R=
egXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> +vpsubs<bw>, 0x66e8 | <bw:opc>, None, CpuAVX512BW, Modrm|Masking=3D3|Spac=
e0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSu=
f|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|Re=
gYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> +vpsubus<bw>, 0x66d8 | <bw:opc>, None, CpuAVX512BW, Modrm|Masking=3D3|Spa=
ce0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS=
uf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|R=
egYMM|RegZMM, RegXMM|RegYMM|RegZMM }
>  vpunpckhbw, 0x6668, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F|VexWIG|=
VexVVVV=3D1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS=
uf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|Re=
gZMM, RegXMM|RegYMM|RegZMM }
>  vpunpcklbw, 0x6660, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F|VexWIG|=
VexVVVV=3D1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS=
uf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|Re=
gZMM, RegXMM|RegYMM|RegZMM }
>
> -vpaddsw, 0x66ED, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F|VexWIG|Vex=
VVVV=3D1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|=
No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZM=
M, RegXMM|RegYMM|RegZMM }
> -vpaddusw, 0x66DD, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F|VexWIG|Ve=
xVVVV=3D1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf=
|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZ=
MM, RegXMM|RegYMM|RegZMM }
> -vpaddw, 0x66FD, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F|VexWIG|VexV=
VVV=3D1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N=
o_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM=
, RegXMM|RegYMM|RegZMM }
> -vpavgw, 0x66E3, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F|VexWIG|VexV=
VVV=3D1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N=
o_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM=
, RegXMM|RegYMM|RegZMM }
>  vpmaxsw, 0x66EE, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F|VexWIG|Vex=
VVVV=3D1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|=
No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZM=
M, RegXMM|RegYMM|RegZMM }
>  vpminsw, 0x66EA, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F|VexWIG|Vex=
VVVV=3D1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|=
No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZM=
M, RegXMM|RegYMM|RegZMM }
>  vpmulhuw, 0x66E4, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F|VexWIG|Ve=
xVVVV=3D1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf=
|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZ=
MM, RegXMM|RegYMM|RegZMM }
> @@ -2689,64 +2660,45 @@ vpsraw, 0x6671, 4, CpuAVX512BW, Modrm|Ma
>  vpsraw, 0x66E1, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F|VexWIG|VexV=
VVV|Disp8MemShift=3D4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|=
No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegY=
MM|RegZMM }
>  vpsrlw, 0x6671, 2, CpuAVX512BW, Modrm|Masking=3D3|Space0F|VexWIG|VexVVVV=
=3D2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_l=
dSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|Reg=
ZMM }
>  vpsrlw, 0x66D1, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F|VexWIG|VexV=
VVV|Disp8MemShift=3D4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|=
No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegY=
MM|RegZMM }
> -vpsubsw, 0x66E9, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F|VexWIG|Vex=
VVVV=3D1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|=
No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZM=
M, RegXMM|RegYMM|RegZMM }
> -vpsubusw, 0x66D9, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F|VexWIG|Ve=
xVVVV=3D1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf=
|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZ=
MM, RegXMM|RegYMM|RegZMM }
> -vpsubw, 0x66F9, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F|VexVVVV=3D1=
|VexWIG|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N=
o_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegY=
MM|RegZMM, RegXMM|RegYMM|RegZMM }
>  vpunpckhwd, 0x6669, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F|VexWIG|=
VexVVVV=3D1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS=
uf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|Re=
gZMM, RegXMM|RegYMM|RegZMM }
>  vpunpcklwd, 0x6661, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F|VexWIG|=
VexVVVV=3D1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS=
uf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|Re=
gZMM, RegXMM|RegYMM|RegZMM }
>
>  vpalignr, 0x660F, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F3A|VexWIG|=
VexVVVV=3D1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS=
uf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|Reg=
YMM|RegZMM, RegXMM|RegYMM|RegZMM }
>
> -vpblendmb, 0x6666, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F38|VexVVV=
V=3D1|VexW=3D1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No=
_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM=
|RegZMM, RegXMM|RegYMM|RegZMM }
> -vpbroadcastb, 0x6678, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F38|Vex=
W0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Byte|Unspecif=
ied|BaseIndex, RegXMM|RegYMM|RegZMM }
> -vpbroadcastb, 0x667A, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F38|Vex=
W=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, RegXMM|Reg=
YMM|RegZMM }
> -
> -vpblendmw, 0x6666, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F38|VexVVV=
V=3D1|VexW=3D2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No=
_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM=
|RegZMM, RegXMM|RegYMM|RegZMM }
> -vpermi2w, 0x6675, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F38|VexVVVV=
=3D1|VexW=3D2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_=
qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|=
RegZMM, RegXMM|RegYMM|RegZMM }
> -vpermt2w, 0x667D, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F38|VexVVVV=
=3D1|VexW=3D2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_=
qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|=
RegZMM, RegXMM|RegYMM|RegZMM }
> -vpermw, 0x668D, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F38|VexVVVV=
=3D1|VexW=3D2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_=
qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|=
RegZMM, RegXMM|RegYMM|RegZMM }
> +vpblendm<bw>, 0x6666, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F38|Vex=
VVVV=3D1|<bw:vexw>|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSu=
f|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|Re=
gYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> +vpbroadcast<bw>, 0x6678 | <bw:opc>, None, CpuAVX512BW, Modrm|Masking=3D3=
|Space0F38|VexW0|Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_l=
dSuf, { RegXMM|<bw:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
> +vpbroadcast<bw>, 0x667a | <bw:opc>, None, CpuAVX512BW, Modrm|Masking=3D3=
|Space0F38|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32,=
 RegXMM|RegYMM|RegZMM }
> +
> +vpermi2<bw>, 0x6675, None, <bw:cpubmi>, Modrm|Masking=3D3|Space0F38|VexV=
VVV|<bw:vexw>|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_=
qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|=
RegZMM, RegXMM|RegYMM|RegZMM }
> +vpermt2<bw>, 0x667d, None, <bw:cpubmi>, Modrm|Masking=3D3|Space0F38|VexV=
VVV|<bw:vexw>|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_=
qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|=
RegZMM, RegXMM|RegYMM|RegZMM }
> +vperm<bw>, 0x668d, None, <bw:cpubmi>, Modrm|Masking=3D3|Space0F38|VexVVV=
V|<bw:vexw>|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS=
uf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|Re=
gZMM, RegXMM|RegYMM|RegZMM }
>  vpsllvw, 0x6612, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F38|VexVVVV=
=3D1|VexW=3D2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_=
qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|=
RegZMM, RegXMM|RegYMM|RegZMM }
>  vpsravw, 0x6611, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F38|VexVVVV=
=3D1|VexW=3D2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_=
qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|=
RegZMM, RegXMM|RegYMM|RegZMM }
>  vpsrlvw, 0x6610, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F38|VexVVVV=
=3D1|VexW=3D2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_=
qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|=
RegZMM, RegXMM|RegYMM|RegZMM }
>
> -vpbroadcastw, 0x6679, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F38|Vex=
W0|Disp8MemShift=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Re=
gXMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
> -vpbroadcastw, 0x667B, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F38|Vex=
W=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, RegXMM|Reg=
YMM|RegZMM }
> -
> -vpcmpeqb, 0x6674, None, CpuAVX512BW, Modrm|Masking=3D2|Space0F|VexWIG|Ve=
xVVVV=3D1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf=
|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZ=
MM, RegMask }
> -vpcmpgtb, 0x6664, None, CpuAVX512BW, Modrm|Masking=3D2|Space0F|VexWIG|Ve=
xVVVV=3D1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf=
|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZ=
MM, RegMask }
> -vpcmpb, 0x663F, None, CpuAVX512BW, Modrm|Masking=3D2|Space0F3A|VexVVVV=
=3D1|VexW=3D1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_=
qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|R=
egYMM|RegZMM, RegMask }
> -vpcmp<avx_irel>b, 0x663F, <avx_irel:imm>, CpuAVX512BW, Modrm|Masking=3D2=
|Space0F3A|VexVVVV|VexW0|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|=
No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseInd=
ex, RegXMM|RegYMM|RegZMM, RegMask }
> -vpcmpub, 0x663E, None, CpuAVX512BW, Modrm|Masking=3D2|Space0F3A|VexVVVV=
=3D1|VexW=3D1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_=
qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|R=
egYMM|RegZMM, RegMask }
> -vpcmp<avx_irel>ub, 0x663E, <avx_irel:imm>, CpuAVX512BW, Modrm|Masking=3D=
2|Space0F3A|VexVVVV|VexW0|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf=
|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIn=
dex, RegXMM|RegYMM|RegZMM, RegMask }
> -
> -vpcmpeqw, 0x6675, None, CpuAVX512BW, Modrm|Masking=3D2|Space0F|VexWIG|Ve=
xVVVV=3D1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf=
|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZ=
MM, RegMask }
> -vpcmpgtw, 0x6665, None, CpuAVX512BW, Modrm|Masking=3D2|Space0F|VexWIG|Ve=
xVVVV=3D1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf=
|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZ=
MM, RegMask }
> -vpcmpw, 0x663F, None, CpuAVX512BW, Modrm|Masking=3D2|Space0F3A|VexVVVV=
=3D1|VexW=3D2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_=
qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|R=
egYMM|RegZMM, RegMask }
> -vpcmp<avx_irel>w, 0x663F, <avx_irel:imm>, CpuAVX512BW, Modrm|Masking=3D2=
|Space0F3A|VexVVVV|VexW1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|=
No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseInd=
ex, RegXMM|RegYMM|RegZMM, RegMask }
> -vpcmpuw, 0x663E, None, CpuAVX512BW, Modrm|Masking=3D2|Space0F3A|VexVVVV=
=3D1|VexW=3D2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_=
qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|R=
egYMM|RegZMM, RegMask }
> -vpcmp<avx_irel>uw, 0x663E, <avx_irel:imm>, CpuAVX512BW, Modrm|Masking=3D=
2|Space0F3A|VexVVVV|VexW1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf=
|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIn=
dex, RegXMM|RegYMM|RegZMM, RegMask }
> +vpcmpeq<bw>, 0x6674 | <bw:opc>, None, CpuAVX512BW, Modrm|Masking=3D2|Spa=
ce0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS=
uf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|R=
egYMM|RegZMM, RegMask }
> +vpcmpgt<bw>, 0x6664 | <bw:opc>, None, CpuAVX512BW, Modrm|Masking=3D2|Spa=
ce0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS=
uf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|R=
egYMM|RegZMM, RegMask }
> +vpcmp<bw>, 0x663f, None, CpuAVX512BW, Modrm|Masking=3D2|Space0F3A|VexVVV=
V|<bw:vexw>|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS=
uf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|Reg=
YMM|RegZMM, RegMask }
> +vpcmpu<bw>, 0x663e, None, CpuAVX512BW, Modrm|Masking=3D2|Space0F3A|VexVV=
VV|<bw:vexw>|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_q=
Suf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|Re=
gYMM|RegZMM, RegMask }
> +vpcmp<avx_irel><bw>, 0x663f, <avx_irel:imm>, CpuAVX512BW, Modrm|Masking=
=3D2|Space0F3A|VexVVVV|<bw:vexw>|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|=
No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified=
|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
> +vpcmp<avx_irel>u<bw>, 0x663e, <avx_irel:imm>, CpuAVX512BW, Modrm|Masking=
=3D2|Space0F3A|VexVVVV|<bw:vexw>|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|=
No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified=
|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
>
>  vpslldq, 0x6673, 7, CpuAVX512BW, Modrm|Space0F|VexWIG|VexVVVV=3D2|Disp8S=
hiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm=
8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
>  vpsrldq, 0x6673, 3, CpuAVX512BW, Modrm|Space0F|VexWIG|VexVVVV=3D2|Disp8S=
hiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm=
8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
>
>  vpextrw, 0x66C5, None, CpuAVX512BW, Load|Modrm|EVex128|Space0F|VexWIG|No=
_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64=
 }
> -vpextrw, 0x6615, None, CpuAVX512BW, RegMem|EVex128|Space0F3A|VexWIG|No_b=
Suf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64 }
> -vpextrw, 0x6615, None, CpuAVX512BW, Modrm|EVex128|Space0F3A|VexWIG|Disp8=
MemShift=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegX=
MM, Word|Unspecified|BaseIndex }
> +vpextr<bw>, 0x6614 | <bw:opc>, None, CpuAVX512BW, RegMem|EVex128|Space0F=
3A|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM,=
 Reg32|Reg64 }
> +vpextr<bw>, 0x6614 | <bw:opc>, None, CpuAVX512BW, Modrm|EVex128|Space0F3=
A|VexWIG|Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { =
Imm8, RegXMM, <bw:elem>|Unspecified|BaseIndex }
> +
>  vpinsrw, 0x66C4, None, CpuAVX512BW, Modrm|EVex128|Space0F|VexWIG|VexVVVV=
=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg32|Reg64,=
 RegXMM, RegXMM }
>  vpinsrw, 0x66C4, None, CpuAVX512BW, Modrm|EVex128|Space0F|VexWIG|VexVVVV=
|Disp8MemShift=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8=
, Word|Unspecified|BaseIndex, RegXMM, RegXMM }
> -
> -vpextrb, 0x6614, None, CpuAVX512BW, RegMem|EVex128|Space0F3A|VexWIG|No_b=
Suf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64 }
> -vpextrb, 0x6614, None, CpuAVX512BW, Modrm|EVex128|Space0F3A|VexWIG|No_bS=
uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Byte|Unspecifi=
ed|BaseIndex }
>  vpinsrb, 0x6620, None, CpuAVX512BW, Modrm|EVex128|Space0F3A|VexWIG|VexVV=
VV=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg32|Reg6=
4, RegXMM, RegXMM }
>  vpinsrb, 0x6620, None, CpuAVX512BW, Modrm|EVex128|Space0F3A|VexWIG|VexVV=
VV|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Byte|Unspecifi=
ed|BaseIndex, RegXMM, RegXMM }
>
>  vpmaddwd, 0x66F5, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F|VexVVVV=
=3D1|VexWIG|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS=
uf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|Re=
gZMM, RegXMM|RegYMM|RegZMM }
>
> -vpmovb2m, 0xF329, None, CpuAVX512BW, Modrm|EVex=3D5|Space0F38|VexW=3D1|N=
o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, Re=
gMask }
> -vpmovw2m, 0xF329, None, CpuAVX512BW, Modrm|EVex=3D5|Space0F38|VexW=3D2|N=
o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, Re=
gMask }
> -
> -vpmovm2b, 0xF328, None, CpuAVX512BW, Modrm|EVex=3D5|Space0F38|VexW=3D1|N=
o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegXMM|RegYMM|R=
egZMM }
> -vpmovm2w, 0xF328, None, CpuAVX512BW, Modrm|EVex=3D5|Space0F38|VexW=3D2|N=
o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegXMM|RegYMM|R=
egZMM }
> +vpmov<bw>2m, 0xf329, None, CpuAVX512BW, Modrm|EVexDYN|Space0F38|<bw:vexw=
>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM,=
 RegMask }
> +vpmovm2<bw>, 0xf328, None, CpuAVX512BW, Modrm|EVexDYN|Space0F38|<bw:vexw=
>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegXMM|RegYM=
M|RegZMM }
>
>  vpmovswb, 0xF320, None, CpuAVX512BW, Modrm|EVex=3D1|MaskingMorZ|Space0F3=
8|VexW=3D1|Disp8MemShift=3D5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS=
uf, { RegZMM, RegYMM|Unspecified|BaseIndex }
>  vpmovswb, 0xF320, None, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3D2|MaskingM=
orZ|Space0F38|VexW0|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS=
uf|No_ldSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex }
> @@ -2772,34 +2724,15 @@ vpsadbw, 0x66F6, None, CpuAVX512BW, Modr
>  vpshufhw, 0xF370, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F|VexWIG|Di=
sp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {=
 Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
>  vpshuflw, 0xF270, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F|VexWIG|Di=
sp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {=
 Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
>
> -vptestmb, 0x6626, None, CpuAVX512BW, Modrm|Masking=3D2|Space0F38|VexVVVV=
=3D1|VexW=3D1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_=
qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|=
RegZMM, RegMask }
> -vptestmw, 0x6626, None, CpuAVX512BW, Modrm|Masking=3D2|Space0F38|VexVVVV=
=3D1|VexW=3D2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_=
qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|=
RegZMM, RegMask }
> -
> -vptestnmb, 0xF326, None, CpuAVX512BW, Modrm|Masking=3D2|Space0F38|VexVVV=
V=3D1|VexW=3D1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No=
_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM=
|RegZMM, RegMask }
> -vptestnmw, 0xF326, None, CpuAVX512BW, Modrm|Masking=3D2|Space0F38|VexVVV=
V=3D1|VexW=3D2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No=
_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM=
|RegZMM, RegMask }
> +vptestm<bw>, 0x6626, None, CpuAVX512BW, Modrm|Masking=3D2|Space0F38|VexV=
VVV|<bw:vexw>|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_=
qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|=
RegZMM, RegMask }
> +vptestnm<bw>, 0xf326, None, CpuAVX512BW, Modrm|Masking=3D2|Space0F38|Vex=
VVVV|<bw:vexw>|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No=
_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM=
|RegZMM, RegMask }
>
>  // AVX512BW instructions end.
>
>  // AVX512DQ instructions.
>
> -kaddb, 0x664A, None, CpuAVX512DQ, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|VexW=
=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, =
RegMask }
> -kandb, 0x6641, None, CpuAVX512DQ, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|VexW=
=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, =
RegMask }
> -kandnb, 0x6642, None, CpuAVX512DQ, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|Vex=
W=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask,=
 RegMask }
> -kmovb, 0x6690, None, CpuAVX512DQ, Modrm|Vex=3D1|Space0F|VexW0|No_bSuf|No=
_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask|Byte|Unspecified|BaseInde=
x, RegMask }
> -kmovb, 0x6691, None, CpuAVX512DQ, Modrm|Vex=3D1|Space0F|VexW0|No_bSuf|No=
_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, Byte|Unspecified|BaseInd=
ex }
> -kmovb, 0x6692, None, CpuAVX512DQ, D|Modrm|Vex=3D1|Space0F|VexW=3D1|No_bS=
uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, RegMask }
> -knotb, 0x6644, None, CpuAVX512DQ, Modrm|Vex=3D1|Space0F|VexW=3D1|No_bSuf=
|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
> -korb, 0x6645, None, CpuAVX512DQ, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|VexW=
=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, =
RegMask }
> -kortestb, 0x6698, None, CpuAVX512DQ, Modrm|Vex=3D1|Space0F|VexW=3D1|No_b=
Suf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
> -ktestb, 0x6699, None, CpuAVX512DQ, Modrm|Vex=3D1|Space0F|VexW=3D1|No_bSu=
f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
> -kxnorb, 0x6646, None, CpuAVX512DQ, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|Vex=
W=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask,=
 RegMask }
> -kxorb, 0x6647, None, CpuAVX512DQ, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|VexW=
=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, =
RegMask }
> -
> -kaddw, 0x4A, None, CpuAVX512DQ, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|VexW=
=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, =
RegMask }
> -ktestw, 0x99, None, CpuAVX512DQ, Modrm|Vex=3D1|Space0F|VexW=3D1|No_bSuf|=
No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
> -
> -kshiftlb, 0x6632, None, CpuAVX512DQ, Modrm|Vex=3D1|Space0F3A|VexW=3D1|No=
_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMask, RegMask }
> -kshiftrb, 0x6630, None, CpuAVX512DQ, Modrm|Vex=3D1|Space0F3A|VexW=3D1|No=
_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMask, RegMask }
> +kadd<bw>, 0x<bw:kpfx>4A, None, CpuAVX512DQ, Modrm|Vex256|Space0F|VexVVVV=
|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask=
, RegMask }
> +ktest<bw>, 0x<bw:kpfx>99, None, CpuAVX512DQ, Modrm|Vex128|Space0F|VexW0|=
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
>
>  vandnp<sd>, 0x<sd:ppfx>55, None, CpuAVX512DQ, Modrm|Masking=3D3|Space0F|=
VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lS=
uf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unsp=
ecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
>  vandp<sd>, 0x<sd:ppfx>54, None, CpuAVX512DQ, Modrm|Masking=3D3|Space0F|V=
exVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSu=
f|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|Ba=
seIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> @@ -2898,9 +2831,6 @@ vpmadd52luq, 0x66B4, None, CpuAVX512IFMA
>  // AVX512VBMI instructions
>
>  vpmultishiftqb, 0x6683, None, CpuAVX512VBMI, Modrm|Masking=3D3|Space0F38=
|VexVVVV=3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|N=
o_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|B=
aseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> -vpermb, 0x668D, None, CpuAVX512VBMI, Modrm|Masking=3D3|Space0F38|VexVVVV=
=3D1|VexW=3D1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_=
qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|=
RegZMM, RegXMM|RegYMM|RegZMM }
> -vpermi2b, 0x6675, None, CpuAVX512VBMI, Modrm|Masking=3D3|Space0F38|VexVV=
VV=3D1|VexW=3D1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N=
o_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYM=
M|RegZMM, RegXMM|RegYMM|RegZMM }
> -vpermt2b, 0x667D, None, CpuAVX512VBMI, Modrm|Masking=3D3|Space0F38|VexVV=
VV=3D1|VexW=3D1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N=
o_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYM=
M|RegZMM, RegXMM|RegYMM|RegZMM }
>
>  // AVX512VBMI instructions end
>
> @@ -2970,8 +2900,7 @@ vpdpwssds, 0x6653, None, CpuAVX512_VNNI,
>
>  // AVX512_BITALG instructions
>
> -vpopcntb, 0x6654, None, CpuAVX512_BITALG, Modrm|Masking=3D3|Space0F38|Ve=
xW=3D1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No=
_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM =
}
> -vpopcntw, 0x6654, None, CpuAVX512_BITALG, Modrm|Masking=3D3|Space0F38|Ve=
xW=3D2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No=
_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM =
}
> +vpopcnt<bw>, 0x6654, None, CpuAVX512_BITALG, Modrm|Masking=3D3|Space0F38=
|<bw:vexw>|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu=
f|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|Reg=
ZMM }
>
>  vpshufbitqmb, 0x668f, None, CpuAVX512_BITALG, Modrm|Masking=3D2|Space0F3=
8|VexVVVV=3D1|VexW=3D1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No=
_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXM=
M|RegYMM|RegZMM, RegMask }
>
>

OK.

Thanks.

--=20
H.J.