From: "H.J. Lu" <hjl.tools@gmail.com>
To: Jan Beulich <jbeulich@suse.com>
Cc: "binutils@sourceware.org" <binutils@sourceware.org>
Subject: Re: [PATCH 3/9] x86: correct MPX insn w/o base or index encoding in 16-bit mode
Date: Wed, 04 Mar 2020 11:46:00 -0000 [thread overview]
Message-ID: <CAMe9rOoUvU2v0v+DbnxgL64ire7WBV2Ce0ZOqg2cdJ2oMim3Ew@mail.gmail.com> (raw)
In-Reply-To: <77f0a1e8-f146-e043-2d30-23b54b08755d@suse.com>
On Wed, Mar 4, 2020 at 1:38 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> Since 16-bit addressing isn't allowed, Disp32 needs to be forced; Disp16
> fails to match the templates.
>
> The SDM leaves open whether BNDC[LNU] with a GPR operand require an
> operand size override; this aspect is therefore left untouched here.
>
> gas/
> 2020-03-XX Jan Beulich <jbeulich@suse.com>
>
> * config/tc-i386.c (i386_addressing_mode): For 32-bit
> addressing for MPX insns without base/index.
> * testsuite/gas/i386/mpx-16bit.s,
> * testsuite/gas/i386/mpx-16bit.d: New.
> * testsuite/gas/i386/i386.exp: Run new test.
>
> opcodes/
> 2020-03-XX Jan Beulich <jbeulich@suse.com>
>
> * i386-dis.c (OP_E_memory): Exclude recording of used address
> prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
> addressed memory operands for MPX insns.
>
> --- a/gas/config/tc-i386.c
> +++ b/gas/config/tc-i386.c
> @@ -10297,6 +10297,21 @@ i386_addressing_mode (void)
>
> if (i.prefix[ADDR_PREFIX])
> addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
> + else if (flag_code == CODE_16BIT
> + && current_templates->start->cpu_flags.bitfield.cpumpx
> + /* Avoid replacing the "16-bit addressing not allowed" diagnostic
> + from md_assemble() by "is not a valid base/index expression"
> + when there is a base and/or index. */
> + && !i.types[this_operand].bitfield.baseindex)
> + {
> + /* MPX insn memory operands with neither base nor index must be forced
> + to use 32-bit addressing in 16-bit mode. */
> + addr_mode = CODE_32BIT;
> + i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
> + ++i.prefixes;
> + gas_assert (!i.types[this_operand].bitfield.disp16);
> + gas_assert (!i.types[this_operand].bitfield.disp32);
> + }
> else
> {
Since MPX isn't available in 16-bit mode, should they be disallowed? Given that
MPX has been deprecated, I prefer an error here.
--
H.J.
next prev parent reply other threads:[~2020-03-04 11:46 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-04 9:32 [PATCH 0/9] x86: (mainly) misc IgnoreSize related adjustments Jan Beulich
2020-03-04 9:41 ` [PATCH 1/9] x86: refine TPAUSE and UMWAIT Jan Beulich
2020-03-04 11:37 ` H.J. Lu
2020-03-04 11:40 ` Jan Beulich
2020-03-04 11:44 ` H.J. Lu
2020-03-05 8:08 ` Jan Beulich
2020-03-05 14:05 ` H.J. Lu
2020-03-05 14:08 ` Jan Beulich
2020-03-05 14:38 ` H.J. Lu
2020-03-05 14:51 ` Jan Beulich
2020-03-05 14:54 ` H.J. Lu
2020-03-05 15:16 ` Jan Beulich
2020-03-05 15:22 ` Jan Beulich
2020-03-05 15:37 ` H.J. Lu
2020-03-05 15:42 ` Jan Beulich
2020-03-05 16:00 ` H.J. Lu
2020-03-04 9:42 ` [PATCH 2/9] x86: add missing IgnoreSize Jan Beulich
2020-03-04 11:40 ` H.J. Lu
2020-03-04 9:43 ` [PATCH 3/9] x86: correct MPX insn w/o base or index encoding in 16-bit mode Jan Beulich
2020-03-04 11:46 ` H.J. Lu [this message]
2020-03-04 11:50 ` Jan Beulich
2020-03-04 11:55 ` H.J. Lu
2020-03-04 12:58 ` Jan Beulich
2020-03-04 13:26 ` H.J. Lu
2020-03-04 9:44 ` [PATCH 4/9] x86: drop Rex64 attribute Jan Beulich
2020-03-04 11:47 ` H.J. Lu
2020-03-04 9:45 ` [PATCH 6/9] x86: don't accept FI{LD,STP,STTP}LL in Intel syntax mode Jan Beulich
2020-03-04 11:55 ` H.J. Lu
2020-03-04 9:46 ` [PATCH 7/9] x86: fold (supposed to be) identical code Jan Beulich
2020-03-04 11:56 ` H.J. Lu
2020-03-04 9:47 ` [PATCH 9/9] x86: reduce amount of various VCVT* templates Jan Beulich
2020-03-04 12:00 ` H.J. Lu
2020-03-04 10:15 ` [PATCH 8/9] x86: drop/replace IgnoreSize Jan Beulich
2020-03-04 11:59 ` H.J. Lu
2020-03-04 10:19 ` [PATCH 5/9] x86: replace NoRex64 on VEX-encoded insns Jan Beulich
2020-03-04 11:51 ` H.J. Lu
2020-03-05 8:07 ` [PATCH v1.1 1/9] x86: refine TPAUSE and UMWAIT Jan Beulich
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=CAMe9rOoUvU2v0v+DbnxgL64ire7WBV2Ce0ZOqg2cdJ2oMim3Ew@mail.gmail.com \
--to=hjl.tools@gmail.com \
--cc=binutils@sourceware.org \
--cc=jbeulich@suse.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).