From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pj1-x1029.google.com (mail-pj1-x1029.google.com [IPv6:2607:f8b0:4864:20::1029]) by sourceware.org (Postfix) with ESMTPS id B384F3857C6F for ; Thu, 14 Apr 2022 16:34:54 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org B384F3857C6F Received: by mail-pj1-x1029.google.com with SMTP id j8-20020a17090a060800b001cd4fb60dccso6187656pjj.2 for ; Thu, 14 Apr 2022 09:34:54 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=ehK4AqW7ufQ0CK3msjYcsGe+OE7W+ZzmnW6YYOga/Mw=; b=4lGfB101ivUIY8jFkBK3A1s+AD3kVamFJyKrPtFznkvAqsMKYjMKMNr5Em69efc6kE TVCdsQfaZIyjqKt2aimiAtSb2vvzMTd5ZVEV8rwTX44O/niC3K6ywiGB6mEbkMBZx6m2 PVJ0+iHUfndYnuyOYM1TMYte122+/jzWNdTO8kWRpjMBe2uOEajxaVOrRUB1prliD9QU SWy02YwppZBw8g59M8rlVnXdn+NuQ0iEiFC3pqnV8NijfjCvTbVD2piTjBItJQf2yvk/ bAxdAtYsp0R7wDthaTDvr5kIHnr59ZazVe8FRe6C19x3+Em1HH2hYugJCLG1amfi3e/c sPLg== X-Gm-Message-State: AOAM531znAZ/vyq+LYCT4zHvHo7X9HOSndr9iPGFK441cShuTyyzaSh2 Ao+lYzyOC56zsHJFVcBTscSMJvBPFnJ/10e09CQTQh2M X-Google-Smtp-Source: ABdhPJzhs51cjS+bfVI0smD5PgtAGGjU2C+lSPba6J5QnWae3kMhPvehOCGkTGfMf4fIuIjXjnPxxyniAfUieP5L4wk= X-Received: by 2002:a17:903:1108:b0:156:73a7:7c1 with SMTP id n8-20020a170903110800b0015673a707c1mr47423370plh.101.1649954093670; Thu, 14 Apr 2022 09:34:53 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: "H.J. Lu" Date: Thu, 14 Apr 2022 09:34:17 -0700 Message-ID: Subject: Re: [PATCH] x86: VCMPSH is Evex.LLIG To: "Cui, Lili" Cc: "Beulich, Jan" , Binutils Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-3019.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, LOTS_OF_MONEY, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 14 Apr 2022 16:34:57 -0000 On Thu, Apr 14, 2022 at 9:24 AM Cui, Lili wrote: > > > > > -----Original Message----- > > From: H.J. Lu > > Sent: Thursday, April 14, 2022 11:22 PM > > To: Beulich, Jan ; Cui, Lili > > Cc: Binutils > > Subject: Re: [PATCH] x86: VCMPSH is Evex.LLIG > > > > On Thu, Apr 14, 2022 at 7:12 AM Jan Beulich wrote: > > > > > > These were mistakenly flagged as Evex.128. Getting the LLIG status > > > right for insns allowing for SAE is a prereq for planned further work. > > > > > > --- a/gas/testsuite/gas/i386/evex-lig.s > > > +++ b/gas/testsuite/gas/i386/evex-lig.s > > > @@ -1703,6 +1703,13 @@ _start: > > > vrndscaless $123, -512(%edx), %xmm5, %xmm6{%k7} # AVX512 > > Disp8 > > > vrndscaless $123, -516(%edx), %xmm5, %xmm6{%k7} # AVX512 > > > > > > + vcmpsh $123, %xmm4, %xmm5, %k5 # AVX512-FP16 > > > + vcmpsh $123, {sae}, %xmm4, %xmm5, %k5{%k7} # AVX512-FP16 > > > + vcmpsh $123, (%ecx), %xmm5, %k5 # AVX512-FP16 > > > + vcmpsh $123, -123456(%esp, %esi, 8), %xmm5, %k5{%k7} # AVX512- > > FP16 > > > + vcmpsh $123, 254(%ecx), %xmm5, %k5 # AVX512-FP16 Disp8 > > > + vcmpsh $123, -256(%edx), %xmm5, %k5{%k7} # AVX512-FP16 > > Disp8 > > > + > > > .intel_syntax noprefix > > > vaddsd xmm6{k7}, xmm5, xmm4 # AVX512 > > > vaddsd xmm6{k7}{z}, xmm5, xmm4 # AVX512 @@ -3403,3 +3410,9 > > > @@ _start: > > > vrndscaless xmm6{k7}, xmm5, DWORD PTR [edx-512], 123 # > > AVX512 Disp8 > > > vrndscaless xmm6{k7}, xmm5, DWORD PTR [edx-516], 123 # > > AVX512 > > > > > > + vcmpsh k5, xmm5, xmm4, 123 # AVX512-FP16 > > > + vcmpsh k5{k7}, xmm5, xmm4, {sae}, 123 # AVX512-FP16 > > > + vcmpsh k5, xmm5, WORD PTR [ecx], 123 # AVX512-FP16 > > > + vcmpsh k5{k7}, xmm5, WORD PTR [esp+esi*8-123456], 123 # > > AVX512-FP16 > > > + vcmpsh k5, xmm5, WORD PTR [ecx+254], 123 # AVX512-FP16 > > Disp8 > > > + vcmpsh k5{k7}, xmm5, WORD PTR [edx-256], 123 # AVX512-FP16 > > Disp8 > > > --- a/gas/testsuite/gas/i386/evex-lig256-intel.d > > > +++ b/gas/testsuite/gas/i386/evex-lig256-intel.d > > > @@ -1536,6 +1536,12 @@ Disassembly of section .text: > > > [ ]*[a-f0-9]+: 62 f3 55 2f 0a b2 00 02 00 00 7b vrndscaless > > xmm6\{k7\},xmm5,DWORD PTR \[edx\+0x200\],0x7b > > > [ ]*[a-f0-9]+: 62 f3 55 2f 0a 72 80 7b vrndscaless > > xmm6\{k7\},xmm5,DWORD PTR \[edx-0x200\],0x7b > > > [ ]*[a-f0-9]+: 62 f3 55 2f 0a b2 fc fd ff ff 7b vrndscaless > > xmm6\{k7\},xmm5,DWORD PTR \[edx-0x204\],0x7b > > > +[ ]*[a-f0-9]+: 62 f3 56 28 c2 ec 7b vcmpsh k5,xmm5,xmm4,0x7b > > > +[ ]*[a-f0-9]+: 62 f3 56 1f c2 ec 7b vcmpsh > > k5\{k7\},xmm5,xmm4,\{sae\},0x7b > > > +[ ]*[a-f0-9]+: 62 f3 56 28 c2 29 7b vcmpsh k5,xmm5,WORD PTR > > \[ecx\],0x7b > > > +[ ]*[a-f0-9]+: 62 f3 56 2f c2 ac f4 c0 1d fe ff 7b vcmpsh > > k5\{k7\},xmm5,WORD PTR \[esp\+esi\*8-0x1e240\],0x7b > > > +[ ]*[a-f0-9]+: 62 f3 56 28 c2 69 7f 7b vcmpsh k5,xmm5,WORD PTR > > \[ecx\+0xfe\],0x7b > > > +[ ]*[a-f0-9]+: 62 f3 56 2f c2 6a 80 7b vcmpsh > > k5\{k7\},xmm5,WORD PTR \[edx-0x100\],0x7b > > > [ ]*[a-f0-9]+: 62 f1 d7 2f 58 f4 vaddsd xmm6\{k7\},xmm5,xmm4 > > > [ ]*[a-f0-9]+: 62 f1 d7 af 58 f4 vaddsd > > xmm6\{k7\}\{z\},xmm5,xmm4 > > > [ ]*[a-f0-9]+: 62 f1 d7 1f 58 f4 vaddsd > > xmm6\{k7\},xmm5,xmm4,\{rn-sae\} > > > @@ -3063,4 +3069,10 @@ Disassembly of section .text: > > > [ ]*[a-f0-9]+: 62 f3 55 2f 0a b2 00 02 00 00 7b vrndscaless > > xmm6\{k7\},xmm5,DWORD PTR \[edx\+0x200\],0x7b > > > [ ]*[a-f0-9]+: 62 f3 55 2f 0a 72 80 7b vrndscaless > > xmm6\{k7\},xmm5,DWORD PTR \[edx-0x200\],0x7b > > > [ ]*[a-f0-9]+: 62 f3 55 2f 0a b2 fc fd ff ff 7b vrndscaless > > xmm6\{k7\},xmm5,DWORD PTR \[edx-0x204\],0x7b > > > +[ ]*[a-f0-9]+: 62 f3 56 28 c2 ec 7b vcmpsh k5,xmm5,xmm4,0x7b > > > +[ ]*[a-f0-9]+: 62 f3 56 1f c2 ec 7b vcmpsh > > k5\{k7\},xmm5,xmm4,\{sae\},0x7b > > > +[ ]*[a-f0-9]+: 62 f3 56 28 c2 29 7b vcmpsh k5,xmm5,WORD PTR > > \[ecx\],0x7b > > > +[ ]*[a-f0-9]+: 62 f3 56 2f c2 ac f4 c0 1d fe ff 7b vcmpsh > > k5\{k7\},xmm5,WORD PTR \[esp\+esi\*8-0x1e240\],0x7b > > > +[ ]*[a-f0-9]+: 62 f3 56 28 c2 69 7f 7b vcmpsh k5,xmm5,WORD PTR > > \[ecx\+0xfe\],0x7b > > > +[ ]*[a-f0-9]+: 62 f3 56 2f c2 6a 80 7b vcmpsh > > k5\{k7\},xmm5,WORD PTR \[edx-0x100\],0x7b > > > #pass > > > --- a/gas/testsuite/gas/i386/evex-lig256.d > > > +++ b/gas/testsuite/gas/i386/evex-lig256.d > > > @@ -1536,6 +1536,12 @@ Disassembly of section .text: > > > [ ]*[a-f0-9]+: 62 f3 55 2f 0a b2 00 02 00 00 7b vrndscaless > > \$0x7b,0x200\(%edx\),%xmm5,%xmm6\{%k7\} > > > [ ]*[a-f0-9]+: 62 f3 55 2f 0a 72 80 7b vrndscaless \$0x7b,- > > 0x200\(%edx\),%xmm5,%xmm6\{%k7\} > > > [ ]*[a-f0-9]+: 62 f3 55 2f 0a b2 fc fd ff ff 7b vrndscaless \$0x7b,- > > 0x204\(%edx\),%xmm5,%xmm6\{%k7\} > > > +[ ]*[a-f0-9]+: 62 f3 56 28 c2 ec 7b vcmpsh > > \$0x7b,%xmm4,%xmm5,%k5 > > > +[ ]*[a-f0-9]+: 62 f3 56 1f c2 ec 7b vcmpsh > > \$0x7b,\{sae\},%xmm4,%xmm5,%k5\{%k7\} > > > +[ ]*[a-f0-9]+: 62 f3 56 28 c2 29 7b vcmpsh > > \$0x7b,\(%ecx\),%xmm5,%k5 > > > +[ ]*[a-f0-9]+: 62 f3 56 2f c2 ac f4 c0 1d fe ff 7b vcmpsh \$0x7b,- > > 0x1e240\(%esp,%esi,8\),%xmm5,%k5\{%k7\} > > > +[ ]*[a-f0-9]+: 62 f3 56 28 c2 69 7f 7b vcmpsh > > \$0x7b,0xfe\(%ecx\),%xmm5,%k5 > > > +[ ]*[a-f0-9]+: 62 f3 56 2f c2 6a 80 7b vcmpsh \$0x7b,- > > 0x100\(%edx\),%xmm5,%k5\{%k7\} > > > [ ]*[a-f0-9]+: 62 f1 d7 2f 58 f4 > > vaddsd %xmm4,%xmm5,%xmm6\{%k7\} > > > [ ]*[a-f0-9]+: 62 f1 d7 af 58 f4 > > vaddsd %xmm4,%xmm5,%xmm6\{%k7\}\{z\} > > > [ ]*[a-f0-9]+: 62 f1 d7 1f 58 f4 vaddsd \{rn- > > sae\},%xmm4,%xmm5,%xmm6\{%k7\} > > > @@ -3063,4 +3069,10 @@ Disassembly of section .text: > > > [ ]*[a-f0-9]+: 62 f3 55 2f 0a b2 00 02 00 00 7b vrndscaless > > \$0x7b,0x200\(%edx\),%xmm5,%xmm6\{%k7\} > > > [ ]*[a-f0-9]+: 62 f3 55 2f 0a 72 80 7b vrndscaless \$0x7b,- > > 0x200\(%edx\),%xmm5,%xmm6\{%k7\} > > > [ ]*[a-f0-9]+: 62 f3 55 2f 0a b2 fc fd ff ff 7b vrndscaless \$0x7b,- > > 0x204\(%edx\),%xmm5,%xmm6\{%k7\} > > > +[ ]*[a-f0-9]+: 62 f3 56 28 c2 ec 7b vcmpsh > > \$0x7b,%xmm4,%xmm5,%k5 > > > +[ ]*[a-f0-9]+: 62 f3 56 1f c2 ec 7b vcmpsh > > \$0x7b,\{sae\},%xmm4,%xmm5,%k5\{%k7\} > > > +[ ]*[a-f0-9]+: 62 f3 56 28 c2 29 7b vcmpsh > > \$0x7b,\(%ecx\),%xmm5,%k5 > > > +[ ]*[a-f0-9]+: 62 f3 56 2f c2 ac f4 c0 1d fe ff 7b vcmpsh \$0x7b,- > > 0x1e240\(%esp,%esi,8\),%xmm5,%k5\{%k7\} > > > +[ ]*[a-f0-9]+: 62 f3 56 28 c2 69 7f 7b vcmpsh > > \$0x7b,0xfe\(%ecx\),%xmm5,%k5 > > > +[ ]*[a-f0-9]+: 62 f3 56 2f c2 6a 80 7b vcmpsh \$0x7b,- > > 0x100\(%edx\),%xmm5,%k5\{%k7\} > > > #pass > > > --- a/gas/testsuite/gas/i386/evex-lig512-intel.d > > > +++ b/gas/testsuite/gas/i386/evex-lig512-intel.d > > > @@ -1536,6 +1536,12 @@ Disassembly of section .text: > > > [ ]*[a-f0-9]+: 62 f3 55 4f 0a b2 00 02 00 00 7b vrndscaless > > xmm6\{k7\},xmm5,DWORD PTR \[edx\+0x200\],0x7b > > > [ ]*[a-f0-9]+: 62 f3 55 4f 0a 72 80 7b vrndscaless > > xmm6\{k7\},xmm5,DWORD PTR \[edx-0x200\],0x7b > > > [ ]*[a-f0-9]+: 62 f3 55 4f 0a b2 fc fd ff ff 7b vrndscaless > > xmm6\{k7\},xmm5,DWORD PTR \[edx-0x204\],0x7b > > > +[ ]*[a-f0-9]+: 62 f3 56 48 c2 ec 7b vcmpsh k5,xmm5,xmm4,0x7b > > > +[ ]*[a-f0-9]+: 62 f3 56 1f c2 ec 7b vcmpsh > > k5\{k7\},xmm5,xmm4,\{sae\},0x7b > > > +[ ]*[a-f0-9]+: 62 f3 56 48 c2 29 7b vcmpsh k5,xmm5,WORD PTR > > \[ecx\],0x7b > > > +[ ]*[a-f0-9]+: 62 f3 56 4f c2 ac f4 c0 1d fe ff 7b vcmpsh > > k5\{k7\},xmm5,WORD PTR \[esp\+esi\*8-0x1e240\],0x7b > > > +[ ]*[a-f0-9]+: 62 f3 56 48 c2 69 7f 7b vcmpsh k5,xmm5,WORD PTR > > \[ecx\+0xfe\],0x7b > > > +[ ]*[a-f0-9]+: 62 f3 56 4f c2 6a 80 7b vcmpsh > > k5\{k7\},xmm5,WORD PTR \[edx-0x100\],0x7b > > > [ ]*[a-f0-9]+: 62 f1 d7 4f 58 f4 vaddsd xmm6\{k7\},xmm5,xmm4 > > > [ ]*[a-f0-9]+: 62 f1 d7 cf 58 f4 vaddsd > > xmm6\{k7\}\{z\},xmm5,xmm4 > > > [ ]*[a-f0-9]+: 62 f1 d7 1f 58 f4 vaddsd > > xmm6\{k7\},xmm5,xmm4,\{rn-sae\} > > > @@ -3063,4 +3069,10 @@ Disassembly of section .text: > > > [ ]*[a-f0-9]+: 62 f3 55 4f 0a b2 00 02 00 00 7b vrndscaless > > xmm6\{k7\},xmm5,DWORD PTR \[edx\+0x200\],0x7b > > > [ ]*[a-f0-9]+: 62 f3 55 4f 0a 72 80 7b vrndscaless > > xmm6\{k7\},xmm5,DWORD PTR \[edx-0x200\],0x7b > > > [ ]*[a-f0-9]+: 62 f3 55 4f 0a b2 fc fd ff ff 7b vrndscaless > > xmm6\{k7\},xmm5,DWORD PTR \[edx-0x204\],0x7b > > > +[ ]*[a-f0-9]+: 62 f3 56 48 c2 ec 7b vcmpsh k5,xmm5,xmm4,0x7b > > > +[ ]*[a-f0-9]+: 62 f3 56 1f c2 ec 7b vcmpsh > > k5\{k7\},xmm5,xmm4,\{sae\},0x7b > > > +[ ]*[a-f0-9]+: 62 f3 56 48 c2 29 7b vcmpsh k5,xmm5,WORD PTR > > \[ecx\],0x7b > > > +[ ]*[a-f0-9]+: 62 f3 56 4f c2 ac f4 c0 1d fe ff 7b vcmpsh > > k5\{k7\},xmm5,WORD PTR \[esp\+esi\*8-0x1e240\],0x7b > > > +[ ]*[a-f0-9]+: 62 f3 56 48 c2 69 7f 7b vcmpsh k5,xmm5,WORD PTR > > \[ecx\+0xfe\],0x7b > > > +[ ]*[a-f0-9]+: 62 f3 56 4f c2 6a 80 7b vcmpsh > > k5\{k7\},xmm5,WORD PTR \[edx-0x100\],0x7b > > > #pass > > > --- a/gas/testsuite/gas/i386/evex-lig512.d > > > +++ b/gas/testsuite/gas/i386/evex-lig512.d > > > @@ -1536,6 +1536,12 @@ Disassembly of section .text: > > > [ ]*[a-f0-9]+: 62 f3 55 4f 0a b2 00 02 00 00 7b vrndscaless > > \$0x7b,0x200\(%edx\),%xmm5,%xmm6\{%k7\} > > > [ ]*[a-f0-9]+: 62 f3 55 4f 0a 72 80 7b vrndscaless \$0x7b,- > > 0x200\(%edx\),%xmm5,%xmm6\{%k7\} > > > [ ]*[a-f0-9]+: 62 f3 55 4f 0a b2 fc fd ff ff 7b vrndscaless \$0x7b,- > > 0x204\(%edx\),%xmm5,%xmm6\{%k7\} > > > +[ ]*[a-f0-9]+: 62 f3 56 48 c2 ec 7b vcmpsh > > \$0x7b,%xmm4,%xmm5,%k5 > > > +[ ]*[a-f0-9]+: 62 f3 56 1f c2 ec 7b vcmpsh > > \$0x7b,\{sae\},%xmm4,%xmm5,%k5\{%k7\} > > > +[ ]*[a-f0-9]+: 62 f3 56 48 c2 29 7b vcmpsh > > \$0x7b,\(%ecx\),%xmm5,%k5 > > > +[ ]*[a-f0-9]+: 62 f3 56 4f c2 ac f4 c0 1d fe ff 7b vcmpsh \$0x7b,- > > 0x1e240\(%esp,%esi,8\),%xmm5,%k5\{%k7\} > > > +[ ]*[a-f0-9]+: 62 f3 56 48 c2 69 7f 7b vcmpsh > > \$0x7b,0xfe\(%ecx\),%xmm5,%k5 > > > +[ ]*[a-f0-9]+: 62 f3 56 4f c2 6a 80 7b vcmpsh \$0x7b,- > > 0x100\(%edx\),%xmm5,%k5\{%k7\} > > > [ ]*[a-f0-9]+: 62 f1 d7 4f 58 f4 > > vaddsd %xmm4,%xmm5,%xmm6\{%k7\} > > > [ ]*[a-f0-9]+: 62 f1 d7 cf 58 f4 > > vaddsd %xmm4,%xmm5,%xmm6\{%k7\}\{z\} > > > [ ]*[a-f0-9]+: 62 f1 d7 1f 58 f4 vaddsd \{rn- > > sae\},%xmm4,%xmm5,%xmm6\{%k7\} > > > @@ -3063,4 +3069,10 @@ Disassembly of section .text: > > > [ ]*[a-f0-9]+: 62 f3 55 4f 0a b2 00 02 00 00 7b vrndscaless > > \$0x7b,0x200\(%edx\),%xmm5,%xmm6\{%k7\} > > > [ ]*[a-f0-9]+: 62 f3 55 4f 0a 72 80 7b vrndscaless \$0x7b,- > > 0x200\(%edx\),%xmm5,%xmm6\{%k7\} > > > [ ]*[a-f0-9]+: 62 f3 55 4f 0a b2 fc fd ff ff 7b vrndscaless \$0x7b,- > > 0x204\(%edx\),%xmm5,%xmm6\{%k7\} > > > +[ ]*[a-f0-9]+: 62 f3 56 48 c2 ec 7b vcmpsh > > \$0x7b,%xmm4,%xmm5,%k5 > > > +[ ]*[a-f0-9]+: 62 f3 56 1f c2 ec 7b vcmpsh > > \$0x7b,\{sae\},%xmm4,%xmm5,%k5\{%k7\} > > > +[ ]*[a-f0-9]+: 62 f3 56 48 c2 29 7b vcmpsh > > \$0x7b,\(%ecx\),%xmm5,%k5 > > > +[ ]*[a-f0-9]+: 62 f3 56 4f c2 ac f4 c0 1d fe ff 7b vcmpsh \$0x7b,- > > 0x1e240\(%esp,%esi,8\),%xmm5,%k5\{%k7\} > > > +[ ]*[a-f0-9]+: 62 f3 56 48 c2 69 7f 7b vcmpsh > > \$0x7b,0xfe\(%ecx\),%xmm5,%k5 > > > +[ ]*[a-f0-9]+: 62 f3 56 4f c2 6a 80 7b vcmpsh \$0x7b,- > > 0x100\(%edx\),%xmm5,%k5\{%k7\} > > > #pass > > > --- a/opcodes/i386-opc.tbl > > > +++ b/opcodes/i386-opc.tbl > > > @@ -3739,10 +3739,10 @@ vcmpph, 0xc2, 0x > > > vcmpph, 0xc2, None, CpuAVX512_FP16, > > > > > Modrm|Masking=2|Space0F3A|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|C > > heckRe > > > gSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, > > > RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, > > RegXMM|RegYMM|RegZMM, > > > RegMask } vcmpph, 0xc2, None, CpuAVX512_FP16, > > > > > Modrm|EVex512|Masking=2|Space0F3A|VexVVVV=1|VexW0|No_bSuf|No_ > > wSuf|No_l > > > Suf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, Imm8, RegZMM, RegZMM, > > > RegMask } > > > > > > -vcmpsh, 0xf3c2, 0x, CpuAVX512_FP16, > > > > > Modrm|EVex128|Masking=2|Space0F3A|VexVVVV|VexW0|Disp8MemShift= > > 1|No_bSu > > > f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { > > > RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegMask } > > > -vcmpsh, 0xf3c2, 0x, CpuAVX512_FP16, > > > > > Modrm|EVex128|Masking=2|Space0F3A|VexVVVV|VexW0|No_bSuf|No_wS > > uf|No_lSu > > > f|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, { Imm8, RegXMM, RegXMM, > > RegMask > > > } -vcmpsh, 0xf3c2, None, CpuAVX512_FP16, > > > > > Modrm|EVex128|Masking=2|Space0F3A|VexVVVV|VexW0|Disp8MemShift= > > 1|No_bSu > > > f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, > > > RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegMask } -vcmpsh, > > 0xf3c2, > > > None, CpuAVX512_FP16, > > > > > Modrm|EVex128|Masking=2|Space0F3A|VexVVVV|VexW0|No_bSuf|No_wS > > uf|No_lSu > > > f|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, Imm8, RegXMM, RegXMM, > > RegMask > > > } > > > +vcmpsh, 0xf3c2, 0x, CpuAVX512_FP16, > > > > > +Modrm|EVexLIG|Masking=2|Space0F3A|VexVVVV|VexW0|Disp8MemShift > > =1|No_bS > > > +uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { > > > +RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegMask } > > > +vcmpsh, 0xf3c2, 0x, CpuAVX512_FP16, > > > > > +Modrm|EVexLIG|Masking=2|Space0F3A|VexVVVV|VexW0|No_bSuf|No_w > > Suf|No_lS > > > +uf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, { Imm8, RegXMM, RegXMM, > > > +RegMask } vcmpsh, 0xf3c2, None, CpuAVX512_FP16, > > > > > +Modrm|EVexLIG|Masking=2|Space0F3A|VexVVVV|VexW0|Disp8MemShift > > =1|No_bS > > > +uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, > > > +RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegMask } vcmpsh, > > 0xf3c2, > > > +None, CpuAVX512_FP16, > > > > > +Modrm|EVexLIG|Masking=2|Space0F3A|VexVVVV|VexW0|No_bSuf|No_w > > Suf|No_lS > > > +uf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, Imm8, RegXMM, RegXMM, > > > +RegMask } > > > > > > vcomish, 0x2f, None, CpuAVX512_FP16, > > > > > Modrm|EVexLIG|EVexMap5|VexW0|Disp8MemShift=1|No_bSuf|No_wSuf| > > No_lSuf|N > > > o_sSuf|No_qSuf|No_ldSuf, { RegXMM|Word|Unspecified|BaseIndex, > > RegXMM } > > > vcomish, 0x2f, None, CpuAVX512_FP16, > > > > > Modrm|EVexLIG|EVexMap5|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf| > > No_qSuf|N > > > o_ldSuf|SAE, { Imm8, RegXMM, RegXMM } > > > > > > > Lili, does it look OK? > > Hi Jan, > I confirmed it with software developer manual, it really should be LLIG. And by the way I checked all AVX512_FP16 instructions, vfpclasssh has the same issue, could you help fix them together, thanks! > Thank you, Lili. This is OK. -- H.J.