Re: [committed, PATCH] Remove Disp16|Disp32 from 64-bit direct branches

["H.J. Lu" <hjl.tools@gmail.com>]

On Mon, May 18, 2015 at 12:05 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>> On 15.05.15 at 18:52, <hjl.tools@gmail.com> wrote:
>> * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
>> Mark direct call/jmp without Disp16|Disp32 as Intel64.
>
> I had hoped that you wouldn't add back Disp32 to the AMD case, and

This is what I checked in.

> perhaps also that CpuAMD64 and CpuIntel64 would imply Cpu64 (as
> their names already suggest).

They are just a bit.  Make them to implement Cpu64 means adding more
codes to x86 assembler without any benefit.  If you can share with me
what you have in mind, I will see what I can do.

-- 
H.J.
----
* i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
* i386-init.h: Regenerated.
---
 opcodes/ChangeLog    | 5 +++++
 opcodes/i386-opc.tbl | 4 ++--
 opcodes/i386-tbl.h   | 4 ++--
 3 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index d3f914c..ef05d2d 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2015-05-18  H.J. Lu  <hongjiu.lu@intel.com>
+
+ * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
+ * i386-init.h: Regenerated.
+
 2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>

  PR binutis/18386
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 56eddbf..42dcb56 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -319,7 +319,7 @@ shrd, 2, 0xfad, None, 2, Cpu386,
Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, {

 // Control transfer instructions.
 call, 1, 0xe8, None, 1, CpuNo64,
JumpDword|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, {
Disp16|Disp32 }
-call, 1, 0xe8, None, 1, Cpu64|CpuAMD64,
JumpDword|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk,
{ Disp16|Disp32|Disp32S }
+call, 1, 0xe8, None, 1, Cpu64|CpuAMD64,
JumpDword|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk,
{ Disp16|Disp32S }
 call, 1, 0xe8, None, 1, Cpu64|CpuIntel64,
JumpDword|DefaultSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk,
{ Disp32S }
 call, 1, 0xff, 0x2, 1, CpuNo64,
Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, {
Reg16|Reg32|Word|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|JumpAbsolute
}
 call, 1, 0xff, 0x2, 1, Cpu64,
Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk,
{ Reg16|Reg64|Word|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S|JumpAbsolute
}
@@ -331,7 +331,7 @@ lcall, 2, 0x9a, None, 1, CpuNo64,
JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|N
 lcall, 1, 0xff, 0x3, 1, 0,
Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, {
Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute }

 jmp, 1, 0xeb, None, 1, CpuNo64,
Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, {
Disp8|Disp16|Disp32|Disp32S }
-jmp, 1, 0xeb, None, 1, Cpu64|CpuAMD64,
Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, {
Disp8|Disp16|Disp32|Disp32S }
+jmp, 1, 0xeb, None, 1, Cpu64|CpuAMD64,
Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, {
Disp8|Disp16|Disp32S }
 jmp, 1, 0xeb, None, 1, Cpu64|CpuIntel64,
Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, {
Disp8|Disp32S }
 jmp, 1, 0xff, 0x4, 1, CpuNo64,
Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, {
Reg16|Reg32|Word|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|JumpAbsolute
}
 jmp, 1, 0xff, 0x4, 1, Cpu64,
Modrm|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk, {
Reg16|Reg64|Word|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S|JumpAbsolute
}