From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qv1-xf36.google.com (mail-qv1-xf36.google.com [IPv6:2607:f8b0:4864:20::f36]) by sourceware.org (Postfix) with ESMTPS id A2CFE3858C74 for ; Thu, 11 Aug 2022 17:49:25 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org A2CFE3858C74 Received: by mail-qv1-xf36.google.com with SMTP id d10so8285582qvn.8 for ; Thu, 11 Aug 2022 10:49:25 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc; bh=DAaEORjofSemQNBUSj7It3YGfHKUxtkRewRIpVizivs=; b=NOClRfY3Il2sTwpDdYX+iCa5XnaQ3Dc7/TueJQD/lVZpO4sd2evrdpAJSkozCOPHPS oYdJtg8/PlsOFzTgRJGuoZcJC1YaIzXL7XWczBgY/g7jxruAL0CtU2bQDIOM9Ce+Jwvw vpEHb+PqtveyNoVHAnPI4Yfa92ZskzedD6x2pS9JRj0LrCiFOpKrvOc6VmxdTpY5bh1r 9zeyky3RenXW8uPWIJWe/bhT9HN1Mztpf960wyeqo21zBkiq4gq04wS/E0lF+IKU7Fp0 uqyaXk/lc63RdvvEjl1opA3+jaHnbeUSWUwSiYko+4cqO8uIN5ZcFOayQksJ0OLa+kZv kmRA== X-Gm-Message-State: ACgBeo31qOO6vaD2qGfN0z+2GMFJ8ByS9azG0LiJ3Ko93ELTkhWOrqH+ oEZe5Yh5wJ7hRm9vajvCeWDwAFVPOy3IzjaAdiPP6k0Z X-Google-Smtp-Source: AA6agR7QVJsJuIqCGT2vKYYWWlw9FKNtd7jiiQxSiyMyPnjRUQSYlSx+qHgmqrcrGKsB/uGtoIuISAT2ENjdOnWuOUc= X-Received: by 2002:a05:6214:d82:b0:477:3d7c:1081 with SMTP id e2-20020a0562140d8200b004773d7c1081mr275113qve.28.1660240164594; Thu, 11 Aug 2022 10:49:24 -0700 (PDT) MIME-Version: 1.0 References: <765b478b-4404-4523-915f-9ea8a011e0b0@suse.com> In-Reply-To: <765b478b-4404-4523-915f-9ea8a011e0b0@suse.com> From: "H.J. Lu" Date: Thu, 11 Aug 2022 10:48:48 -0700 Message-ID: Subject: Re: [PATCH 11/12] x86: template-ize certain vector conversion insns To: Jan Beulich Cc: Binutils Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-3018.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 11 Aug 2022 17:49:30 -0000 On Fri, Aug 5, 2022 at 5:28 AM Jan Beulich wrote: > > Many of the vector conversion insns come with X/Y/Z suffixed forms, for > disambiguation purposes in AT&T syntax. All of these gorups follow > certain patterns. Introduce "xy" and "xyz" templates to reduce > redundancy. > > To facilitate using a uniform name for both AVX and AVX512, further > introduce a means to purge a previously defined template: A standalone > will be recognized to have this effect. > > Note that in the course of the conversion VFPCLASSPH is properly split > to separate AT&T and Intel syntax forms, matching VFPCLASSP{S,D} and > yielding the intended "ambiguous operand size" diagnostic in Intel mode. > --- > For the template purging syntax I was considering an XML-like as > an alternative. Thoughts? > > --- a/opcodes/i386-gen.c > +++ b/opcodes/i386-gen.c > @@ -822,13 +822,13 @@ struct template_param { > }; > > struct template { > - const struct template *next; > + struct template *next; > const char *name; > const struct template_instance *instances; > const struct template_param *params; > }; > > -static const struct template *templates; > +static struct template *templates; > > static int > compare (const void *x, const void *y) > @@ -1509,18 +1509,40 @@ static void > parse_template (char *buf, int lineno) > { > char sep, *end, *name; > - struct template *tmpl =3D xmalloc (sizeof (*tmpl)); > + struct template *tmpl; > struct template_instance *last_inst =3D NULL; > > buf =3D remove_leading_whitespaces (buf + 1); > end =3D strchr (buf, ':'); > if (end =3D=3D NULL) > - fail ("%s: %d: missing ':'\n", filename, lineno); > + { > + struct template *prev =3D NULL; > + > + end =3D strchr (buf, '>'); > + if (end =3D=3D NULL) > + fail ("%s: %d: missing ':' or '>'\n", filename, lineno); > + if (*remove_leading_whitespaces (end + 1)) > + fail ("%s: %d: malformed template purge\n", filename, lineno); > + *end =3D '\0'; > + remove_trailing_whitespaces (buf); > + /* Don't bother freeing the various structures. */ > + for (tmpl =3D templates; tmpl !=3D NULL; tmpl =3D (prev =3D tmpl)-= >next) > + if (!strcmp (buf, tmpl->name)) > + break; > + if (tmpl =3D=3D NULL) > + fail ("%s: %d: no template '%s'\n", filename, lineno, buf); > + if (prev) > + prev->next =3D tmpl->next; > + else > + templates =3D tmpl->next; > + return; > + } > *end++ =3D '\0'; > remove_trailing_whitespaces (buf); > > if (*buf =3D=3D '\0') > fail ("%s: %d: missing template identifier\n", filename, lineno); > + tmpl =3D xmalloc (sizeof (*tmpl)); > tmpl->name =3D xstrdup (buf); > > tmpl->params =3D NULL; > --- a/opcodes/i386-opc.tbl > +++ b/opcodes/i386-opc.tbl > @@ -1462,6 +1462,12 @@ gf2p8mulb, 0x660f38cf, None, nge_uq:19:, ngt_uq:1a:, false_os:1b:C, neq_os:1c:C, ge_oq:1d:, gt_oq= :1e:, + > true_us:1f:C> > > + + $i:Vex:IntelSyntax:RegXMM|RegYMM|Unspecified|BaseIndex, + > + $a:Vex:ATTSyntax:RegXMM|RegYMM, + > + x:Vex128:ATTSyntax:RegXMM|Unspecified|BaseIndex, + > + y:Vex256:ATTSyntax:RegYMM|Unspecified|BaseIndex> > + > vaddp, 0x58, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG= |CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecifi= ed|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } > vadds, 0x58, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|Vex= WIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { |Unspecifi= ed|BaseIndex|RegXMM, RegXMM, RegXMM } > vaddsubpd, 0x66d0, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|Ch= eckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|= BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } > @@ -1481,14 +1487,8 @@ vcomis, 0x2f, None, CpuAVX, > vcvtdq2pd, 0xf3e6, None, CpuAVX, Modrm|Vex128|Space0F|VexWIG|No_bSuf|No_= wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex= , RegXMM } > vcvtdq2pd, 0xf3e6, None, CpuAVX, Modrm|Vex256|Space0F|VexWIG|No_bSuf|No_= wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegY= MM } > vcvtdq2ps, 0x5b, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|No_= bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegX= MM|RegYMM, RegXMM|RegYMM } > -vcvtpd2dq, 0xf2e6, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|No_bSuf|No_wSu= f|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { RegXMM|RegYMM|Unspecified= |BaseIndex, RegXMM } > -vcvtpd2dq, 0xf2e6, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|No_bSuf|No_wSu= f|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|RegYMM, RegXMM } > -vcvtpd2dqx, 0xf2e6, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|No_bSuf|No_wS= uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Unspecified|BaseIndex|RegX= MM, RegXMM } > -vcvtpd2dqy, 0xf2e6, None, CpuAVX, Modrm|Vex=3D2|Space0F|VexWIG|No_bSuf|N= o_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Unspecified|BaseIndex|= RegYMM, RegXMM } > -vcvtpd2ps, 0x665a, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|No_bSuf|No_wSu= f|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { RegXMM|RegYMM|Unspecified= |BaseIndex, RegXMM } > -vcvtpd2ps, 0x665a, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|No_bSuf|No_wSu= f|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|RegYMM, RegXMM } > -vcvtpd2psx, 0x665a, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|No_bSuf|No_wS= uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Unspecified|BaseIndex|RegX= MM, RegXMM } > -vcvtpd2psy, 0x665a, None, CpuAVX, Modrm|Vex=3D2|Space0F|VexWIG|No_bSuf|N= o_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Unspecified|BaseIndex|= RegYMM, RegXMM } > +vcvtpd2dq, 0xf2e6, None, CpuAVX, Modrm||Space0F|VexWIG|No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|, { , RegXMM= } > +vcvtpd2ps, 0x665a, None, CpuAVX, Modrm||Space0F|VexWIG|No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|, { , RegXMM= } > vcvtps2dq, 0x665b, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|N= o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|Re= gXMM|RegYMM, RegXMM|RegYMM } > vcvtps2pd, 0x5a, None, CpuAVX, Modrm|Vex128|Space0F|VexWIG|No_bSuf|No_wS= uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, = RegXMM } > vcvtps2pd, 0x5a, None, CpuAVX, Modrm|Vex256|Space0F|VexWIG|No_bSuf|No_wS= uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegYMM= } > @@ -1498,10 +1498,7 @@ vcvtsi2s, 0x2a, None, CpuAV > vcvtsi2s, 0x2a, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|= No_bSuf|No_wSuf|No_sSuf|No_ldSuf|IntelSyntax, { Reg32|Reg64|Unspecified|Bas= eIndex, RegXMM, RegXMM } > vcvtss2sd, 0xf35a, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexVVVV|VexWIG|No= _bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseInd= ex|RegXMM, RegXMM, RegXMM } > vcvtss2si, 0xf32d, None, CpuAVX, Modrm|Vex=3D3|Space0F|No_bSuf|No_wSuf|N= o_sSuf|No_ldSuf|ToQword, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 = } > -vcvttpd2dq, 0x66e6, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|No_bSuf|No_wS= uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { RegXMM|RegYMM|Unspecifie= d|BaseIndex, RegXMM } > -vcvttpd2dq, 0x66e6, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|No_bSuf|No_wS= uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|RegYMM, RegXMM } > -vcvttpd2dqx, 0x66e6, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|No_bSuf|No_w= Suf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTsyntax, { Unspecified|BaseIndex|Reg= XMM, RegXMM } > -vcvttpd2dqy, 0x66e6, None, CpuAVX, Modrm|Vex=3D2|Space0F|VexWIG|No_bSuf|= No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTsyntax, { Unspecified|BaseIndex= |RegYMM, RegXMM } > +vcvttpd2dq, 0x66e6, None, CpuAVX, Modrm||Space0F|VexWIG|No_b= Suf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|, { , RegXM= M } > vcvttps2dq, 0xf35b, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|No_bSuf|No_wS= uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM,= RegXMM|RegYMM } > vcvttsd2si, 0xf22c, None, CpuAVX, Modrm|Vex=3D3|Space0F|IgnoreSize|No_bS= uf|No_wSuf|No_sSuf|No_ldSuf|ToDword, { Qword|Unspecified|BaseIndex|RegXMM, = Reg32|Reg64 } > vcvttss2si, 0xf32c, None, CpuAVX, Modrm|Vex=3D3|Space0F|No_bSuf|No_wSuf|= No_sSuf|No_ldSuf|ToQword, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64= } > @@ -1699,6 +1696,8 @@ vxorp, 0x57, None, CpuAVX, > vzeroall, 0x77, None, CpuAVX, Vex=3D2|Space0F|VexWIG|No_bSuf|No_wSuf|No_= lSuf|No_sSuf|No_qSuf|No_ldSuf, {} > vzeroupper, 0x77, None, CpuAVX, Vex|Space0F|VexWIG|No_bSuf|No_wSuf|No_lS= uf|No_sSuf|No_qSuf|No_ldSuf, {} > > + > + > // 256bit integer AVX2 instructions. > > vpmovsxbd, 0x6621, None, CpuAVX2, Modrm|Vex=3D2|Space0F38|VexWIG|No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Re= gXMM, RegYMM } > @@ -2044,6 +2043,13 @@ vpclmulhqhqdq, 0x6644, 0x11, CpuVPCLMULQ > d:CpuAVX512F:CpuAVX512DQ:66:f2:66:Space0F:Space0F38:1:VexW1:Qword, + > h:CpuAVX512_FP16:CpuAVX512_FP16::f3::EVexMap5:EVexMap6:0:VexW0:Word> > > + + $z::EVex512|Disp8MemShift=3D6:StaticRounding|SAE:SAE:RegZMM|Unspecif= ied|BaseIndex:RegYMM, + > + $i:CpuAVX512VL:Disp8ShiftVL|IntelSyntax:::RegXMM|RegYMM|Unspecified|= BaseIndex:RegXMM, + > + $a:CpuAVX512VL:Disp8ShiftVL|ATTSyntax:::RegXMM|RegYMM|BaseIndex:RegX= MM, + > + x:CpuAVX512VL:EVex128|Disp8MemShift=3D4|ATTSyntax:::RegXMM|Unspecifi= ed|BaseIndex:RegXMM, + > + y:CpuAVX512VL:EVex256|Disp8MemShift=3D5|ATTSyntax:::RegYMM|Unspecifi= ed|BaseIndex:RegXMM> > + > kand, 0x41, None, , Modrm|Vex256|Space0F|VexVVVV|V= exW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, = RegMask } > kandn, 0x42, None, , Modrm|Vex256|Space0F|VexVVVV|= VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask,= RegMask } > kor, 0x45, None, , Modrm|Vex256|Space0F|VexVVVV|Ve= xW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, R= egMask } > @@ -2135,11 +2141,11 @@ vcvtudq2pd, 0xF37A, None, CpuAVX512F, Mo > vcvtdq2ps, 0x5B, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexW0|Broad= cast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_l= dSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM } > vcvtps2udq, 0x79, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexW0|Broa= dcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_= ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseInde= x, RegXMM|RegYMM|RegZMM } > > -vcvtpd2dq, 0xF2E6, None, CpuAVX512F, Modrm|EVex512|Masking=3D3|Space0F|V= exW1|Broadcast|Disp8MemShift=3D6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No= _ldSuf|StaticRounding|SAE, { RegZMM|Qword|Unspecified|BaseIndex, RegYMM } > +vcvtpd2dq, 0xf2e6, None, CpuAVX512F|, Modrm||Masking= =3D3|Space0F|VexW1|Broadcast|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS= uf|, { |Qword, } > > -vcvtpd2ps, 0x665A, None, CpuAVX512F, Modrm|EVex512|Masking=3D3|Space0F|V= exW1|Broadcast|Disp8MemShift=3D6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No= _ldSuf|StaticRounding|SAE, { RegZMM|Qword|Unspecified|BaseIndex, RegYMM } > +vcvtpd2ps, 0x665a, None, CpuAVX512F|, Modrm||Masking= =3D3|Space0F|VexW1|Broadcast|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS= uf|, { |Qword, } > > -vcvtpd2udq, 0x79, None, CpuAVX512F, Modrm|EVex512|Masking=3D3|Space0F|Ve= xW1|Broadcast|Disp8MemShift=3D6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_= ldSuf|StaticRounding|SAE, { RegZMM|Qword|Unspecified|BaseIndex, RegYMM } > +vcvtpd2udq, 0x79, None, CpuAVX512F|, Modrm||Masking= =3D3|Space0F|VexW1|Broadcast|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS= uf|, { |Qword, } > > vcvtph2ps, 0x6613, None, CpuAVX512F, Modrm|EVex512|Masking=3D3|Space0F38= |VexW0|Disp8MemShift=3D5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|S= AE, { RegYMM|Unspecified|BaseIndex, RegZMM } > > @@ -2173,8 +2179,8 @@ vcvtss2sd, 0xF35A, None, CpuAVX512F, Mod > vcvtss2si, 0xF32D, None, CpuAVX512F, Modrm|EVexLIG|Space0F|Disp8MemShift= =3D2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToQword|StaticRounding|SAE, { RegXMM|= Dword|Unspecified|BaseIndex, Reg32|Reg64 } > vcvtss2usi, 0xF379, None, CpuAVX512F, Modrm|EVexLIG|Space0F|Disp8MemShif= t=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ToQword|StaticRoundi= ng|SAE, { RegXMM|Dword|Unspecified|BaseIndex, Reg32|Reg64 } > > -vcvttpd2dq, 0x66E6, None, CpuAVX512F, Modrm|EVex512|Masking=3D3|Space0F|= VexW1|Broadcast|Disp8MemShift=3D6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N= o_ldSuf|SAE, { RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegYMM } > -vcvttpd2udq, 0x78, None, CpuAVX512F, Modrm|EVex512|Masking=3D3|Space0F|V= exW1|Broadcast|Disp8MemShift=3D6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No= _ldSuf|SAE, { RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegYMM } > +vcvttpd2dq, 0x66e6, None, CpuAVX512F|, Modrm||Maskin= g=3D3|Space0F|VexW1|Broadcast|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ld= Suf|, { |Qword, } > +vcvttpd2udq, 0x78, None, CpuAVX512F|, Modrm||Masking= =3D3|Space0F|VexW1|Broadcast|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS= uf|, { |Qword, } > > vcvttps2dq, 0xF35B, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexW0|Br= oadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N= o_ldSuf|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|Reg= YMM|RegZMM } > vcvttps2udq, 0x78, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexW0|Bro= adcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No= _ldSuf|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegY= MM|RegZMM } > @@ -2500,21 +2506,6 @@ vcvtdq2pd, 0xF3E6, None, CpuAVX512F|CpuA > vcvtudq2pd, 0xF37A, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking= =3D3|Space0F|VexW0|Broadcast|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_s= Suf|No_qSuf|No_ldSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } > vcvtudq2pd, 0xF37A, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking= =3D3|Space0F|VexW0|Broadcast|Disp8MemShift=3D4|No_bSuf|No_wSuf|No_lSuf|No_s= Suf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } > > -vcvtpd2dq, 0xF2E6, None, CpuAVX512F|CpuAVX512VL, Modrm|Masking=3D3|Space= 0F|VexW=3D2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|= No_ldSuf|IntelSyntax, { RegXMM|RegYMM|Qword|Unspecified|BaseIndex, RegXMM } > -vcvtpd2dq, 0xF2E6, None, CpuAVX512F|CpuAVX512VL, Modrm|Masking=3D3|Space= 0F|VexW=3D2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|= No_ldSuf|ATTSyntax, { RegXMM|RegYMM|Qword|BaseIndex, RegXMM } > -vcvtpd2dqx, 0xF2E6, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D2|Masking= =3D3|Space0F|VexW=3D2|Broadcast|Disp8MemShift=3D4|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|Qword|Unspecified|BaseIndex, Re= gXMM } > -vcvtpd2dqy, 0xF2E6, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D3|Masking= =3D3|Space0F|VexW=3D2|Broadcast|Disp8MemShift=3D5|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegYMM|Qword|Unspecified|BaseIndex, Re= gXMM } > - > -vcvtpd2ps, 0x665A, None, CpuAVX512F|CpuAVX512VL, Modrm|Masking=3D3|Space= 0F|VexW=3D2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|= No_ldSuf|IntelSyntax, { RegXMM|RegYMM|Qword|Unspecified|BaseIndex, RegXMM } > -vcvtpd2ps, 0x665A, None, CpuAVX512F|CpuAVX512VL, Modrm|Masking=3D3|Space= 0F|VexW=3D2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|= No_ldSuf|ATTSyntax, { RegXMM|RegYMM|Qword|BaseIndex, RegXMM } > -vcvtpd2psx, 0x665A, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D2|Masking= =3D3|Space0F|VexW=3D2|Broadcast|Disp8MemShift=3D4|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|Qword|Unspecified|BaseIndex, Re= gXMM } > -vcvtpd2psy, 0x665A, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D3|Masking= =3D3|Space0F|VexW=3D2|Broadcast|Disp8MemShift=3D5|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegYMM|Qword|Unspecified|BaseIndex, Re= gXMM } > - > -vcvtpd2udq, 0x79, None, CpuAVX512F|CpuAVX512VL, Modrm|Masking=3D3|Space0= F|VexW=3D2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N= o_ldSuf|IntelSyntax, { RegXMM|RegYMM|Qword|Unspecified|BaseIndex, RegXMM } > -vcvtpd2udq, 0x79, None, CpuAVX512F|CpuAVX512VL, Modrm|Masking=3D3|Space0= F|VexW=3D2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N= o_ldSuf|ATTSyntax, { RegXMM|RegYMM|Qword|BaseIndex, RegXMM } > -vcvtpd2udqx, 0x79, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D2|Masking= =3D3|Space0F|VexW=3D2|Broadcast|Disp8MemShift=3D4|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|Qword|Unspecified|BaseIndex, Re= gXMM } > -vcvtpd2udqy, 0x79, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D3|Masking= =3D3|Space0F|VexW=3D2|Broadcast|Disp8MemShift=3D5|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegYMM|Qword|Unspecified|BaseIndex, Re= gXMM } > - > vcvtph2ps, 0x6613, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D2|Masking= =3D3|Space0F38|VexW0|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_q= Suf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } > vcvtph2ps, 0x6613, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D3|Masking= =3D3|Space0F38|VexW=3D1|Disp8MemShift=3D4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N= o_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } > > @@ -2524,16 +2515,6 @@ vcvtps2pd, 0x5A, None, CpuAVX512F|CpuAVX > vcvtps2ph, 0x661D, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|MaskingMo= rZ|Space0F3A|VexW0|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu= f|No_ldSuf, { Imm8, RegXMM, RegXMM|Qword|Unspecified|BaseIndex } > vcvtps2ph, 0x661D, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|MaskingMo= rZ|Space0F3A|VexW0|Disp8MemShift=3D4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu= f|No_ldSuf, { Imm8, RegYMM, RegXMM|Unspecified|BaseIndex } > > -vcvttpd2dq, 0x66E6, None, CpuAVX512F|CpuAVX512VL, Modrm|Masking=3D3|Spac= e0F|VexW=3D2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf= |No_ldSuf|IntelSyntax, { RegXMM|RegYMM|Unspecified|Qword|BaseIndex, RegXMM = } > -vcvttpd2dq, 0x66E6, None, CpuAVX512F|CpuAVX512VL, Modrm|Masking=3D3|Spac= e0F|VexW=3D2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf= |No_ldSuf|ATTSyntax, { RegXMM|RegYMM|Qword|BaseIndex, RegXMM } > -vcvttpd2dqx, 0x66E6, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D2|Maskin= g=3D3|Space0F|VexW=3D2|Broadcast|Disp8MemShift=3D4|No_bSuf|No_wSuf|No_lSuf|= No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|Qword|Unspecified|BaseIndex, R= egXMM } > -vcvttpd2dqy, 0x66E6, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D3|Maskin= g=3D3|Space0F|VexW=3D2|Broadcast|Disp8MemShift=3D5|No_bSuf|No_wSuf|No_lSuf|= No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegYMM|Qword|Unspecified|BaseIndex, R= egXMM } > - > -vcvttpd2udq, 0x78, None, CpuAVX512F|CpuAVX512VL, Modrm|Masking=3D3|Space= 0F|VexW=3D2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|= No_ldSuf|IntelSyntax, { RegXMM|RegYMM|Qword|Unspecified|BaseIndex, RegXMM } > -vcvttpd2udq, 0x78, None, CpuAVX512F|CpuAVX512VL, Modrm|Masking=3D3|Space= 0F|VexW=3D2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|= No_ldSuf|ATTSyntax, { RegXMM|RegYMM|Qword|BaseIndex, RegXMM } > -vcvttpd2udqx, 0x78, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D2|Masking= =3D3|Space0F|VexW=3D2|Broadcast|Disp8MemShift=3D4|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|Qword|Unspecified|BaseIndex, Re= gXMM } > -vcvttpd2udqy, 0x78, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D3|Masking= =3D3|Space0F|VexW=3D2|Broadcast|Disp8MemShift=3D5|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegYMM|Qword|Unspecified|BaseIndex, Re= gXMM } > - > vmovddup, 0xF212, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D2|Masking= =3D3|Space0F|VexW1|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu= f|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } > > vpmovdb, 0xF331, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D2|MaskingMor= Z|Space0F38|VexW0|Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf= |No_ldSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } > @@ -2731,6 +2712,13 @@ vptestnm, 0xf326, None, CpuAVX512BW, > > // AVX512DQ instructions. > > + + $i::Disp8ShiftVL|IntelSyntax:StaticRounding|SAE::RegXMM|RegYMM|RegZM= M|Unspecified|BaseIndex, + > + $a::Disp8ShiftVL|ATTSyntax:StaticRounding|SAE::RegXMM|RegYMM|RegZMM|= BaseIndex, + > + z::EVex512|Disp8MemShift=3D6:StaticRounding|SAE:ATTSyntax:RegZMM|Uns= pecified|BaseIndex, + > + x:CpuAVX512VL:EVex128|Disp8MemShift=3D4::ATTSyntax:RegXMM|Unspecifie= d|BaseIndex, + > + y:CpuAVX512VL:EVex256|Disp8MemShift=3D5::ATTSyntax:RegYMM|Unspecifie= d|BaseIndex> > + > kadd, 0x4A, None, CpuAVX512DQ, Modrm|Vex256|Space0F|VexVVVV= |VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask= , RegMask } > ktest, 0x99, None, CpuAVX512DQ, Modrm|Vex128|Space0F|VexW0|= No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask } > > @@ -2760,11 +2748,7 @@ vcvtps2uqq, 0x6679, None, CpuAVX512DQ|Cp > vcvtqq2pd, 0xF3E6, None, CpuAVX512DQ, Modrm|Masking=3D3|Space0F|VexW1|Br= oadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N= o_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIn= dex, RegXMM|RegYMM|RegZMM } > vcvtuqq2pd, 0xF37A, None, CpuAVX512DQ, Modrm|Masking=3D3|Space0F|VexW1|B= roadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|= No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseI= ndex, RegXMM|RegYMM|RegZMM } > > -vcvtqq2ps, 0x5B, None, CpuAVX512DQ, Modrm|EVex512|Masking=3D3|Space0F|Ve= xW1|Broadcast|Disp8MemShift=3D6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_= ldSuf|StaticRounding|SAE, { RegZMM|Qword|Unspecified|BaseIndex, RegYMM } > -vcvtqq2ps, 0x5B, None, CpuAVX512DQ|CpuAVX512VL, Modrm|Masking=3D3|Space0= F|VexW=3D2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N= o_ldSuf|IntelSyntax, { RegXMM|RegYMM|Qword|Unspecified|BaseIndex, RegXMM } > -vcvtqq2ps, 0x5B, None, CpuAVX512DQ|CpuAVX512VL, Modrm|Masking=3D3|Space0= F|VexW=3D2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N= o_ldSuf|ATTSyntax, { RegXMM|RegYMM|Qword|BaseIndex, RegXMM } > -vcvtqq2psx, 0x5B, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex=3D2|Masking= =3D3|Space0F|VexW=3D2|Broadcast|Disp8MemShift=3D4|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|Qword|Unspecified|BaseIndex, Re= gXMM } > -vcvtqq2psy, 0x5B, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex=3D3|Masking= =3D3|Space0F|VexW=3D2|Broadcast|Disp8MemShift=3D5|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegYMM|Qword|Unspecified|BaseIndex, Re= gXMM } > +vcvtqq2ps, 0x5b, None, CpuAVX512DQ|, Modrm||Masking= =3D3|Space0F|VexW1|Broadcast|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS= uf|, { |Qword, } > > vcvttpd2qq, 0x667A, None, CpuAVX512DQ, Modrm|Masking=3D3|Space0F|VexW1|B= roadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|= No_ldSuf|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|Re= gYMM|RegZMM } > vcvttpd2uqq, 0x6678, None, CpuAVX512DQ, Modrm|Masking=3D3|Space0F|VexW1|= Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf= |No_ldSuf|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|R= egYMM|RegZMM } > @@ -2776,11 +2760,7 @@ vcvttps2uqq, 0x6678, None, CpuAVX512DQ, > vcvttps2uqq, 0x6678, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex128|Maskin= g=3D3|Space0F|VexW0|Broadcast|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_= sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } > vcvttps2uqq, 0x6678, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex256|Maskin= g=3D3|Space0F|VexW0|Broadcast|Disp8MemShift=3D4|No_bSuf|No_wSuf|No_lSuf|No_= sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } > > -vcvtuqq2ps, 0xF27A, None, CpuAVX512DQ, Modrm|EVex512|Masking=3D3|Space0F= |VexW1|Broadcast|Disp8MemShift=3D6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|= No_ldSuf|StaticRounding|SAE, { RegZMM|Qword|Unspecified|BaseIndex, RegYMM } > -vcvtuqq2ps, 0xF27A, None, CpuAVX512DQ|CpuAVX512VL, Modrm|Masking=3D3|Spa= ce0F|VexW=3D2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu= f|No_ldSuf|IntelSyntax, { RegXMM|RegYMM|Qword|Unspecified|BaseIndex, RegXMM= } > -vcvtuqq2ps, 0xF27A, None, CpuAVX512DQ|CpuAVX512VL, Modrm|Masking=3D3|Spa= ce0F|VexW=3D2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu= f|No_ldSuf|ATTSyntax, { RegXMM|RegYMM|Qword|BaseIndex, RegXMM } > -vcvtuqq2psx, 0xF27A, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex=3D2|Maski= ng=3D3|Space0F|VexW=3D2|Broadcast|Disp8MemShift=3D4|No_bSuf|No_wSuf|No_lSuf= |No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|Qword|Unspecified|BaseIndex, = RegXMM } > -vcvtuqq2psy, 0xF27A, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex=3D3|Maski= ng=3D3|Space0F|VexW=3D2|Broadcast|Disp8MemShift=3D5|No_bSuf|No_wSuf|No_lSuf= |No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegYMM|Qword|Unspecified|BaseIndex, = RegXMM } > +vcvtuqq2ps, 0xf27a, None, CpuAVX512DQ|, Modrm||Maski= ng=3D3|Space0F|VexW1|Broadcast|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_l= dSuf|, { |Qword, } > > vextractf32x8, 0x661B, None, CpuAVX512DQ, Modrm|EVex=3D1|MaskingMorZ|Spa= ce0F3A|VexW=3D1|Disp8MemShift=3D5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N= o_ldSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } > vextracti32x8, 0x663B, None, CpuAVX512DQ, Modrm|EVex=3D1|MaskingMorZ|Spa= ce0F3A|VexW=3D1|Disp8MemShift=3D5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N= o_ldSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } > @@ -2795,8 +2775,8 @@ vextracti64x2, 0x6639, None, CpuAVX512DQ > vinsertf64x2, 0x6618, None, CpuAVX512DQ, Modrm|Masking=3D3|Space0F3A|Vex= VVVV=3D1|VexW=3D2|Disp8MemShift=3D4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No= _sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM= , RegYMM|RegZMM } > vinserti64x2, 0x6638, None, CpuAVX512DQ, Modrm|Masking=3D3|Space0F3A|Vex= VVVV=3D1|VexW=3D2|Disp8MemShift=3D4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No= _sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM= , RegYMM|RegZMM } > > -vfpclassp, 0x6666, None, CpuAVX512DQ, Modrm|Masking=3D2|Space0F3A||Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_l= dSuf|ATTSyntax, { Imm8, RegXMM|RegYMM|RegZMM||BaseIndex, RegMask } > vfpclassp, 0x6666, None, CpuAVX512DQ, Modrm|Masking=3D2|Space0F3A||Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_l= dSuf|IntelSyntax, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIn= dex, RegMask } > +vfpclassp, 0x6666, None, CpuAVX512DQ, Modrm|Masking=3D2|Space0F3A||Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_l= dSuf|ATTSyntax, { Imm8, RegXMM|RegYMM|RegZMM||BaseIndex, RegMask } > vfpclasspz, 0x6666, None, CpuAVX512DQ, Modrm|EVex512|Masking=3D2|Spa= ce0F3A||Broadcast|Disp8MemShift=3D6|No_bSuf|No_wSuf|No_lSuf|No_sSu= f|No_qSuf|No_ldSuf, { Imm8, RegZMM||Unspecified|BaseIndex, RegMask= } > vfpclasspx, 0x6666, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex128|Mas= king=3D2|Space0F3A||Broadcast|Disp8MemShift=3D4|No_bSuf|No_wSuf|No= _lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM||Unspecified|BaseIn= dex, RegMask } > vfpclasspy, 0x6666, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex256|Mas= king=3D2|Space0F3A||Broadcast|Disp8MemShift=3D5|No_bSuf|No_wSuf|No= _lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM||Unspecified|BaseIn= dex, RegMask } > @@ -3048,11 +3028,7 @@ movdir64b, 0x660f38f8, None, CpuMOVDIR64 > > vcvtne2ps2bf16, 0xf272, None, CpuAVX512_BF16, Modrm|Space0F38|VexVVVV|Ma= sking=3D3|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf= |No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseInd= ex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > > -vcvtneps2bf16, 0xf372, None, CpuAVX512_BF16, Modrm|Space0F38|EVex512|Mas= king=3D3|VexW0|Broadcast|Disp8MemShift=3D6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|= No_qSuf|No_ldSuf, { RegZMM|Dword|Unspecified|BaseIndex, RegYMM } > -vcvtneps2bf16, 0xf372, None, CpuAVX512_BF16|CpuAVX512VL, Modrm|Space0F38= |Masking=3D3|VexW0|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N= o_qSuf|No_ldSuf|IntelSyntax, { RegXMM|RegYMM|Dword|Unspecified|BaseIndex, R= egXMM } > -vcvtneps2bf16, 0xf372, None, CpuAVX512_BF16|CpuAVX512VL, Modrm|Space0F38= |Masking=3D3|VexW0|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N= o_qSuf|No_ldSuf|ATTSyntax, { RegXMM|RegYMM|Dword|BaseIndex, RegXMM } > -vcvtneps2bf16x, 0xf372, None, CpuAVX512_BF16|CpuAVX512VL, Modrm|Space0F3= 8|EVex128|Masking=3D3|VexW0|Broadcast|Disp8MemShift=3D4|No_bSuf|No_wSuf|No_= lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|Dword|Unspecified|BaseInd= ex, RegXMM } > -vcvtneps2bf16y, 0xf372, None, CpuAVX512_BF16|CpuAVX512VL, Modrm|Space0F3= 8|EVex256|Masking=3D3|VexW0|Broadcast|Disp8MemShift=3D5|No_bSuf|No_wSuf|No_= lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegYMM|Dword|Unspecified|BaseInd= ex, RegXMM } > +vcvtneps2bf16, 0xf372, None, CpuAVX512_BF16|, Modrm|Space0F38= ||Masking=3D3|VexW0|Broadcast|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_q= Suf|No_ldSuf, { |Dword, } > > vdpbf16ps, 0xf352, None, CpuAVX512_BF16, Modrm|Space0F38|VexVVVV|Masking= =3D3|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_s= Suf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, R= egXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > > @@ -3195,41 +3171,15 @@ vcmpph, 0xc2, None, CpuAVX512_FP16, Modr > vcmpsh, 0xf3c2, 0x, CpuAVX512_FP16, Modrm|EVexLI= G|Masking=3D2|Space0F3A|VexVVVV|VexW0|Disp8MemShift=3D1|No_bSuf|No_wSuf|No_= lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, { RegXMM|Word|Unspecified|BaseInd= ex, RegXMM, RegMask } > vcmpsh, 0xf3c2, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3D2|Space0F3= A|VexVVVV|VexW0|Disp8MemShift=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N= o_ldSuf|SAE, { Imm8, RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegMask } > > -vcvtdq2ph, 0x5b, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3D3|EVexMap= 5|VexW0|Broadcast|Disp8MemShift=3D6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf= |No_ldSuf|StaticRounding|SAE, { RegZMM|Dword|Unspecified|BaseIndex, RegYMM = } > -vcvtdq2ph, 0x5b, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|Masking=3D3|EVe= xMap5|VexW0|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|= No_ldSuf|IntelSyntax, { RegXMM|RegYMM|Dword|Unspecified|BaseIndex, RegXMM } > -vcvtdq2ph, 0x5b, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|Masking=3D3|EVe= xMap5|VexW0|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|= No_ldSuf|ATTSyntax, { RegXMM|RegYMM|Dword|BaseIndex, RegXMM } > -vcvtdq2phx, 0x5b, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Maskin= g=3D3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3D4|No_bSuf|No_wSuf|No_lSuf|No= _sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|Dword|Unspecified|BaseIndex, Reg= XMM } > -vcvtdq2phy, 0x5b, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Maskin= g=3D3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3D5|No_bSuf|No_wSuf|No_lSuf|No= _sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegYMM|Dword|Unspecified|BaseIndex, Reg= XMM } > - > -vcvtudq2ph, 0xf27a, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3D3|EVex= Map5|VexW0|Broadcast|Disp8MemShift=3D6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_q= Suf|No_ldSuf|StaticRounding|SAE, { RegZMM|Dword|Unspecified|BaseIndex, RegY= MM } > -vcvtudq2ph, 0xf27a, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|Masking=3D3|= EVexMap5|VexW0|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS= uf|No_ldSuf|IntelSyntax, { RegXMM|RegYMM|Dword|Unspecified|BaseIndex, RegXM= M } > -vcvtudq2ph, 0xf27a, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|Masking=3D3|= EVexMap5|VexW0|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS= uf|No_ldSuf|ATTSyntax, { RegXMM|RegYMM|Dword|BaseIndex, RegXMM } > -vcvtudq2phx, 0xf27a, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Mas= king=3D3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3D4|No_bSuf|No_wSuf|No_lSuf= |No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|Dword|Unspecified|BaseIndex, = RegXMM } > -vcvtudq2phy, 0xf27a, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Mas= king=3D3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3D5|No_bSuf|No_wSuf|No_lSuf= |No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegYMM|Dword|Unspecified|BaseIndex, = RegXMM } > - > -vcvtqq2ph, 0x5b, None, CpuAVX512_FP16, Modrm|Masking=3D3|EVexMap5|VexW1|= Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Sta= ticRounding|SAE|IntelSyntax, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseI= ndex, RegXMM } > -vcvtqq2ph, 0x5b, None, CpuAVX512_FP16, Modrm|Masking=3D3|EVexMap5|VexW1|= Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Sta= ticRounding|SAE|ATTSyntax, { RegXMM|RegYMM|RegZMM|Qword|BaseIndex, RegXMM } > -vcvtqq2phz, 0x5b, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3D3|EVexMa= p5|VexW1|Broadcast|Disp8MemShift=3D6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu= f|No_ldSuf|StaticRounding|SAE|ATTSyntax, { RegZMM|Qword|Unspecified|BaseInd= ex, RegXMM } > -vcvtqq2phx, 0x5b, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Maskin= g=3D3|EVexMap5|VexW1|Broadcast|Disp8MemShift=3D4|No_bSuf|No_wSuf|No_lSuf|No= _sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|Qword|Unspecified|BaseIndex, Reg= XMM } > -vcvtqq2phy, 0x5b, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Maskin= g=3D3|EVexMap5|VexW1|Broadcast|Disp8MemShift=3D5|No_bSuf|No_wSuf|No_lSuf|No= _sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegYMM|Qword|Unspecified|BaseIndex, Reg= XMM } > - > -vcvtuqq2ph, 0xf27a, None, CpuAVX512_FP16, Modrm|Masking=3D3|EVexMap5|Vex= W1|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|= StaticRounding|SAE|IntelSyntax, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|Ba= seIndex, RegXMM } > -vcvtuqq2ph, 0xf27a, None, CpuAVX512_FP16, Modrm|Masking=3D3|EVexMap5|Vex= W1|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|= StaticRounding|SAE|ATTSyntax, { RegXMM|RegYMM|RegZMM|Qword|BaseIndex, RegXM= M } > -vcvtuqq2phz, 0xf27a, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3D3|EVe= xMap5|VexW1|Broadcast|Disp8MemShift=3D6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_= qSuf|No_ldSuf|StaticRounding|SAE|ATTSyntax, { RegZMM|Qword|Unspecified|Base= Index, RegXMM } > -vcvtuqq2phx, 0xf27a, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Mas= king=3D3|EVexMap5|VexW1|Broadcast|Disp8MemShift=3D4|No_bSuf|No_wSuf|No_lSuf= |No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|Qword|Unspecified|BaseIndex, = RegXMM } > -vcvtuqq2phy, 0xf27a, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Mas= king=3D3|EVexMap5|VexW1|Broadcast|Disp8MemShift=3D5|No_bSuf|No_wSuf|No_lSuf= |No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegYMM|Qword|Unspecified|BaseIndex, = RegXMM } > - > -vcvtpd2ph, 0x665a, None, CpuAVX512_FP16, Modrm|Masking=3D3|EVexMap5|VexW= 1|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|S= taticRounding|SAE|IntelSyntax, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|Bas= eIndex, RegXMM } > -vcvtpd2ph, 0x665a, None, CpuAVX512_FP16, Modrm|Masking=3D3|EVexMap5|VexW= 1|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|S= taticRounding|SAE|ATTSyntax, { RegXMM|RegYMM|RegZMM|Qword|BaseIndex, RegXMM= } > -vcvtpd2phx, 0x665a, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Mask= ing=3D3|EVexMap5|VexW1|Broadcast|Disp8MemShift=3D4|No_bSuf|No_wSuf|No_lSuf|= No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|Qword|Unspecified|BaseIndex, R= egXMM } > -vcvtpd2phy, 0x665a, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Mask= ing=3D3|EVexMap5|VexW1|Broadcast|Disp8MemShift=3D5|No_bSuf|No_wSuf|No_lSuf|= No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegYMM|Qword|Unspecified|BaseIndex, R= egXMM } > -vcvtpd2phz, 0x665a, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3D3|EVex= Map5|VexW1|Broadcast|Disp8MemShift=3D6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_q= Suf|No_ldSuf|StaticRounding|SAE|ATTSyntax, { RegZMM|Qword|Unspecified|BaseI= ndex, RegXMM } > - > -vcvtps2phx, 0x661d, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3D3|EVex= Map5|VexW0|Broadcast|Disp8MemShift=3D6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_q= Suf|No_ldSuf|StaticRounding|SAE, { RegZMM|Dword|Unspecified|BaseIndex, RegY= MM } > -vcvtps2phx, 0x661d, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|Masking=3D3|= EVexMap5|VexW0|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS= uf|No_ldSuf|IntelSyntax, { RegXMM|RegYMM|Dword|Unspecified|BaseIndex, RegXM= M } > -vcvtps2phx, 0x661d, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|Masking=3D3|= EVexMap5|VexW0|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS= uf|No_ldSuf|ATTSyntax, { RegXMM|RegYMM|Dword|BaseIndex, RegXMM } > -vcvtps2phxx, 0x661d, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Mas= king=3D3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3D4|No_bSuf|No_wSuf|No_lSuf= |No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|Dword|Unspecified|BaseIndex, = RegXMM } > -vcvtps2phxy, 0x661d, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Mas= king=3D3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3D5|No_bSuf|No_wSuf|No_lSuf= |No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegYMM|Dword|Unspecified|BaseIndex, = RegXMM } > +vcvtdq2ph, 0x5b, None, CpuAVX512_FP16|, Modrm||Maski= ng=3D3|EVexMap5|VexW0|Broadcast|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_= ldSuf|, { |Dword, } > +vcvtudq2ph, 0xf27a, None, CpuAVX512_FP16|, Modrm||Ma= sking=3D3|EVexMap5|VexW0|Broadcast|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|= No_ldSuf|, { |Dword, } > + > +vcvtqq2ph, 0x5b, None, CpuAVX512_FP16|, Modrm||Ma= sking=3D3|EVexMap5|VexW1|Broadcast|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|= No_ldSuf||, { |Qword, RegXMM } > +vcvtuqq2ph, 0xf27a, None, CpuAVX512_FP16|, Modrm|= |Masking=3D3|EVexMap5|VexW1|Broadcast|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS= uf|No_ldSuf||, { |Qword, RegXMM } > + > +vcvtpd2ph, 0x665a, None, CpuAVX512_FP16|, Modrm||= Masking=3D3|EVexMap5|VexW1|Broadcast|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu= f|No_ldSuf||, { |Qword, RegXMM } > + > +vcvtps2phx, 0x661d, None, CpuAVX512_FP16|, Modrm||Ma= sking=3D3|EVexMap5|VexW0|Broadcast|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|= No_ldSuf|, { |Dword, } > > vcvtw2ph, 0xf37d, None, CpuAVX512_FP16, Modrm|Masking=3D3|EVexMap5|VexW0= |Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu= f|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|Base= Index, RegXMM|RegYMM|RegZMM } > vcvtuw2ph, 0xf27d, None, CpuAVX512_FP16, Modrm|Masking=3D3|EVexMap5|VexW= 0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS= uf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|Bas= eIndex, RegXMM|RegYMM|RegZMM } > @@ -3298,10 +3248,7 @@ vcvttph2uw, 0x7c, None, CpuAVX512_FP16, > vcvttsh2si, 0xf32c, None, CpuAVX512_FP16, Modrm|EVexLIG|EVexMap5|Disp8Me= mShift=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ToQword|SAE, { = RegXMM|Word|Unspecified|BaseIndex, Reg32|Reg64 } > vcvttsh2usi, 0xf378, None, CpuAVX512_FP16, Modrm|EVexLIG|EVexMap5|Disp8M= emShift=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ToQword|SAE, {= RegXMM|Word|Unspecified|BaseIndex, Reg32|Reg64 } > > -vfpclassph, 0x66, None, CpuAVX512_FP16, Modrm|Masking=3D2|Space0F3A|VexW= 0|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, = { Imm8, RegXMM|RegYMM|RegZMM|Word|BaseIndex, RegMask } > -vfpclassphz, 0x66, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3D2|Space= 0F3A|VexW0|Broadcast|Disp8MemShift=3D6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_q= Suf|No_ldSuf|ATTSyntax, { Imm8, RegZMM|Word|Unspecified|BaseIndex, RegMask = } > -vfpclassphx, 0x66, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Maski= ng=3D2|Space0F3A|VexW0|Broadcast|Disp8MemShift=3D4|No_bSuf|No_wSuf|No_lSuf|= No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Imm8, RegXMM|Word|Unspecified|BaseInd= ex, RegMask } > -vfpclassphy, 0x66, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Maski= ng=3D2|Space0F3A|VexW0|Broadcast|Disp8MemShift=3D5|No_bSuf|No_wSuf|No_lSuf|= No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Imm8, RegYMM|Word|Unspecified|BaseInd= ex, RegMask } > +vfpclassph, 0x66, None, CpuAVX512_FP16|, Modrm||M= asking=3D2|Space0F3A|VexW0|Broadcast|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu= f|No_ldSuf|, { Imm8, |Word, RegMask } > > vmovw, 0x666e, None, CpuAVX512_FP16, D|Modrm|EVex128|VexWIG|EVexMap5|Dis= p8MemShift=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Uns= pecified|BaseIndex, RegXMM } > vmovw, 0x667e, None, CpuAVX512_FP16, D|RegMem|EVex128|VexWIG|EVexMap5|No= _bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Reg32 } > OK. Thanks. --=20 H.J.