From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 5920 invoked by alias); 20 Mar 2014 17:30:48 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 5910 invoked by uid 89); 20 Mar 2014 17:30:48 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.5 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-oa0-f50.google.com Received: from mail-oa0-f50.google.com (HELO mail-oa0-f50.google.com) (209.85.219.50) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Thu, 20 Mar 2014 17:30:46 +0000 Received: by mail-oa0-f50.google.com with SMTP id i7so1273990oag.37 for ; Thu, 20 Mar 2014 10:30:45 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.182.81.197 with SMTP id c5mr8333912oby.40.1395336645095; Thu, 20 Mar 2014 10:30:45 -0700 (PDT) Received: by 10.76.151.198 with HTTP; Thu, 20 Mar 2014 10:30:45 -0700 (PDT) In-Reply-To: References: <20140220151936.GA1312@msticlxl7.ims.intel.com> <20140224132223.GA39232@msticlxl7.ims.intel.com> <20140225094128.GB31394@msticlxl7.ims.intel.com> <20140225162451.GB75072@msticlxl7.ims.intel.com> Date: Thu, 20 Mar 2014 17:30:00 -0000 Message-ID: Subject: Re: [PATCH, i386][3/3] Update to match latest AVX512 spec. From: "H.J. Lu" To: Ilya Tocar Cc: Binutils Content-Type: text/plain; charset=ISO-8859-1 X-IsSubscribed: yes X-SW-Source: 2014-03/txt/msg00234.txt.bz2 On Tue, Feb 25, 2014 at 8:53 AM, H.J. Lu wrote: > On Tue, Feb 25, 2014 at 8:24 AM, Ilya Tocar wrote: >>> >>> vcvtps2ph supports memory destination. Please add AVX512F testcases >>> >>> with memory destination. >>> >>> >>> >> We already have such tests. See e. g. on lines 6883-6890 in >>> >> gas/testsuite/gas/i386/avx512f.s we have: >>> >> >>> >> vcvtps2ph $0xab, %zmm6, (%ecx) # AVX512F >>> >> vcvtps2ph $0xab, %zmm6, (%ecx){%k7} # AVX512F >>> >> vcvtps2ph $123, %zmm6, (%ecx) # AVX512F >>> >> vcvtps2ph $123, %zmm6, -123456(%esp,%esi,8) # AVX512F >>> >> vcvtps2ph $123, %zmm6, 4064(%edx) # AVX512F Disp8 >>> >> vcvtps2ph $123, %zmm6, 4096(%edx) # AVX512F >>> >> vcvtps2ph $123, %zmm6, -4096(%edx) # AVX512F Disp8 >>> >> >>> >> Do we need additional tests? >>> > >>> > Yes, please test with memory destination for: >>> > >>> > vcvtps2ph, 3, 0x661D, None, 1, CpuAVX512F, >>> > Modrm|EVex=1|Masking=2|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, >>> > { Imm8, Imm8, RegZMM|RegMem } >> This variant is removed in my patch. What exactly should I test? >>> >>> Also for >>> >>> vcvtps2ph, 4, 0x661D, None, 1, CpuAVX512F, >>> Modrm|EVex=1|Masking=3|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, >>> { Imm8, Imm8, RegZMM, RegYMM|RegMem } >> This is reg-reg version with SAE, which is already tested on e. g. >> line 2602 in gas/testsuite/gas/i386/avx512f.s: >> >> vcvtps2ph $0xab, {sae}, %zmm5, %ymm6{%k7} # AVX512F >> >> Also instruction can't have memory operand and SAE at the same time. > > OK. I checked it in for you. > I backported it to binutils-2_24-branch. -- H.J.