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Lu" Date: Tue, 1 Nov 2022 07:42:03 -0700 Message-ID: Subject: Re: [PATCH 1/2] i386: Add and To: "Kong, Lingling" Cc: "Beulich, Jan" , "Jiang, Haochen" , "binutils@sourceware.org" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-3022.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Tue, Nov 1, 2022 at 1:50 AM Kong, Lingling wro= te: > > > On Mon, Oct 31, 2022 at 2:04 AM Jan Beulich wrote: > > > > > > On 31.10.2022 07:06, Haochen Jiang wrote: > > > > From: konglin1 > > > > > > > > opcodes/ > > > > * i386-opc.tbl: Add for VEX insn with x/y suffix, > > > > and for EVEX insn with x/y suffix. > > > > > > Code change looks good (and thanks for splitting it off), but the > > > changelog entry wants to use "rename" instead of "add", not the least > > > to also mention > > > > Agreed. > > > > > the identifier which goes away. However, this kind of a change is > > > where personally I think the legacy changelog model is quite a bit > > > worse than the modern one with a proper textual commit message. > > > > > > > I prefer concise and accurate ChangeLog entries. It is easier to tell = what the > > changes are. > > > > -- > > H.J. > > Fixed. Thanks for the review! > > [PATCH 1/3] i386: Rename template. > > opcodes/ > * i386-opc.tbl: Rename template for VEX insn with x/y su= ffix to . > Rename for EVEX insn with x/y suffix to . > --- > opcodes/i386-opc.tbl | 35 ++++++++++++++++++----------------- > 1 file changed, 18 insertions(+), 17 deletions(-) > > diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index f1d17171c3= ..3238c4fc2e 100644 > --- a/opcodes/i386-opc.tbl > +++ b/opcodes/i386-opc.tbl > @@ -1469,7 +1469,8 @@ gf2p8mulb, 0x660f38cf, None, CpuGFN= I, Modrm||No_bSuf|No > nge_uq:19:, ngt_uq:1a:, false_os:1b:C, neq_os:1c:C, ge_oq:1d:, gt_oq= :1e:, + > true_us:1f:C> > > - +// is used for VEX instructions with x/y suffixes. > + $i:Vex:IntelSyntax:RegXMM|RegYMM|Unspecified|BaseIndex, + > $a:Vex:ATTSyntax:RegXMM|RegYMM, + > x:Vex128:ATTSyntax:RegXMM|Unspecified|BaseIndex, + @@ -1494,8 +1495,= 8 @@ vcomis, 0x2f, None, CpuAVX, Modrm|VexLIG|Space0F|VexWIG|N= o_bSuf|No_ > vcvtdq2pd, 0xf3e6, None, CpuAVX, Modrm|Vex128|Space0F|VexWIG|No_bSuf|No_= wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex= , RegXMM } vcvtdq2pd, 0xf3e6, None, CpuAVX, Modrm|Vex256|Space0F|VexWIG|No= _bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIn= dex, RegYMM } vcvtdq2ps, 0x5b, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|Chec= kRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|Ba= seIndex|RegXMM|RegYMM, RegXMM|RegYMM } -vcvtpd2dq, 0xf2e6, None, CpuAVX= , Modrm||Space0F|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_= ldSuf|, { , RegXMM } -vcvtpd2ps, 0x665a, None, CpuAV= X, Modrm||Space0F|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No= _ldSuf|, { , RegXMM } > +vcvtpd2dq, 0xf2e6, None, CpuAVX, > +Modrm||Space0F|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf| > +No_ldSuf|, { , RegXMM } vcvtpd2ps, 0x665a, > +None, CpuAVX, > +Modrm||Space0F|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf| > +No_ldSuf|, { , RegXMM } > vcvtps2dq, 0x665b, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|N= o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|Re= gXMM|RegYMM, RegXMM|RegYMM } vcvtps2pd, 0x5a, None, CpuAVX, Modrm|Vex128|S= pace0F|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qw= ord|Unspecified|BaseIndex, RegXMM } vcvtps2pd, 0x5a, None, CpuAVX, Modrm|V= ex256|Space0F|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Re= gXMM|Unspecified|BaseIndex, RegYMM } @@ -1504,7 +1505,7 @@ vcvtsd2ss, 0xf25= a, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexVVVV|VexWIG|No_bSuf|No_w > vcvtsi2s, 0x2a, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|= IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ATTSyntax, { Reg32|Reg64|Unspec= ified|BaseIndex, RegXMM, RegXMM } vcvtsi2s, 0x2a, None, CpuAV= X, Modrm|VexLIG|Space0F|VexVVVV|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|IntelSynta= x, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } vcvtss2sd, 0xf35a= , None, CpuAVX, Modrm|Vex=3D3|Space0F|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSu= f|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, R= egXMM } -vcvttpd2dq, 0x66e6, None, CpuAVX, Modrm||Space0F|VexWI= G|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|, { ,= RegXMM } > +vcvttpd2dq, 0x66e6, None, CpuAVX, > +Modrm||Space0F|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf| > +No_ldSuf|, { , RegXMM } > vcvttps2dq, 0xf35b, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|No_bSuf|No_wS= uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM,= RegXMM|RegYMM } vcvtts2si, 0x2c, None, CpuAVX, Modrm|VexLIG|= Space0F|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { |Unspecified|BaseIndex= |RegXMM, Reg32|Reg64 } vdivp, 0x5e, None, CpuAVX, Modrm|Vex|S= pace0F|VexVVVV|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|= No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegY= MM } @@ -1701,7 +1702,6 @@ vxorp, 0x57, None, CpuAVX, Modrm|C|= Vex|Space0F|VexVVVV|VexWIG|Check > vzeroall, 0x77, None, CpuAVX, Vex=3D2|Space0F|VexWIG|No_bSuf|No_wSuf|No_= lSuf|No_sSuf|No_qSuf|No_ldSuf, {} vzeroupper, 0x77, None, CpuAVX, Vex|Spac= e0F|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {} > > - > > // 256bit integer AVX2 instructions. > > @@ -2052,7 +2052,8 @@ vpclmulhqhqdq, 0x6644, 0x11, CpuVPCLMULQDQ, Modrm|V= ex=3D2|Space0F3A|VexWIG|VexVVVV > d:CpuAVX512F:CpuAVX512DQ:66:f2:66:Space0F:Space0F38:1:VexW1:Qword, + > h:CpuAVX512_FP16:CpuAVX512_FP16::f3::EVexMap5:EVexMap6:0:VexW0:Word> > > - +// is used for EVEX instructions with x/y suffixes. > + $z::EVex512|Disp8MemShift=3D6:StaticRounding|SAE:SAE:RegZMM|Unspecif= ied|BaseIndex:RegYMM, + > $i:CpuAVX512VL:Disp8ShiftVL|IntelSyntax:::RegXMM|RegYMM|Unspecified|= BaseIndex:RegXMM, + > $a:CpuAVX512VL:Disp8ShiftVL|ATTSyntax:::RegXMM|RegYMM|BaseIndex:RegX= MM, + @@ -2150,11 +2151,11 @@ vcvtudq2pd, 0xF37A, None, CpuAVX512F, Modrm|E= Vex=3D1|Masking=3D3|Space0F|VexW=3D1|Broa > vcvtdq2ps, 0x5B, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexW0|Broad= cast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_l= dSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM } vcvtps2udq, 0x79, None, CpuAVX512F, Modrm|Masking= =3D3|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_l= Suf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dwo= rd|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } > > -vcvtpd2dq, 0xf2e6, None, CpuAVX512F|, Modrm||Masking= =3D3|Space0F|VexW1|Broadcast|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS= uf|, { |Qword, } > +vcvtpd2dq, 0xf2e6, None, CpuAVX512F|, > +Modrm||Masking=3D3|Space0F|VexW1|Broadcast|No_bSuf|No_wSuf|No_= l > +Suf|No_sSuf|No_qSuf|No_ldSuf|, { |Qword, } > > -vcvtpd2ps, 0x665a, None, CpuAVX512F|, Modrm||Masking= =3D3|Space0F|VexW1|Broadcast|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS= uf|, { |Qword, } > +vcvtpd2ps, 0x665a, None, CpuAVX512F|, > +Modrm||Masking=3D3|Space0F|VexW1|Broadcast|No_bSuf|No_wSuf|No_= l > +Suf|No_sSuf|No_qSuf|No_ldSuf|, { |Qword, } > > -vcvtpd2udq, 0x79, None, CpuAVX512F|, Modrm||Masking= =3D3|Space0F|VexW1|Broadcast|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS= uf|, { |Qword, } > +vcvtpd2udq, 0x79, None, CpuAVX512F|, > +Modrm||Masking=3D3|Space0F|VexW1|Broadcast|No_bSuf|No_wSuf|No_= l > +Suf|No_sSuf|No_qSuf|No_ldSuf|, { |Qword, } > > vcvtph2ps, 0x6613, None, CpuAVX512F, Modrm|EVex512|Masking=3D3|Space0F38= |VexW0|Disp8MemShift=3D5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|S= AE, { RegYMM|Unspecified|BaseIndex, RegZMM } > > @@ -2185,8 +2186,8 @@ vcvtusi2ss, 0xF37B, None, CpuAVX512F, Modrm|EVexLIG= |Space0F|VexVVVV|Disp8ShiftVL > > vcvtss2sd, 0xF35A, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0F|V= exVVVV|VexW0|Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_l= dSuf|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } > > -vcvttpd2dq, 0x66e6, None, CpuAVX512F|, Modrm||Maskin= g=3D3|Space0F|VexW1|Broadcast|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ld= Suf|, { |Qword, } -vcvttpd2udq, 0x78, None, Cp= uAVX512F|, Modrm||Masking=3D3|Space0F|VexW1|Broadcast|No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|, { |Qword, } > +vcvttpd2dq, 0x66e6, None, CpuAVX512F|, > +Modrm||Masking=3D3|Space0F|VexW1|Broadcast|No_bSuf|No_wSuf|No_= l > +Suf|No_sSuf|No_qSuf|No_ldSuf|, { |Qword, } > +vcvttpd2udq, 0x78, None, CpuAVX512F|, > +Modrm||Masking=3D3|Space0F|VexW1|Broadcast|No_bSuf|No_wSuf|No_= l > +Suf|No_sSuf|No_qSuf|No_ldSuf|, { |Qword, } > > vcvttps2dq, 0xF35B, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexW0|Br= oadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N= o_ldSuf|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|Reg= YMM|RegZMM } vcvttps2udq, 0x78, None, CpuAVX512F, Modrm|Masking=3D3|Space0= F|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf= |No_qSuf|No_ldSuf|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, = RegXMM|RegYMM|RegZMM } @@ -2751,7 +2752,7 @@ vcvtps2uqq, 0x6679, None, CpuA= VX512DQ|CpuAVX512VL, Modrm|EVex256|Masking=3D3|Space vcvtqq2pd, 0xF3E6, No= ne, CpuAVX512DQ, Modrm|Masking=3D3|Space0F|VexW1|Broadcast|Disp8ShiftVL|Che= ckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|S= AE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZM= M } vcvtuqq2pd, 0xF37A, None, CpuAVX512DQ, Modrm|Masking=3D3|Space0F|VexW1= |Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu= f|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|Bas= eIndex, RegXMM|RegYMM|RegZMM } > > -vcvtqq2ps, 0x5b, None, CpuAVX512DQ|, Modrm||Masking= =3D3|Space0F|VexW1|Broadcast|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS= uf|, { |Qword, } > +vcvtqq2ps, 0x5b, None, CpuAVX512DQ|, > +Modrm||Masking=3D3|Space0F|VexW1|Broadcast|No_bSuf|No_wSuf|No_= l > +Suf|No_sSuf|No_qSuf|No_ldSuf|, { |Qword, } > > vcvttpd2qq, 0x667A, None, CpuAVX512DQ, Modrm|Masking=3D3|Space0F|VexW1|B= roadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|= No_ldSuf|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|Re= gYMM|RegZMM } vcvttpd2uqq, 0x6678, None, CpuAVX512DQ, Modrm|Masking=3D3|Sp= ace0F|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_= sSuf|No_qSuf|No_ldSuf|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseInd= ex, RegXMM|RegYMM|RegZMM } @@ -2763,7 +2764,7 @@ vcvttps2uqq, 0x6678, None,= CpuAVX512DQ, Modrm|EVex512|Masking=3D3|Space0F|VexW0|Br > vcvttps2uqq, 0x6678, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex128|Maskin= g=3D3|Space0F|VexW0|Broadcast|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_= sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM }= vcvttps2uqq, 0x6678, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex256|Masking= =3D3|Space0F|VexW0|Broadcast|Disp8MemShift=3D4|No_bSuf|No_wSuf|No_lSuf|No_s= Suf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } > > -vcvtuqq2ps, 0xf27a, None, CpuAVX512DQ|, Modrm||Maski= ng=3D3|Space0F|VexW1|Broadcast|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_l= dSuf|, { |Qword, } > +vcvtuqq2ps, 0xf27a, None, CpuAVX512DQ|, > +Modrm||Masking=3D3|Space0F|VexW1|Broadcast|No_bSuf|No_wSuf|No_= l > +Suf|No_sSuf|No_qSuf|No_ldSuf|, { |Qword, } > > vextractf32x8, 0x661B, None, CpuAVX512DQ, Modrm|EVex=3D1|MaskingMorZ|Spa= ce0F3A|VexW=3D1|Disp8MemShift=3D5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N= o_ldSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } vextracti32x8, 0x6= 63B, None, CpuAVX512DQ, Modrm|EVex=3D1|MaskingMorZ|Space0F3A|VexW=3D1|Disp8= MemShift=3D5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZ= MM, RegYMM|Unspecified|BaseIndex } @@ -3049,7 +3050,7 @@ movdir64b, 0x660f3= 8f8, None, CpuMOVDIR64B, Modrm|AddrPrefixOpReg, { Unspecified| > > vcvtne2ps2bf16, 0xf272, None, CpuAVX512_BF16, Modrm|Space0F38|VexVVVV|Ma= sking=3D3|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf= |No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseInd= ex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > > -vcvtneps2bf16, 0xf372, None, CpuAVX512_BF16|, Modrm|Space0F38= ||Masking=3D3|VexW0|Broadcast|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_q= Suf|No_ldSuf, { |Dword, } > +vcvtneps2bf16, 0xf372, None, CpuAVX512_BF16|, > +Modrm|Space0F38||Masking=3D3|VexW0|Broadcast|No_bSuf|No_wSuf|N= o > +_lSuf|No_sSuf|No_qSuf|No_ldSuf, { |Dword, } > > vdpbf16ps, 0xf352, None, CpuAVX512_BF16, Modrm|Space0F38|VexVVVV|Masking= =3D3|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_s= Suf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, R= egXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > > @@ -3193,15 +3194,15 @@ vcmpph, 0xc2, None, CpuAVX512_FP16, Modrm|Masking= =3D2|Space0F3A|VexVVVV|VexW0|Broa > vcmpsh, 0xf3c2, 0x, CpuAVX512_FP16, Modrm|EVexLIG|Maskin= g=3D2|Space0F3A|VexVVVV|VexW0|Disp8MemShift=3D1|No_bSuf|No_wSuf|No_lSuf|No_= sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegX= MM, RegMask } vcmpsh, 0xf3c2, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking= =3D2|Space0F3A|VexVVVV|VexW0|Disp8MemShift=3D1|No_bSuf|No_wSuf|No_lSuf|No_s= Suf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM|Word|Unspecified|BaseIndex, RegXMM= , RegMask } > > -vcvtdq2ph, 0x5b, None, CpuAVX512_FP16|, Modrm||Maski= ng=3D3|EVexMap5|VexW0|Broadcast|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_= ldSuf|, { |Dword, } -vcvtudq2ph, 0xf27a, None, = CpuAVX512_FP16|, Modrm||Masking=3D3|EVexMap5|VexW0|Broadcas= t|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|, { |Dwor= d, } > +vcvtdq2ph, 0x5b, None, CpuAVX512_FP16|, > +Modrm||Masking=3D3|EVexMap5|VexW0|Broadcast|No_bSuf|No_wSuf|No= _ > +lSuf|No_sSuf|No_qSuf|No_ldSuf|, { |Dword, } > +vcvtudq2ph, 0xf27a, None, CpuAVX512_FP16|, > +Modrm||Masking=3D3|EVexMap5|VexW0|Broadcast|No_bSuf|No_wSuf|No= _ > +lSuf|No_sSuf|No_qSuf|No_ldSuf|, { |Dword, } > > vcvtqq2ph, 0x5b, None, CpuAVX512_FP16|, Modrm||Ma= sking=3D3|EVexMap5|VexW1|Broadcast|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|= No_ldSuf||, { |Qword, RegXMM } vcvtuqq2ph, = 0xf27a, None, CpuAVX512_FP16|, Modrm||Masking=3D3|EVexMap= 5|VexW1|Broadcast|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|= |, { |Qword, RegXMM } > > vcvtpd2ph, 0x665a, None, CpuAVX512_FP16|, Modrm||= Masking=3D3|EVexMap5|VexW1|Broadcast|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu= f|No_ldSuf||, { |Qword, RegXMM } > > -vcvtps2phx, 0x661d, None, CpuAVX512_FP16|, Modrm||Ma= sking=3D3|EVexMap5|VexW0|Broadcast|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|= No_ldSuf|, { |Dword, } > +vcvtps2phx, 0x661d, None, CpuAVX512_FP16|, > +Modrm||Masking=3D3|EVexMap5|VexW0|Broadcast|No_bSuf|No_wSuf|No= _ > +lSuf|No_sSuf|No_qSuf|No_ldSuf|, { |Dword, } > > vcvtw2ph, 0xf37d, None, CpuAVX512_FP16, Modrm|Masking=3D3|EVexMap5|VexW0= |Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu= f|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|Base= Index, RegXMM|RegYMM|RegZMM } vcvtuw2ph, 0xf27d, None, CpuAVX512_FP16, Mod= rm|Masking=3D3|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|N= o_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM= |RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } > -- > 2.27.0 > > > > OK. Thanks. --=20 H.J.