* [PATCH] Allow setting CpuVRex bit in .arch directive @ 2016-05-21 16:54 Jakub Jelinek 2016-05-21 17:06 ` Jakub Jelinek 0 siblings, 1 reply; 18+ messages in thread From: Jakub Jelinek @ 2016-05-21 16:54 UTC (permalink / raw) To: binutils; +Cc: Uros Bizjak, Kirill Yukhin, H.J. Lu [-- Attachment #1: Type: text/plain, Size: 2483 bytes --] Hi! I've tried today to check for the various AVX512* ISA issues in GCC using assembly .arch support. Seems by default all flags (but l10m/k10m) are set, but if I want to allow all insns but say AVX512DQ ISA instructions or something similar, there is no way to do it - there is no way except for explicit no* flags to remove ISA bits from the default, so one has to set some CPU and then add all the ISA flags one wants. Seems most of them can be added, except for one very important one - the CpuVRex bit. Here is a patch to add support for .arch .vrex to set that, another option might be to set CpuVRex whenever CpuAVX512F is set in 64-bit mode. Any preferences? Attached is then the hack I've been using on the GCC side, plus another hack to try to use XMM16+ regs more often. 2016-05-21 Jakub Jelinek <jakub@redhat.com> * config/tc-i386.c (cpu_arch): Add .vrex entry. * i386-gen.c (cpu_flag_init): Add CPU_VREX_FLAGS. * i386-init.h: Regenerated. diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 8a4d987..212796a 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -963,6 +963,8 @@ static const arch_entry cpu_arch[] = CPU_OSPKE_FLAGS, 0, 0 }, { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN, CPU_RDPID_FLAGS, 0, 0 }, + { STRING_COMMA_LEN (".vrex"), PROCESSOR_UNKNOWN, + CPU_VREX_FLAGS, 0, 0 } }; #ifdef I386COFF diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index 5b997f9..8042bee 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -258,7 +258,9 @@ static initializer cpu_flag_init[] = { "CPU_OSPKE_FLAGS", "CpuOSPKE" }, { "CPU_RDPID_FLAGS", - "CpuRDPID" } + "CpuRDPID" }, + { "CPU_VREX_FLAGS", + "CpuVRex" } }; static initializer operand_type_init[] = diff --git a/opcodes/i386-init.h b/opcodes/i386-init.h index de68c22..f5d6c64 100644 --- a/opcodes/i386-init.h +++ b/opcodes/i386-init.h @@ -781,6 +781,13 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } } +#define CPU_VREX_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + #define OPERAND_TYPE_NONE \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ Jakub [-- Attachment #2: P2 --] [-- Type: text/plain, Size: 2407 bytes --] --- gcc/config/i386/i386.c.jj 2016-05-20 20:48:23.000000000 +0200 +++ gcc/config/i386/i386.c 2016-05-21 16:10:39.689599317 +0200 @@ -7910,6 +7910,8 @@ ix86_function_ms_hook_prologue (const_tr return false; } +static int prev_avx512 = -1; + /* Write the extra assembler code needed to declare a function properly. */ void @@ -7918,6 +7920,59 @@ ix86_asm_output_function_label (FILE *as { bool is_ms_hook = ix86_function_ms_hook_prologue (decl); + int cur_avx512 = ((TARGET_AVX512F ? 1 : 0) + | (TARGET_AVX512PF ? 2 : 0) + | (TARGET_AVX512ER ? 4 : 0) + | (TARGET_AVX512CD ? 8 : 0) + | (TARGET_AVX512DQ ? 16 : 0) + | (TARGET_AVX512BW ? 32 : 0) + | (TARGET_AVX512VL ? 64 : 0) + | (TARGET_AVX512VBMI ? 128 : 0) + | (TARGET_AVX512IFMA ? 256 : 0)); + if (cur_avx512 != prev_avx512) + { + fprintf (asm_out_file, + "\t.arch\tbdver4\n" + "\t.arch\t.8087\n" + "\t.arch\t.287\n" + "\t.arch\t.3dnow\n" + "\t.arch\t.3dnowa\n" + "\t.arch\t.padlock\n" + "\t.arch\t.vmx\n" + "\t.arch\t.smx\n" + "\t.arch\t.ept\n" + "\t.arch\t.hle\n" + "\t.arch\t.rtm\n" + "\t.arch\t.invpcid\n" + "\t.arch\t.vmfunc\n" + "\t.arch\t.prefetchwt1\n" + "\t.arch\t.se1\n" + "\t.arch\t.clwb\n" + "\t.arch\t.pcommit\n" + "\t.arch\t.mpx\n" + "\t.arch\t.adx\n" + "\t.arch\t.rdseed\n" + "\t.arch\t.smap\n" + "\t.arch\t.sha\n" + "\t.arch\t.xsavec\n" + "\t.arch\t.xsaves\n" + "\t.arch\t.clflushopt\n" + "\t.arch\t.clzero\n" + "\t.arch\t.ospke\n" + "\t.arch\t.rdpid\n%s%s%s%s%s%s%s%s%s%s", + (TARGET_64BIT && TARGET_AVX512F) ? "\t.arch\t.vrex\n" : "", + TARGET_AVX512F ? "\t.arch\t.avx512f\n" : "", + TARGET_AVX512PF ? "\t.arch\t.avx512pf\n" : "", + TARGET_AVX512ER ? "\t.arch\t.avx512er\n" : "", + TARGET_AVX512CD ? "\t.arch\t.avx512cd\n" : "", + TARGET_AVX512DQ ? "\t.arch\t.avx512dq\n" : "", + TARGET_AVX512BW ? "\t.arch\t.avx512bw\n" : "", + TARGET_AVX512VL ? "\t.arch\t.avx512vl\n" : "", + TARGET_AVX512VBMI ? "\t.arch\t.avx512vbmi\n" : "", + TARGET_AVX512IFMA ? "\t.arch\t.avx512ifma\n" : ""); + prev_avx512 = cur_avx512; + } + if (is_ms_hook) { int i, filler_count = (TARGET_64BIT ? 32 : 16); [-- Attachment #3: P3 --] [-- Type: text/plain, Size: 914 bytes --] --- gcc/config/i386/i386.h.jj 2016-05-12 10:29:41.000000000 +0200 +++ gcc/config/i386/i386.h 2016-05-21 17:50:01.923718417 +0200 @@ -1064,10 +1064,10 @@ extern const char *host_detect_local_cpu #define REG_ALLOC_ORDER \ { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\ - 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \ - 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ - 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, \ - 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, \ + 18, 19, 20, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, \ + 65, 66, 67, 68, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \ + 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, \ + 47, 48, 49, 50, 51, 52, 69, 70, 71, 72, 73, 74, 75, 76, 77, \ 78, 79, 80 } /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH] Allow setting CpuVRex bit in .arch directive 2016-05-21 16:54 [PATCH] Allow setting CpuVRex bit in .arch directive Jakub Jelinek @ 2016-05-21 17:06 ` Jakub Jelinek 2016-05-24 17:24 ` H.J. Lu 0 siblings, 1 reply; 18+ messages in thread From: Jakub Jelinek @ 2016-05-21 17:06 UTC (permalink / raw) To: binutils; +Cc: Uros Bizjak, Kirill Yukhin, H.J. Lu Hi! On Sat, May 21, 2016 at 06:54:05PM +0200, Jakub Jelinek wrote: > I've tried today to check for the various AVX512* ISA issues in GCC > using assembly .arch support. Seems by default all flags (but l10m/k10m) > are set, but if I want to allow all insns but say AVX512DQ ISA instructions > or something similar, there is no way to do it - there is no way except > for explicit no* flags to remove ISA bits from the default, so one has to > set some CPU and then add all the ISA flags one wants. Seems most of them > can be added, except for one very important one - the CpuVRex bit. > > Here is a patch to add support for .arch .vrex to set that, another option > might be to set CpuVRex whenever CpuAVX512F is set in 64-bit mode. > Any preferences? BTW, to my surprise, I haven't found any issues in the compiler this way, even the known ones that I've just fixed. E.g. .arch corei7 .arch .avx512f .arch .avx512vl vinserti32x4 $0x0, %xmm0, %ymm15, %ymm15 vinserti32x4 $0x1, %xmm0, %ymm15, %ymm15 vinserti64x2 $0x0, %xmm0, %ymm15, %ymm15 vinserti64x2 $0x1, %xmm0, %ymm15, %ymm15 vinsertf32x4 $0x0, %xmm0, %ymm15, %ymm15 vinsertf32x4 $0x1, %xmm0, %ymm15, %ymm15 vinsertf64x2 $0x0, %xmm0, %ymm15, %ymm15 vinsertf64x2 $0x1, %xmm0, %ymm15, %ymm15 assembles fine, even when it IMHO should not - the 64x2 instructions are all AVX512VL & AVX512DQ. Jakub ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH] Allow setting CpuVRex bit in .arch directive 2016-05-21 17:06 ` Jakub Jelinek @ 2016-05-24 17:24 ` H.J. Lu 2016-05-24 17:49 ` Jakub Jelinek 0 siblings, 1 reply; 18+ messages in thread From: H.J. Lu @ 2016-05-24 17:24 UTC (permalink / raw) To: Jakub Jelinek; +Cc: Binutils, Uros Bizjak, Kirill Yukhin On Sat, May 21, 2016 at 10:06 AM, Jakub Jelinek <jakub@redhat.com> wrote: > Hi! > > On Sat, May 21, 2016 at 06:54:05PM +0200, Jakub Jelinek wrote: >> I've tried today to check for the various AVX512* ISA issues in GCC >> using assembly .arch support. Seems by default all flags (but l10m/k10m) >> are set, but if I want to allow all insns but say AVX512DQ ISA instructions >> or something similar, there is no way to do it - there is no way except >> for explicit no* flags to remove ISA bits from the default, so one has to >> set some CPU and then add all the ISA flags one wants. Seems most of them >> can be added, except for one very important one - the CpuVRex bit. >> >> Here is a patch to add support for .arch .vrex to set that, another option >> might be to set CpuVRex whenever CpuAVX512F is set in 64-bit mode. >> Any preferences? Do you have a testcase to show how CpuVRex is used? > BTW, to my surprise, I haven't found any issues in the compiler this way, > even the known ones that I've just fixed. > E.g. > .arch corei7 > .arch .avx512f > .arch .avx512vl > vinserti32x4 $0x0, %xmm0, %ymm15, %ymm15 > vinserti32x4 $0x1, %xmm0, %ymm15, %ymm15 > vinserti64x2 $0x0, %xmm0, %ymm15, %ymm15 > vinserti64x2 $0x1, %xmm0, %ymm15, %ymm15 > vinsertf32x4 $0x0, %xmm0, %ymm15, %ymm15 > vinsertf32x4 $0x1, %xmm0, %ymm15, %ymm15 > vinsertf64x2 $0x0, %xmm0, %ymm15, %ymm15 > vinsertf64x2 $0x1, %xmm0, %ymm15, %ymm15 > assembles fine, even when it IMHO should not - the 64x2 instructions > are all AVX512VL & AVX512DQ. > Since vinsertf64x2 is an CpuAVX512VL instruction, I don't see why it shouldn't assemble. -- H.J. ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH] Allow setting CpuVRex bit in .arch directive 2016-05-24 17:24 ` H.J. Lu @ 2016-05-24 17:49 ` Jakub Jelinek 2016-05-24 19:02 ` H.J. Lu 0 siblings, 1 reply; 18+ messages in thread From: Jakub Jelinek @ 2016-05-24 17:49 UTC (permalink / raw) To: H.J. Lu; +Cc: Binutils, Uros Bizjak, Kirill Yukhin On Tue, May 24, 2016 at 10:24:11AM -0700, H.J. Lu wrote: > On Sat, May 21, 2016 at 10:06 AM, Jakub Jelinek <jakub@redhat.com> wrote: > > Hi! > > > > On Sat, May 21, 2016 at 06:54:05PM +0200, Jakub Jelinek wrote: > >> I've tried today to check for the various AVX512* ISA issues in GCC > >> using assembly .arch support. Seems by default all flags (but l10m/k10m) > >> are set, but if I want to allow all insns but say AVX512DQ ISA instructions > >> or something similar, there is no way to do it - there is no way except > >> for explicit no* flags to remove ISA bits from the default, so one has to > >> set some CPU and then add all the ISA flags one wants. Seems most of them > >> can be added, except for one very important one - the CpuVRex bit. > >> > >> Here is a patch to add support for .arch .vrex to set that, another option > >> might be to set CpuVRex whenever CpuAVX512F is set in 64-bit mode. > >> Any preferences? > > Do you have a testcase to show how CpuVRex is used? Try: .arch corei7 .arch .avx512f vpxord %xmm15, %xmm15, %xmm15 vpxord %xmm16, %xmm16, %xmm16 I get: /tmp/1.s: Assembler messages: /tmp/1.s:4: Error: bad register name `%xmm16' and couldn't find any way how to make that assemble if I want to disable even some ISA set and thus have to start with .arch <cpuname> and add all the ISA sets I want to enable on top of that CPU. > > BTW, to my surprise, I haven't found any issues in the compiler this way, > > even the known ones that I've just fixed. > > E.g. > > .arch corei7 > > .arch .avx512f > > .arch .avx512vl > > vinserti32x4 $0x0, %xmm0, %ymm15, %ymm15 > > vinserti32x4 $0x1, %xmm0, %ymm15, %ymm15 > > vinserti64x2 $0x0, %xmm0, %ymm15, %ymm15 > > vinserti64x2 $0x1, %xmm0, %ymm15, %ymm15 > > vinsertf32x4 $0x0, %xmm0, %ymm15, %ymm15 > > vinsertf32x4 $0x1, %xmm0, %ymm15, %ymm15 > > vinsertf64x2 $0x0, %xmm0, %ymm15, %ymm15 > > vinsertf64x2 $0x1, %xmm0, %ymm15, %ymm15 > > assembles fine, even when it IMHO should not - the 64x2 instructions > > are all AVX512VL & AVX512DQ. > > > > Since vinsertf64x2 is an CpuAVX512VL instruction, I don't see > why it shouldn't assemble. Is it? I believe only vinsertf32x4 is, vinsertf64x2 is CpuAVX512VL & CpuAVX512DQ: EVEX.NDS.256.66.0F3A.W0 18 /r ib T4 V/V AVX512VL Insert 128 bits of packed single-precision floating- VINSERTF32X4 ymm1 {k1}{z}, ymm2, AVX512F point values from xmm3/m128 and the remaining xmm3/m128, imm8 values from ymm2 into ymm1 under writemask k1. EVEX.NDS.512.66.0F3A.W0 18 /r ib T4 V/V AVX512F Insert 128 bits of packed single-precision floating- VINSERTF32X4 zmm1 {k1}{z}, zmm2, point values from xmm3/m128 and the remaining xmm3/m128, imm8 values from zmm2 into zmm1 under writemask k1. EVEX.NDS.256.66.0F3A.W1 18 /r ib T2 V/V AVX512VL Insert 128 bits of packed double-precision floating- VINSERTF64X2 ymm1 {k1}{z}, ymm2, AVX512DQ point values from xmm3/m128 and the remaining xmm3/m128, imm8 values from ymm2 into ymm1 under writemask k1. EVEX.NDS.512.66.0F3A.W1 18 /r ib T2 V/V AVX512DQ Insert 128 bits of packed double-precision floating- VINSERTF64X2 zmm1 {k1}{z}, zmm2, point values from xmm3/m128 and the remaining xmm3/m128, imm8 values from zmm2 into zmm1 under writemask k1. vinsertf64x2, 4, 0x6618, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM } At least in 319433-024.pdf I see in 5.1.5: The fourth column holds abbreviated CPUID feature flags (e.g. appropriate bits in CPUID.1:ECX, CPUID.1:EDX for SSE/SSE2/SSE3/SSSE3/SSE4.1/SSE4.2/AVX/F16C support; bits in CPUID.(EAX=07H,ECX=0):BCX for AVX2/AVX512F etc) that indicate processor support for the instruction. If the corresponding flag is ‘0’, the instruction will #UD. Therefore, my understanding is that you need all the mentioned flags enabled or it will #UD. Does binutils treat CpuAVX512DQ|CpuAVX512VL instead as the insn being enabled in either .arch .avx512vl, or .arch .avx512dq alone, rather than only in .arch .avx512vl; .arch .avx512dq ? Jakub ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH] Allow setting CpuVRex bit in .arch directive 2016-05-24 17:49 ` Jakub Jelinek @ 2016-05-24 19:02 ` H.J. Lu 2016-05-24 19:07 ` Jakub Jelinek 2016-05-25 23:22 ` H.J. Lu 0 siblings, 2 replies; 18+ messages in thread From: H.J. Lu @ 2016-05-24 19:02 UTC (permalink / raw) To: Jakub Jelinek; +Cc: Binutils, Uros Bizjak, Kirill Yukhin On Tue, May 24, 2016 at 10:49 AM, Jakub Jelinek <jakub@redhat.com> wrote: > On Tue, May 24, 2016 at 10:24:11AM -0700, H.J. Lu wrote: >> On Sat, May 21, 2016 at 10:06 AM, Jakub Jelinek <jakub@redhat.com> wrote: >> > Hi! >> > >> > On Sat, May 21, 2016 at 06:54:05PM +0200, Jakub Jelinek wrote: >> >> I've tried today to check for the various AVX512* ISA issues in GCC >> >> using assembly .arch support. Seems by default all flags (but l10m/k10m) >> >> are set, but if I want to allow all insns but say AVX512DQ ISA instructions >> >> or something similar, there is no way to do it - there is no way except >> >> for explicit no* flags to remove ISA bits from the default, so one has to >> >> set some CPU and then add all the ISA flags one wants. Seems most of them >> >> can be added, except for one very important one - the CpuVRex bit. >> >> >> >> Here is a patch to add support for .arch .vrex to set that, another option >> >> might be to set CpuVRex whenever CpuAVX512F is set in 64-bit mode. >> >> Any preferences? >> >> Do you have a testcase to show how CpuVRex is used? > > Try: > .arch corei7 > .arch .avx512f > vpxord %xmm15, %xmm15, %xmm15 > vpxord %xmm16, %xmm16, %xmm16 > > I get: > /tmp/1.s: Assembler messages: > /tmp/1.s:4: Error: bad register name `%xmm16' I opened: https://sourceware.org/bugzilla/show_bug.cgi?id=20141 > and couldn't find any way how to make that assemble if I want to > disable even some ISA set and thus have to start with .arch <cpuname> > and add all the ISA sets I want to enable on top of that CPU. So you want to just disable AVX512D, no thing else. Wouldn't a ".noarch" directive work better? >> > BTW, to my surprise, I haven't found any issues in the compiler this way, >> > even the known ones that I've just fixed. >> > E.g. >> > .arch corei7 >> > .arch .avx512f >> > .arch .avx512vl >> > vinserti32x4 $0x0, %xmm0, %ymm15, %ymm15 >> > vinserti32x4 $0x1, %xmm0, %ymm15, %ymm15 >> > vinserti64x2 $0x0, %xmm0, %ymm15, %ymm15 >> > vinserti64x2 $0x1, %xmm0, %ymm15, %ymm15 >> > vinsertf32x4 $0x0, %xmm0, %ymm15, %ymm15 >> > vinsertf32x4 $0x1, %xmm0, %ymm15, %ymm15 >> > vinsertf64x2 $0x0, %xmm0, %ymm15, %ymm15 >> > vinsertf64x2 $0x1, %xmm0, %ymm15, %ymm15 >> > assembles fine, even when it IMHO should not - the 64x2 instructions >> > are all AVX512VL & AVX512DQ. >> > >> >> Since vinsertf64x2 is an CpuAVX512VL instruction, I don't see >> why it shouldn't assemble. > > Is it? I believe only vinsertf32x4 is, vinsertf64x2 is > CpuAVX512VL & CpuAVX512DQ: > > EVEX.NDS.256.66.0F3A.W0 18 /r ib T4 V/V AVX512VL Insert 128 bits of packed single-precision floating- > VINSERTF32X4 ymm1 {k1}{z}, ymm2, AVX512F point values from xmm3/m128 and the remaining > xmm3/m128, imm8 values from ymm2 into ymm1 under writemask k1. > > EVEX.NDS.512.66.0F3A.W0 18 /r ib T4 V/V AVX512F Insert 128 bits of packed single-precision floating- > VINSERTF32X4 zmm1 {k1}{z}, zmm2, point values from xmm3/m128 and the remaining > xmm3/m128, imm8 values from zmm2 into zmm1 under writemask k1. > > EVEX.NDS.256.66.0F3A.W1 18 /r ib T2 V/V AVX512VL Insert 128 bits of packed double-precision floating- > VINSERTF64X2 ymm1 {k1}{z}, ymm2, AVX512DQ point values from xmm3/m128 and the remaining > xmm3/m128, imm8 values from ymm2 into ymm1 under writemask k1. > > EVEX.NDS.512.66.0F3A.W1 18 /r ib T2 V/V AVX512DQ Insert 128 bits of packed double-precision floating- > VINSERTF64X2 zmm1 {k1}{z}, zmm2, point values from xmm3/m128 and the remaining > xmm3/m128, imm8 values from zmm2 into zmm1 under writemask k1. > > vinsertf64x2, 4, 0x6618, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM } > > At least in 319433-024.pdf I see in 5.1.5: > > The fourth column holds abbreviated CPUID feature flags (e.g. appropriate > bits in CPUID.1:ECX, CPUID.1:EDX for SSE/SSE2/SSE3/SSSE3/SSE4.1/SSE4.2/AVX/F16C support; bits in > CPUID.(EAX=07H,ECX=0):BCX for AVX2/AVX512F etc) that indicate processor support for the instruction. If > the corresponding flag is ‘0’, the instruction will #UD. > > Therefore, my understanding is that you need all the mentioned flags enabled > or it will #UD. Does binutils treat CpuAVX512DQ|CpuAVX512VL instead > as the insn being enabled in either .arch .avx512vl, or .arch .avx512dq > alone, rather than only in .arch .avx512vl; .arch .avx512dq ? > I opened: https://sourceware.org/bugzilla/show_bug.cgi?id=20140 -- H.J. ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH] Allow setting CpuVRex bit in .arch directive 2016-05-24 19:02 ` H.J. Lu @ 2016-05-24 19:07 ` Jakub Jelinek 2016-05-24 20:36 ` H.J. Lu 2016-05-25 23:22 ` H.J. Lu 1 sibling, 1 reply; 18+ messages in thread From: Jakub Jelinek @ 2016-05-24 19:07 UTC (permalink / raw) To: H.J. Lu; +Cc: Binutils, Uros Bizjak, Kirill Yukhin On Tue, May 24, 2016 at 12:02:42PM -0700, H.J. Lu wrote: > > Try: > > .arch corei7 > > .arch .avx512f > > vpxord %xmm15, %xmm15, %xmm15 > > vpxord %xmm16, %xmm16, %xmm16 > > > > I get: > > /tmp/1.s: Assembler messages: > > /tmp/1.s:4: Error: bad register name `%xmm16' > > I opened: > > https://sourceware.org/bugzilla/show_bug.cgi?id=20141 > > > and couldn't find any way how to make that assemble if I want to > > disable even some ISA set and thus have to start with .arch <cpuname> > > and add all the ISA sets I want to enable on top of that CPU. > > So you want to just disable AVX512D, no thing else. Wouldn't a > ".noarch" directive work better? Well, to be able to generically disable specific ISAs (one, several). An alternative to .noarch would be just allowing .arch .noavx512vl etc. (like it already allows .no87). Perhaps instead of mentioning all the ISAs once again with "no" prefix just handle it generically, if .arch .no* is used, look first for entries with explicit no at the beginning, and if not found, look for the string after the prefix in the table and assume negate. Anyway, still it would be good to be able to change (both set and remove) the CpuVRex bit. Jakub ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH] Allow setting CpuVRex bit in .arch directive 2016-05-24 19:07 ` Jakub Jelinek @ 2016-05-24 20:36 ` H.J. Lu 2016-05-25 16:35 ` H.J. Lu 2016-05-25 17:54 ` H.J. Lu 0 siblings, 2 replies; 18+ messages in thread From: H.J. Lu @ 2016-05-24 20:36 UTC (permalink / raw) To: Jakub Jelinek; +Cc: Binutils, Uros Bizjak, Kirill Yukhin On Tue, May 24, 2016 at 12:07 PM, Jakub Jelinek <jakub@redhat.com> wrote: > On Tue, May 24, 2016 at 12:02:42PM -0700, H.J. Lu wrote: >> > Try: >> > .arch corei7 >> > .arch .avx512f >> > vpxord %xmm15, %xmm15, %xmm15 >> > vpxord %xmm16, %xmm16, %xmm16 >> > >> > I get: >> > /tmp/1.s: Assembler messages: >> > /tmp/1.s:4: Error: bad register name `%xmm16' >> >> I opened: >> >> https://sourceware.org/bugzilla/show_bug.cgi?id=20141 >> >> > and couldn't find any way how to make that assemble if I want to >> > disable even some ISA set and thus have to start with .arch <cpuname> >> > and add all the ISA sets I want to enable on top of that CPU. >> >> So you want to just disable AVX512D, no thing else. Wouldn't a >> ".noarch" directive work better? > > Well, to be able to generically disable specific ISAs (one, several). > An alternative to .noarch would be just allowing > .arch .noavx512vl etc. (like it already allows .no87). > Perhaps instead of mentioning all the ISAs once again with "no" prefix > just handle it generically, if .arch .no* is used, look first for > entries with explicit no at the beginning, and if not found, look for > the string after the prefix in the table and assume negate. Yes, it should work. > Anyway, still it would be good to be able to change (both set and remove) > the CpuVRex bit. > CpuVRex should be cleared/set automatically based on ISA. -- H.J. ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH] Allow setting CpuVRex bit in .arch directive 2016-05-24 20:36 ` H.J. Lu @ 2016-05-25 16:35 ` H.J. Lu 2016-05-25 17:26 ` H.J. Lu 2016-05-25 17:54 ` H.J. Lu 1 sibling, 1 reply; 18+ messages in thread From: H.J. Lu @ 2016-05-25 16:35 UTC (permalink / raw) To: Jakub Jelinek; +Cc: Binutils, Uros Bizjak, Kirill Yukhin [-- Attachment #1: Type: text/plain, Size: 1576 bytes --] On Tue, May 24, 2016 at 1:36 PM, H.J. Lu <hjl.tools@gmail.com> wrote: > On Tue, May 24, 2016 at 12:07 PM, Jakub Jelinek <jakub@redhat.com> wrote: >> On Tue, May 24, 2016 at 12:02:42PM -0700, H.J. Lu wrote: >>> > Try: >>> > .arch corei7 >>> > .arch .avx512f >>> > vpxord %xmm15, %xmm15, %xmm15 >>> > vpxord %xmm16, %xmm16, %xmm16 >>> > >>> > I get: >>> > /tmp/1.s: Assembler messages: >>> > /tmp/1.s:4: Error: bad register name `%xmm16' >>> >>> I opened: >>> >>> https://sourceware.org/bugzilla/show_bug.cgi?id=20141 >>> >>> > and couldn't find any way how to make that assemble if I want to >>> > disable even some ISA set and thus have to start with .arch <cpuname> >>> > and add all the ISA sets I want to enable on top of that CPU. >>> >>> So you want to just disable AVX512D, no thing else. Wouldn't a >>> ".noarch" directive work better? >> >> Well, to be able to generically disable specific ISAs (one, several). >> An alternative to .noarch would be just allowing >> .arch .noavx512vl etc. (like it already allows .no87). >> Perhaps instead of mentioning all the ISAs once again with "no" prefix >> just handle it generically, if .arch .no* is used, look first for >> entries with explicit no at the beginning, and if not found, look for >> the string after the prefix in the table and assume negate. > > Yes, it should work. It won't work since .noavx should disable all AVX instructions, just just AVX. I am going to check in this patch to move all .noXXX directives to cpu_noarch. We can add more .noXXX to cpu_noarch. -- H.J. [-- Attachment #2: 0001-Reimplement-.no87-.nommx-.nosse-.noavx-directives.patch --] [-- Type: text/x-patch, Size: 30865 bytes --] From aea4cf9db554229cfd1445813df2cf05e5d650d1 Mon Sep 17 00:00:00 2001 From: "H.J. Lu" <hjl.tools@gmail.com> Date: Tue, 24 May 2016 14:50:01 -0700 Subject: [PATCH] Reimplement .no87/.nommx/.nosse/.noavx directives Move all .noXXX directives to cpu_noarch. gas/ * config/tc-i386.c (arch_entry): Remove negated. (noarch_entry): New struct. (cpu_arch): Updated. Remove .no87, .nommx, .nosse and .noavx. (cpu_noarch): New. (set_cpu_arch): Check cpu_noarch after cpu_arch. (md_parse_option): Allow -march=+nosse. Check cpu_noarch after cpu_arch. (output_message): New function. (show_arch): Use it. Handle cpu_noarch. * testsuite/gas/i386/i386.exp: Run nommx-1, nommx-2, nommx-3, nosse-1, nosse-2, nosse-3, noavx-1 and noavx-2. * testsuite/gas/i386/noavx-1.l: New file. * testsuite/gas/i386/noavx-1.s: Likewise. * testsuite/gas/i386/noavx-2.s: Likewise. * testsuite/gas/i386/noavx-2.l: Likewise. * testsuite/gas/i386/nommx-1.s: Likewise. * testsuite/gas/i386/nommx-1.l: Likewise. * testsuite/gas/i386/nommx-2.s: Likewise. * testsuite/gas/i386/nommx-2.l: Likewise. * testsuite/gas/i386/nommx-3.s: Likewise. * testsuite/gas/i386/nommx-3.l: Likewise. * testsuite/gas/i386/nosse-1.s: Likewise. * testsuite/gas/i386/nosse-1.l: Likewise. * testsuite/gas/i386/nosse-2.s: Likewise. * testsuite/gas/i386/nosse-2.l: Likewise. * testsuite/gas/i386/nosse-3.s: Likewise. * testsuite/gas/i386/nosse-3.l: Likewise. opcodes/ * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS. * i386-init.h: Regenerated. --- gas/config/tc-i386.c | 410 ++++++++++++++++++++++++--------------- gas/testsuite/gas/i386/i386.exp | 8 + gas/testsuite/gas/i386/noavx-1.l | 13 ++ gas/testsuite/gas/i386/noavx-1.s | 8 + gas/testsuite/gas/i386/noavx-2.l | 7 + gas/testsuite/gas/i386/noavx-2.s | 3 + gas/testsuite/gas/i386/nommx-1.l | 21 ++ gas/testsuite/gas/i386/nommx-1.s | 14 ++ gas/testsuite/gas/i386/nommx-2.l | 7 + gas/testsuite/gas/i386/nommx-2.s | 3 + gas/testsuite/gas/i386/nommx-3.l | 7 + gas/testsuite/gas/i386/nommx-3.s | 3 + gas/testsuite/gas/i386/nosse-1.l | 13 ++ gas/testsuite/gas/i386/nosse-1.s | 8 + gas/testsuite/gas/i386/nosse-2.l | 7 + gas/testsuite/gas/i386/nosse-2.s | 3 + gas/testsuite/gas/i386/nosse-3.l | 7 + gas/testsuite/gas/i386/nosse-3.s | 3 + opcodes/i386-gen.c | 4 +- opcodes/i386-init.h | 9 +- 20 files changed, 396 insertions(+), 162 deletions(-) create mode 100644 gas/testsuite/gas/i386/noavx-1.l create mode 100644 gas/testsuite/gas/i386/noavx-1.s create mode 100644 gas/testsuite/gas/i386/noavx-2.l create mode 100644 gas/testsuite/gas/i386/noavx-2.s create mode 100644 gas/testsuite/gas/i386/nommx-1.l create mode 100644 gas/testsuite/gas/i386/nommx-1.s create mode 100644 gas/testsuite/gas/i386/nommx-2.l create mode 100644 gas/testsuite/gas/i386/nommx-2.s create mode 100644 gas/testsuite/gas/i386/nommx-3.l create mode 100644 gas/testsuite/gas/i386/nommx-3.s create mode 100644 gas/testsuite/gas/i386/nosse-1.l create mode 100644 gas/testsuite/gas/i386/nosse-1.s create mode 100644 gas/testsuite/gas/i386/nosse-2.l create mode 100644 gas/testsuite/gas/i386/nosse-2.s create mode 100644 gas/testsuite/gas/i386/nosse-3.l create mode 100644 gas/testsuite/gas/i386/nosse-3.s diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 8a4d987..21e300f 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -133,10 +133,18 @@ typedef struct enum processor_type type; /* arch type */ i386_cpu_flags flags; /* cpu feature flags */ unsigned int skip; /* show_arch should skip this. */ - unsigned int negated; /* turn off indicated flags. */ } arch_entry; +/* Used to turn off indicated flags. */ +typedef struct +{ + const char *name; /* arch name */ + unsigned int len; /* arch string length */ + i386_cpu_flags flags; /* cpu feature flags */ +} +noarch_entry; + static void update_code_flag (int, int); static void set_code_flag (int); static void set_16bit_gcc_code_flag (int); @@ -730,239 +738,239 @@ static const arch_entry cpu_arch[] = /* Do not replace the first two entries - i386_target_format() relies on them being there in this order. */ { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32, - CPU_GENERIC32_FLAGS, 0, 0 }, + CPU_GENERIC32_FLAGS, 0 }, { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64, - CPU_GENERIC64_FLAGS, 0, 0 }, + CPU_GENERIC64_FLAGS, 0 }, { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN, - CPU_NONE_FLAGS, 0, 0 }, + CPU_NONE_FLAGS, 0 }, { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN, - CPU_I186_FLAGS, 0, 0 }, + CPU_I186_FLAGS, 0 }, { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN, - CPU_I286_FLAGS, 0, 0 }, + CPU_I286_FLAGS, 0 }, { STRING_COMMA_LEN ("i386"), PROCESSOR_I386, - CPU_I386_FLAGS, 0, 0 }, + CPU_I386_FLAGS, 0 }, { STRING_COMMA_LEN ("i486"), PROCESSOR_I486, - CPU_I486_FLAGS, 0, 0 }, + CPU_I486_FLAGS, 0 }, { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM, - CPU_I586_FLAGS, 0, 0 }, + CPU_I586_FLAGS, 0 }, { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO, - CPU_I686_FLAGS, 0, 0 }, + CPU_I686_FLAGS, 0 }, { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM, - CPU_I586_FLAGS, 0, 0 }, + CPU_I586_FLAGS, 0 }, { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO, - CPU_PENTIUMPRO_FLAGS, 0, 0 }, + CPU_PENTIUMPRO_FLAGS, 0 }, { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO, - CPU_P2_FLAGS, 0, 0 }, + CPU_P2_FLAGS, 0 }, { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO, - CPU_P3_FLAGS, 0, 0 }, + CPU_P3_FLAGS, 0 }, { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4, - CPU_P4_FLAGS, 0, 0 }, + CPU_P4_FLAGS, 0 }, { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA, - CPU_CORE_FLAGS, 0, 0 }, + CPU_CORE_FLAGS, 0 }, { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA, - CPU_NOCONA_FLAGS, 0, 0 }, + CPU_NOCONA_FLAGS, 0 }, { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE, - CPU_CORE_FLAGS, 1, 0 }, + CPU_CORE_FLAGS, 1 }, { STRING_COMMA_LEN ("core"), PROCESSOR_CORE, - CPU_CORE_FLAGS, 0, 0 }, + CPU_CORE_FLAGS, 0 }, { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2, - CPU_CORE2_FLAGS, 1, 0 }, + CPU_CORE2_FLAGS, 1 }, { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2, - CPU_CORE2_FLAGS, 0, 0 }, + CPU_CORE2_FLAGS, 0 }, { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7, - CPU_COREI7_FLAGS, 0, 0 }, + CPU_COREI7_FLAGS, 0 }, { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM, - CPU_L1OM_FLAGS, 0, 0 }, + CPU_L1OM_FLAGS, 0 }, { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM, - CPU_K1OM_FLAGS, 0, 0 }, + CPU_K1OM_FLAGS, 0 }, { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU, - CPU_IAMCU_FLAGS, 0, 0 }, + CPU_IAMCU_FLAGS, 0 }, { STRING_COMMA_LEN ("k6"), PROCESSOR_K6, - CPU_K6_FLAGS, 0, 0 }, + CPU_K6_FLAGS, 0 }, { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6, - CPU_K6_2_FLAGS, 0, 0 }, + CPU_K6_2_FLAGS, 0 }, { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON, - CPU_ATHLON_FLAGS, 0, 0 }, + CPU_ATHLON_FLAGS, 0 }, { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8, - CPU_K8_FLAGS, 1, 0 }, + CPU_K8_FLAGS, 1 }, { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8, - CPU_K8_FLAGS, 0, 0 }, + CPU_K8_FLAGS, 0 }, { STRING_COMMA_LEN ("k8"), PROCESSOR_K8, - CPU_K8_FLAGS, 0, 0 }, + CPU_K8_FLAGS, 0 }, { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10, - CPU_AMDFAM10_FLAGS, 0, 0 }, + CPU_AMDFAM10_FLAGS, 0 }, { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD, - CPU_BDVER1_FLAGS, 0, 0 }, + CPU_BDVER1_FLAGS, 0 }, { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD, - CPU_BDVER2_FLAGS, 0, 0 }, + CPU_BDVER2_FLAGS, 0 }, { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD, - CPU_BDVER3_FLAGS, 0, 0 }, + CPU_BDVER3_FLAGS, 0 }, { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD, - CPU_BDVER4_FLAGS, 0, 0 }, + CPU_BDVER4_FLAGS, 0 }, { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER, - CPU_ZNVER1_FLAGS, 0, 0 }, + CPU_ZNVER1_FLAGS, 0 }, { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT, - CPU_BTVER1_FLAGS, 0, 0 }, + CPU_BTVER1_FLAGS, 0 }, { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT, - CPU_BTVER2_FLAGS, 0, 0 }, + CPU_BTVER2_FLAGS, 0 }, { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN, - CPU_8087_FLAGS, 0, 0 }, + CPU_8087_FLAGS, 0 }, { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN, - CPU_287_FLAGS, 0, 0 }, + CPU_287_FLAGS, 0 }, { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN, - CPU_387_FLAGS, 0, 0 }, - { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN, - CPU_ANY87_FLAGS, 0, 1 }, + CPU_387_FLAGS, 0 }, { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN, - CPU_MMX_FLAGS, 0, 0 }, - { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN, - CPU_3DNOWA_FLAGS, 0, 1 }, + CPU_MMX_FLAGS, 0 }, { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN, - CPU_SSE_FLAGS, 0, 0 }, + CPU_SSE_FLAGS, 0 }, { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN, - CPU_SSE2_FLAGS, 0, 0 }, + CPU_SSE2_FLAGS, 0 }, { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN, - CPU_SSE3_FLAGS, 0, 0 }, + CPU_SSE3_FLAGS, 0 }, { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN, - CPU_SSSE3_FLAGS, 0, 0 }, + CPU_SSSE3_FLAGS, 0 }, { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN, - CPU_SSE4_1_FLAGS, 0, 0 }, + CPU_SSE4_1_FLAGS, 0 }, { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN, - CPU_SSE4_2_FLAGS, 0, 0 }, + CPU_SSE4_2_FLAGS, 0 }, { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN, - CPU_SSE4_2_FLAGS, 0, 0 }, - { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN, - CPU_ANY_SSE_FLAGS, 0, 1 }, + CPU_SSE4_2_FLAGS, 0 }, { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN, - CPU_AVX_FLAGS, 0, 0 }, + CPU_AVX_FLAGS, 0 }, { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN, - CPU_AVX2_FLAGS, 0, 0 }, + CPU_AVX2_FLAGS, 0 }, { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN, - CPU_AVX512F_FLAGS, 0, 0 }, + CPU_AVX512F_FLAGS, 0 }, { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN, - CPU_AVX512CD_FLAGS, 0, 0 }, + CPU_AVX512CD_FLAGS, 0 }, { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN, - CPU_AVX512ER_FLAGS, 0, 0 }, + CPU_AVX512ER_FLAGS, 0 }, { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN, - CPU_AVX512PF_FLAGS, 0, 0 }, + CPU_AVX512PF_FLAGS, 0 }, { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN, - CPU_AVX512DQ_FLAGS, 0, 0 }, + CPU_AVX512DQ_FLAGS, 0 }, { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN, - CPU_AVX512BW_FLAGS, 0, 0 }, + CPU_AVX512BW_FLAGS, 0 }, { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN, - CPU_AVX512VL_FLAGS, 0, 0 }, - { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN, - CPU_ANY_AVX_FLAGS, 0, 1 }, + CPU_AVX512VL_FLAGS, 0 }, { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN, - CPU_VMX_FLAGS, 0, 0 }, + CPU_VMX_FLAGS, 0 }, { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN, - CPU_VMFUNC_FLAGS, 0, 0 }, + CPU_VMFUNC_FLAGS, 0 }, { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN, - CPU_SMX_FLAGS, 0, 0 }, + CPU_SMX_FLAGS, 0 }, { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN, - CPU_XSAVE_FLAGS, 0, 0 }, + CPU_XSAVE_FLAGS, 0 }, { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN, - CPU_XSAVEOPT_FLAGS, 0, 0 }, + CPU_XSAVEOPT_FLAGS, 0 }, { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN, - CPU_XSAVEC_FLAGS, 0, 0 }, + CPU_XSAVEC_FLAGS, 0 }, { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN, - CPU_XSAVES_FLAGS, 0, 0 }, + CPU_XSAVES_FLAGS, 0 }, { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN, - CPU_AES_FLAGS, 0, 0 }, + CPU_AES_FLAGS, 0 }, { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN, - CPU_PCLMUL_FLAGS, 0, 0 }, + CPU_PCLMUL_FLAGS, 0 }, { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN, - CPU_PCLMUL_FLAGS, 1, 0 }, + CPU_PCLMUL_FLAGS, 1 }, { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN, - CPU_FSGSBASE_FLAGS, 0, 0 }, + CPU_FSGSBASE_FLAGS, 0 }, { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN, - CPU_RDRND_FLAGS, 0, 0 }, + CPU_RDRND_FLAGS, 0 }, { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN, - CPU_F16C_FLAGS, 0, 0 }, + CPU_F16C_FLAGS, 0 }, { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN, - CPU_BMI2_FLAGS, 0, 0 }, + CPU_BMI2_FLAGS, 0 }, { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN, - CPU_FMA_FLAGS, 0, 0 }, + CPU_FMA_FLAGS, 0 }, { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN, - CPU_FMA4_FLAGS, 0, 0 }, + CPU_FMA4_FLAGS, 0 }, { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN, - CPU_XOP_FLAGS, 0, 0 }, + CPU_XOP_FLAGS, 0 }, { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN, - CPU_LWP_FLAGS, 0, 0 }, + CPU_LWP_FLAGS, 0 }, { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN, - CPU_MOVBE_FLAGS, 0, 0 }, + CPU_MOVBE_FLAGS, 0 }, { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN, - CPU_CX16_FLAGS, 0, 0 }, + CPU_CX16_FLAGS, 0 }, { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN, - CPU_EPT_FLAGS, 0, 0 }, + CPU_EPT_FLAGS, 0 }, { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN, - CPU_LZCNT_FLAGS, 0, 0 }, + CPU_LZCNT_FLAGS, 0 }, { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN, - CPU_HLE_FLAGS, 0, 0 }, + CPU_HLE_FLAGS, 0 }, { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN, - CPU_RTM_FLAGS, 0, 0 }, + CPU_RTM_FLAGS, 0 }, { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN, - CPU_INVPCID_FLAGS, 0, 0 }, + CPU_INVPCID_FLAGS, 0 }, { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN, - CPU_CLFLUSH_FLAGS, 0, 0 }, + CPU_CLFLUSH_FLAGS, 0 }, { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN, - CPU_NOP_FLAGS, 0, 0 }, + CPU_NOP_FLAGS, 0 }, { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN, - CPU_SYSCALL_FLAGS, 0, 0 }, + CPU_SYSCALL_FLAGS, 0 }, { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN, - CPU_RDTSCP_FLAGS, 0, 0 }, + CPU_RDTSCP_FLAGS, 0 }, { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN, - CPU_3DNOW_FLAGS, 0, 0 }, + CPU_3DNOW_FLAGS, 0 }, { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN, - CPU_3DNOWA_FLAGS, 0, 0 }, + CPU_3DNOWA_FLAGS, 0 }, { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN, - CPU_PADLOCK_FLAGS, 0, 0 }, + CPU_PADLOCK_FLAGS, 0 }, { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN, - CPU_SVME_FLAGS, 1, 0 }, + CPU_SVME_FLAGS, 1 }, { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN, - CPU_SVME_FLAGS, 0, 0 }, + CPU_SVME_FLAGS, 0 }, { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN, - CPU_SSE4A_FLAGS, 0, 0 }, + CPU_SSE4A_FLAGS, 0 }, { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN, - CPU_ABM_FLAGS, 0, 0 }, + CPU_ABM_FLAGS, 0 }, { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN, - CPU_BMI_FLAGS, 0, 0 }, + CPU_BMI_FLAGS, 0 }, { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN, - CPU_TBM_FLAGS, 0, 0 }, + CPU_TBM_FLAGS, 0 }, { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN, - CPU_ADX_FLAGS, 0, 0 }, + CPU_ADX_FLAGS, 0 }, { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN, - CPU_RDSEED_FLAGS, 0, 0 }, + CPU_RDSEED_FLAGS, 0 }, { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN, - CPU_PRFCHW_FLAGS, 0, 0 }, + CPU_PRFCHW_FLAGS, 0 }, { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN, - CPU_SMAP_FLAGS, 0, 0 }, + CPU_SMAP_FLAGS, 0 }, { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN, - CPU_MPX_FLAGS, 0, 0 }, + CPU_MPX_FLAGS, 0 }, { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN, - CPU_SHA_FLAGS, 0, 0 }, + CPU_SHA_FLAGS, 0 }, { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN, - CPU_CLFLUSHOPT_FLAGS, 0, 0 }, + CPU_CLFLUSHOPT_FLAGS, 0 }, { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN, - CPU_PREFETCHWT1_FLAGS, 0, 0 }, + CPU_PREFETCHWT1_FLAGS, 0 }, { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN, - CPU_SE1_FLAGS, 0, 0 }, + CPU_SE1_FLAGS, 0 }, { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN, - CPU_CLWB_FLAGS, 0, 0 }, + CPU_CLWB_FLAGS, 0 }, { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN, - CPU_PCOMMIT_FLAGS, 0, 0 }, + CPU_PCOMMIT_FLAGS, 0 }, { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN, - CPU_AVX512IFMA_FLAGS, 0, 0 }, + CPU_AVX512IFMA_FLAGS, 0 }, { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN, - CPU_AVX512VBMI_FLAGS, 0, 0 }, + CPU_AVX512VBMI_FLAGS, 0 }, { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN, - CPU_CLZERO_FLAGS, 0, 0 }, + CPU_CLZERO_FLAGS, 0 }, { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN, - CPU_MWAITX_FLAGS, 0, 0 }, + CPU_MWAITX_FLAGS, 0 }, { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN, - CPU_OSPKE_FLAGS, 0, 0 }, + CPU_OSPKE_FLAGS, 0 }, { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN, - CPU_RDPID_FLAGS, 0, 0 }, + CPU_RDPID_FLAGS, 0 }, +}; + +static const noarch_entry cpu_noarch[] = +{ + { STRING_COMMA_LEN (".no87"), CPU_ANY_X87_FLAGS }, + { STRING_COMMA_LEN (".nommx"), CPU_ANY_MMX_FLAGS }, + { STRING_COMMA_LEN (".nosse"), CPU_ANY_SSE_FLAGS }, + { STRING_COMMA_LEN (".noavx"), CPU_ANY_AVX_FLAGS }, }; #ifdef I386COFF @@ -2370,12 +2378,8 @@ set_cpu_arch (int dummy ATTRIBUTE_UNUSED) break; } - if (!cpu_arch[j].negated) - flags = cpu_flags_or (cpu_arch_flags, - cpu_arch[j].flags); - else - flags = cpu_flags_and_not (cpu_arch_flags, - cpu_arch[j].flags); + flags = cpu_flags_or (cpu_arch_flags, + cpu_arch[j].flags); if (!valid_iamcu_cpu_flags (&flags)) as_fatal (_("`%s' isn't valid for Intel MCU"), @@ -2400,6 +2404,38 @@ set_cpu_arch (int dummy ATTRIBUTE_UNUSED) return; } } + + if (j >= ARRAY_SIZE (cpu_arch)) + { + /* Disable an ISA entension. */ + for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) + if (strcmp (string, cpu_noarch [j].name) == 0) + { + flags = cpu_flags_and_not (cpu_arch_flags, + cpu_noarch[j].flags); + if (!cpu_flags_equal (&flags, &cpu_arch_flags)) + { + if (cpu_sub_arch_name) + { + char *name = cpu_sub_arch_name; + cpu_sub_arch_name = concat (name, + cpu_noarch[j].name, + (const char *) NULL); + free (name); + } + else + cpu_sub_arch_name = xstrdup (cpu_noarch[j].name); + cpu_arch_flags = flags; + cpu_arch_isa_flags = flags; + } + (void) restore_line_pointer (e); + demand_empty_rest_of_line (); + return; + } + + j = ARRAY_SIZE (cpu_arch); + } + if (j >= ARRAY_SIZE (cpu_arch)) as_bad (_("no such architecture: `%s'"), string); @@ -9805,6 +9841,9 @@ md_parse_option (int c, const char *arg) case OPTION_MARCH: arch = xstrdup (arg); + /* Allow -march=+nosse. */ + if (*arch == '+') + arch++; do { if (*arch == '.') @@ -9838,12 +9877,8 @@ md_parse_option (int c, const char *arg) /* ISA entension. */ i386_cpu_flags flags; - if (!cpu_arch[j].negated) - flags = cpu_flags_or (cpu_arch_flags, - cpu_arch[j].flags); - else - flags = cpu_flags_and_not (cpu_arch_flags, - cpu_arch[j].flags); + flags = cpu_flags_or (cpu_arch_flags, + cpu_arch[j].flags); if (!valid_iamcu_cpu_flags (&flags)) as_fatal (_("`%s' isn't valid for Intel MCU"), arch); @@ -9867,6 +9902,38 @@ md_parse_option (int c, const char *arg) } if (j >= ARRAY_SIZE (cpu_arch)) + { + /* Disable an ISA entension. */ + for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) + if (*cpu_noarch [j].name == '.' + && strcmp (arch, cpu_noarch [j].name + 1) == 0) + { + i386_cpu_flags flags; + + flags = cpu_flags_and_not (cpu_arch_flags, + cpu_noarch[j].flags); + if (!cpu_flags_equal (&flags, &cpu_arch_flags)) + { + if (cpu_sub_arch_name) + { + char *name = cpu_sub_arch_name; + cpu_sub_arch_name = concat (cpu_noarch[j].name + 1, + (const char *) NULL); + free (name); + } + else + cpu_sub_arch_name = xstrdup (cpu_noarch[j].name); + cpu_arch_flags = flags; + cpu_arch_isa_flags = flags; + } + break; + } + + if (j >= ARRAY_SIZE (cpu_noarch)) + j = ARRAY_SIZE (cpu_arch); + } + + if (j >= ARRAY_SIZE (cpu_arch)) as_fatal (_("invalid -march= option: `%s'"), arg); arch = next; @@ -10049,6 +10116,44 @@ md_parse_option (int c, const char *arg) #define MESSAGE_TEMPLATE \ " " +static char * +output_message (FILE *stream, char *p, char *message, char *start, + int *left_p, const char *name, int len) +{ + int size = sizeof (MESSAGE_TEMPLATE); + int left = *left_p; + + /* Reserve 2 spaces for ", " or ",\0" */ + left -= len + 2; + + /* Check if there is any room. */ + if (left >= 0) + { + if (p != start) + { + *p++ = ','; + *p++ = ' '; + } + p = mempcpy (p, name, len); + } + else + { + /* Output the current message now and start a new one. */ + *p++ = ','; + *p = '\0'; + fprintf (stream, "%s\n", message); + p = start; + left = size - (start - message) - len - 2; + + gas_assert (left >= 0); + + p = mempcpy (p, name, len); + } + + *left_p = left; + return p; +} + static void show_arch (FILE *stream, int ext, int check) { @@ -10093,34 +10198,19 @@ show_arch (FILE *stream, int ext, int check) continue; } - /* Reserve 2 spaces for ", " or ",\0" */ - left -= len + 2; - - /* Check if there is any room. */ - if (left >= 0) - { - if (p != start) - { - *p++ = ','; - *p++ = ' '; - } - p = mempcpy (p, name, len); - } - else - { - /* Output the current message now and start a new one. */ - *p++ = ','; - *p = '\0'; - fprintf (stream, "%s\n", message); - p = start; - left = size - (start - message) - len - 2; - - gas_assert (left >= 0); - - p = mempcpy (p, name, len); - } + p = output_message (stream, p, message, start, &left, name, len); } + /* Display extensions. */ + if (ext) + for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) + { + name = cpu_noarch [j].name + 1; + len = cpu_noarch [j].len - 1; + p = output_message (stream, p, message, start, &left, name, + len); + } + *p = '\0'; fprintf (stream, "%s\n", message); } diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index a18200e..716ec43 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -165,6 +165,14 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]] run_dump_test "387" run_list_test "no87" "-al" run_list_test "no87-2" "-march=i686+no87 -al" + run_list_test "nommx-1" "-al" + run_list_test "nommx-2" "-march=core+nommx -al" + run_list_test "nommx-3" "-march=+nommx -al" + run_list_test "nosse-1" "-al" + run_list_test "nosse-2" "-march=core+nosse -al" + run_list_test "nosse-3" "-march=+nosse -al" + run_list_test "noavx-1" "-al" + run_list_test "noavx-2" "-march=+noavx -al" run_dump_test "xsave" run_dump_test "xsave-intel" run_dump_test "aes" diff --git a/gas/testsuite/gas/i386/noavx-1.l b/gas/testsuite/gas/i386/noavx-1.l new file mode 100644 index 0000000..f4e2840 --- /dev/null +++ b/gas/testsuite/gas/i386/noavx-1.l @@ -0,0 +1,13 @@ +.*: Assembler messages: +.*:4: Error: .*generic.* +.*:8: Error: .*noavx.* +GAS LISTING .* +#... +[ ]*1[ ]+\# Test \.arch \.noavx +[ ]*2[ ]+\.text +[ ]*3[ ]+\.arch generic32 +[ ]*4[ ]+vzeroupper +[ ]*5[ ]+\.arch \.avx +[ ]*6[ ]+\?\?\?\? C5F877 vzeroupper +[ ]*7[ ]+\.arch \.noavx +[ ]*8[ ]+vzeroupper diff --git a/gas/testsuite/gas/i386/noavx-1.s b/gas/testsuite/gas/i386/noavx-1.s new file mode 100644 index 0000000..759b429 --- /dev/null +++ b/gas/testsuite/gas/i386/noavx-1.s @@ -0,0 +1,8 @@ +# Test .arch .noavx + .text + .arch generic32 + vzeroupper + .arch .avx + vzeroupper + .arch .noavx + vzeroupper diff --git a/gas/testsuite/gas/i386/noavx-2.l b/gas/testsuite/gas/i386/noavx-2.l new file mode 100644 index 0000000..32cc140 --- /dev/null +++ b/gas/testsuite/gas/i386/noavx-2.l @@ -0,0 +1,7 @@ +.*: Assembler messages: +.*:3: Error: .*noavx.* +GAS LISTING .* +#... +[ ]*1[ ]+\# Test -march=\+noavx +[ ]*2[ ]+\.text +[ ]*3[ ]+vzeroupper diff --git a/gas/testsuite/gas/i386/noavx-2.s b/gas/testsuite/gas/i386/noavx-2.s new file mode 100644 index 0000000..82ffa3e --- /dev/null +++ b/gas/testsuite/gas/i386/noavx-2.s @@ -0,0 +1,3 @@ +# Test -march=+noavx + .text + vzeroupper diff --git a/gas/testsuite/gas/i386/nommx-1.l b/gas/testsuite/gas/i386/nommx-1.l new file mode 100644 index 0000000..2b7a6ca --- /dev/null +++ b/gas/testsuite/gas/i386/nommx-1.l @@ -0,0 +1,21 @@ +.*: Assembler messages: +.*:4: Error: .*generic.* +.*:7: Error: .*mmx.* +.*:10: Error: .*3dnow.* +.*:14: Error: .*nommx.* +GAS LISTING .* +#... +[ ]*1[ ]+\# Test \.arch \.nommx +[ ]*2[ ]+\.text +[ ]*3[ ]+\.arch generic32 +[ ]*4[ ]+emms +[ ]*5[ ]+\.arch \.mmx +[ ]*6[ ]+\?\?\?\? 0F7EC0 movd %mm0, %eax +[ ]*7[ ]+femms +[ ]*8[ ]+\.arch \.3dnow +[ ]*9[ ]+\?\?\?\? 0F0E femms +[ ]*10[ ]+pswapd %mm1,%mm0 +[ ]*11[ ]+\.arch \.3dnowa +[ ]*12[ ]+\?\?\?\? 0F0FC1BB pswapd %mm1,%mm0 +[ ]*13[ ]+\.arch \.nommx +[ ]*14[ ]+emms diff --git a/gas/testsuite/gas/i386/nommx-1.s b/gas/testsuite/gas/i386/nommx-1.s new file mode 100644 index 0000000..f87edda --- /dev/null +++ b/gas/testsuite/gas/i386/nommx-1.s @@ -0,0 +1,14 @@ +# Test .arch .nommx + .text + .arch generic32 + emms + .arch .mmx + movd %mm0, %eax + femms + .arch .3dnow + femms + pswapd %mm1,%mm0 + .arch .3dnowa + pswapd %mm1,%mm0 + .arch .nommx + emms diff --git a/gas/testsuite/gas/i386/nommx-2.l b/gas/testsuite/gas/i386/nommx-2.l new file mode 100644 index 0000000..a94b0a8 --- /dev/null +++ b/gas/testsuite/gas/i386/nommx-2.l @@ -0,0 +1,7 @@ +.*: Assembler messages: +.*:3: Error: .*nommx.* +GAS LISTING .* +#... +[ ]*1[ ]+\# Test -march=\.\.\.\+nommx +[ ]*2[ ]+\.text +[ ]*3[ ]+emms diff --git a/gas/testsuite/gas/i386/nommx-2.s b/gas/testsuite/gas/i386/nommx-2.s new file mode 100644 index 0000000..266ab8d --- /dev/null +++ b/gas/testsuite/gas/i386/nommx-2.s @@ -0,0 +1,3 @@ +# Test -march=...+nommx + .text + emms diff --git a/gas/testsuite/gas/i386/nommx-3.l b/gas/testsuite/gas/i386/nommx-3.l new file mode 100644 index 0000000..0d2e1f1 --- /dev/null +++ b/gas/testsuite/gas/i386/nommx-3.l @@ -0,0 +1,7 @@ +.*: Assembler messages: +.*:3: Error: .*nommx.* +GAS LISTING .* +#... +[ ]*1[ ]+\# Test -march=\+nommx +[ ]*2[ ]+\.text +[ ]*3[ ]+emms diff --git a/gas/testsuite/gas/i386/nommx-3.s b/gas/testsuite/gas/i386/nommx-3.s new file mode 100644 index 0000000..4641c1d --- /dev/null +++ b/gas/testsuite/gas/i386/nommx-3.s @@ -0,0 +1,3 @@ +# Test -march=+nommx + .text + emms diff --git a/gas/testsuite/gas/i386/nosse-1.l b/gas/testsuite/gas/i386/nosse-1.l new file mode 100644 index 0000000..486241b --- /dev/null +++ b/gas/testsuite/gas/i386/nosse-1.l @@ -0,0 +1,13 @@ +.*: Assembler messages: +.*:4: Error: .*generic.* +.*:8: Error: .*nosse.* +GAS LISTING .* +#... +[ ]*1[ ]+\# Test \.arch \.nosse +[ ]*2[ ]+\.text +[ ]*3[ ]+\.arch generic32 +[ ]*4[ ]+lfence +[ ]*5[ ]+\.arch \.sse2 +[ ]*6[ ]+\?\?\?\? 0FAEE8 lfence +[ ]*7[ ]+\.arch \.nosse +[ ]*8[ ]+lfence diff --git a/gas/testsuite/gas/i386/nosse-1.s b/gas/testsuite/gas/i386/nosse-1.s new file mode 100644 index 0000000..27f2528 --- /dev/null +++ b/gas/testsuite/gas/i386/nosse-1.s @@ -0,0 +1,8 @@ +# Test .arch .nosse + .text + .arch generic32 + lfence + .arch .sse2 + lfence + .arch .nosse + lfence diff --git a/gas/testsuite/gas/i386/nosse-2.l b/gas/testsuite/gas/i386/nosse-2.l new file mode 100644 index 0000000..45652b5 --- /dev/null +++ b/gas/testsuite/gas/i386/nosse-2.l @@ -0,0 +1,7 @@ +.*: Assembler messages: +.*:3: Error: .*nosse.* +GAS LISTING .* +#... +[ ]*1[ ]+\# Test -march=\.\.\.\+nosse +[ ]*2[ ]+\.text +[ ]*3[ ]+lfence diff --git a/gas/testsuite/gas/i386/nosse-2.s b/gas/testsuite/gas/i386/nosse-2.s new file mode 100644 index 0000000..bceb0c4 --- /dev/null +++ b/gas/testsuite/gas/i386/nosse-2.s @@ -0,0 +1,3 @@ +# Test -march=...+nosse + .text + lfence diff --git a/gas/testsuite/gas/i386/nosse-3.l b/gas/testsuite/gas/i386/nosse-3.l new file mode 100644 index 0000000..6626928 --- /dev/null +++ b/gas/testsuite/gas/i386/nosse-3.l @@ -0,0 +1,7 @@ +.*: Assembler messages: +.*:3: Error: .*nosse.* +GAS LISTING .* +#... +[ ]*1[ ]+\# Test -march=\+nosse +[ ]*2[ ]+\.text +[ ]*3[ ]+lfence diff --git a/gas/testsuite/gas/i386/nosse-3.s b/gas/testsuite/gas/i386/nosse-3.s new file mode 100644 index 0000000..b2ba5f7 --- /dev/null +++ b/gas/testsuite/gas/i386/nosse-3.s @@ -0,0 +1,3 @@ +# Test -march=+nosse + .text + lfence diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index 5b997f9..542ec6a 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -107,7 +107,7 @@ static initializer cpu_flag_init[] = "Cpu287" }, { "CPU_387_FLAGS", "Cpu387" }, - { "CPU_ANY87_FLAGS", + { "CPU_ANY_X87_FLAGS", "Cpu8087|Cpu287|Cpu387|Cpu687|CpuFISTTP" }, { "CPU_CLFLUSH_FLAGS", "CpuClflush" }, @@ -185,6 +185,8 @@ static initializer cpu_flag_init[] = "CpuMMX|Cpu3dnow" }, { "CPU_3DNOWA_FLAGS", "CpuMMX|Cpu3dnow|Cpu3dnowA" }, + { "CPU_ANY_MMX_FLAGS", + "CpuMMX|Cpu3dnow|Cpu3dnowA" }, { "CPU_PADLOCK_FLAGS", "CpuPadLock" }, { "CPU_SVME_FLAGS", diff --git a/opcodes/i386-init.h b/opcodes/i386-init.h index de68c22..f553d43 100644 --- a/opcodes/i386-init.h +++ b/opcodes/i386-init.h @@ -249,7 +249,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } -#define CPU_ANY87_FLAGS \ +#define CPU_ANY_X87_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -522,6 +522,13 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } +#define CPU_ANY_MMX_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + #define CPU_PADLOCK_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ -- 2.5.5 ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH] Allow setting CpuVRex bit in .arch directive 2016-05-25 16:35 ` H.J. Lu @ 2016-05-25 17:26 ` H.J. Lu 0 siblings, 0 replies; 18+ messages in thread From: H.J. Lu @ 2016-05-25 17:26 UTC (permalink / raw) To: Jakub Jelinek; +Cc: Binutils, Uros Bizjak, Kirill Yukhin [-- Attachment #1: Type: text/plain, Size: 1718 bytes --] On Wed, May 25, 2016 at 9:35 AM, H.J. Lu <hjl.tools@gmail.com> wrote: > On Tue, May 24, 2016 at 1:36 PM, H.J. Lu <hjl.tools@gmail.com> wrote: >> On Tue, May 24, 2016 at 12:07 PM, Jakub Jelinek <jakub@redhat.com> wrote: >>> On Tue, May 24, 2016 at 12:02:42PM -0700, H.J. Lu wrote: >>>> > Try: >>>> > .arch corei7 >>>> > .arch .avx512f >>>> > vpxord %xmm15, %xmm15, %xmm15 >>>> > vpxord %xmm16, %xmm16, %xmm16 >>>> > >>>> > I get: >>>> > /tmp/1.s: Assembler messages: >>>> > /tmp/1.s:4: Error: bad register name `%xmm16' >>>> >>>> I opened: >>>> >>>> https://sourceware.org/bugzilla/show_bug.cgi?id=20141 >>>> >>>> > and couldn't find any way how to make that assemble if I want to >>>> > disable even some ISA set and thus have to start with .arch <cpuname> >>>> > and add all the ISA sets I want to enable on top of that CPU. >>>> >>>> So you want to just disable AVX512D, no thing else. Wouldn't a >>>> ".noarch" directive work better? >>> >>> Well, to be able to generically disable specific ISAs (one, several). >>> An alternative to .noarch would be just allowing >>> .arch .noavx512vl etc. (like it already allows .no87). >>> Perhaps instead of mentioning all the ISAs once again with "no" prefix >>> just handle it generically, if .arch .no* is used, look first for >>> entries with explicit no at the beginning, and if not found, look for >>> the string after the prefix in the table and assume negate. >> >> Yes, it should work. > > It won't work since .noavx should disable all AVX instructions, > just just AVX. I am going to check in this patch to move all .noXXX > directives to cpu_noarch. We can add more .noXXX to cpu_noarch. > This is what I checked in. -- H.J. [-- Attachment #2: 0001-Reimplement-.no87-.nommx-.nosse-.noavx-directives.patch --] [-- Type: text/x-patch, Size: 31131 bytes --] From 0c1a2483f16bd8a26f1064e04f53d5fa4d2bef5f Mon Sep 17 00:00:00 2001 From: "H.J. Lu" <hjl.tools@gmail.com> Date: Tue, 24 May 2016 14:50:01 -0700 Subject: [PATCH] Reimplement .no87/.nommx/.nosse/.noavx directives Move all .noXXX directives to cpu_noarch. gas/ * config/tc-i386.c (arch_entry): Remove negated. (noarch_entry): New struct. (cpu_arch): Updated. Remove .no87, .nommx, .nosse and .noavx. (cpu_noarch): New. (set_cpu_arch): Check cpu_noarch after cpu_arch. (md_parse_option): Allow -march=+nosse. Check cpu_noarch after cpu_arch. (output_message): New function. (show_arch): Use it. Handle cpu_noarch. * testsuite/gas/i386/i386.exp: Run nommx-1, nommx-2, nommx-3, nosse-1, nosse-2, nosse-3, noavx-1 and noavx-2. * testsuite/gas/i386/noavx-1.l: New file. * testsuite/gas/i386/noavx-1.s: Likewise. * testsuite/gas/i386/noavx-2.s: Likewise. * testsuite/gas/i386/noavx-2.l: Likewise. * testsuite/gas/i386/nommx-1.s: Likewise. * testsuite/gas/i386/nommx-1.l: Likewise. * testsuite/gas/i386/nommx-2.s: Likewise. * testsuite/gas/i386/nommx-2.l: Likewise. * testsuite/gas/i386/nommx-3.s: Likewise. * testsuite/gas/i386/nommx-3.l: Likewise. * testsuite/gas/i386/nosse-1.s: Likewise. * testsuite/gas/i386/nosse-1.l: Likewise. * testsuite/gas/i386/nosse-2.s: Likewise. * testsuite/gas/i386/nosse-2.l: Likewise. * testsuite/gas/i386/nosse-3.s: Likewise. * testsuite/gas/i386/nosse-3.l: Likewise. opcodes/ * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS. * i386-init.h: Regenerated. --- gas/config/tc-i386.c | 416 ++++++++++++++++++++++++--------------- gas/testsuite/gas/i386/i386.exp | 8 + gas/testsuite/gas/i386/noavx-1.l | 13 ++ gas/testsuite/gas/i386/noavx-1.s | 8 + gas/testsuite/gas/i386/noavx-2.l | 7 + gas/testsuite/gas/i386/noavx-2.s | 3 + gas/testsuite/gas/i386/nommx-1.l | 21 ++ gas/testsuite/gas/i386/nommx-1.s | 14 ++ gas/testsuite/gas/i386/nommx-2.l | 7 + gas/testsuite/gas/i386/nommx-2.s | 3 + gas/testsuite/gas/i386/nommx-3.l | 7 + gas/testsuite/gas/i386/nommx-3.s | 3 + gas/testsuite/gas/i386/nosse-1.l | 13 ++ gas/testsuite/gas/i386/nosse-1.s | 8 + gas/testsuite/gas/i386/nosse-2.l | 7 + gas/testsuite/gas/i386/nosse-2.s | 3 + gas/testsuite/gas/i386/nosse-3.l | 7 + gas/testsuite/gas/i386/nosse-3.s | 3 + opcodes/i386-gen.c | 4 +- opcodes/i386-init.h | 9 +- 20 files changed, 399 insertions(+), 165 deletions(-) create mode 100644 gas/testsuite/gas/i386/noavx-1.l create mode 100644 gas/testsuite/gas/i386/noavx-1.s create mode 100644 gas/testsuite/gas/i386/noavx-2.l create mode 100644 gas/testsuite/gas/i386/noavx-2.s create mode 100644 gas/testsuite/gas/i386/nommx-1.l create mode 100644 gas/testsuite/gas/i386/nommx-1.s create mode 100644 gas/testsuite/gas/i386/nommx-2.l create mode 100644 gas/testsuite/gas/i386/nommx-2.s create mode 100644 gas/testsuite/gas/i386/nommx-3.l create mode 100644 gas/testsuite/gas/i386/nommx-3.s create mode 100644 gas/testsuite/gas/i386/nosse-1.l create mode 100644 gas/testsuite/gas/i386/nosse-1.s create mode 100644 gas/testsuite/gas/i386/nosse-2.l create mode 100644 gas/testsuite/gas/i386/nosse-2.s create mode 100644 gas/testsuite/gas/i386/nosse-3.l create mode 100644 gas/testsuite/gas/i386/nosse-3.s diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 8a4d987..13041ea 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -133,10 +133,18 @@ typedef struct enum processor_type type; /* arch type */ i386_cpu_flags flags; /* cpu feature flags */ unsigned int skip; /* show_arch should skip this. */ - unsigned int negated; /* turn off indicated flags. */ } arch_entry; +/* Used to turn off indicated flags. */ +typedef struct +{ + const char *name; /* arch name */ + unsigned int len; /* arch string length */ + i386_cpu_flags flags; /* cpu feature flags */ +} +noarch_entry; + static void update_code_flag (int, int); static void set_code_flag (int); static void set_16bit_gcc_code_flag (int); @@ -730,239 +738,239 @@ static const arch_entry cpu_arch[] = /* Do not replace the first two entries - i386_target_format() relies on them being there in this order. */ { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32, - CPU_GENERIC32_FLAGS, 0, 0 }, + CPU_GENERIC32_FLAGS, 0 }, { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64, - CPU_GENERIC64_FLAGS, 0, 0 }, + CPU_GENERIC64_FLAGS, 0 }, { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN, - CPU_NONE_FLAGS, 0, 0 }, + CPU_NONE_FLAGS, 0 }, { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN, - CPU_I186_FLAGS, 0, 0 }, + CPU_I186_FLAGS, 0 }, { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN, - CPU_I286_FLAGS, 0, 0 }, + CPU_I286_FLAGS, 0 }, { STRING_COMMA_LEN ("i386"), PROCESSOR_I386, - CPU_I386_FLAGS, 0, 0 }, + CPU_I386_FLAGS, 0 }, { STRING_COMMA_LEN ("i486"), PROCESSOR_I486, - CPU_I486_FLAGS, 0, 0 }, + CPU_I486_FLAGS, 0 }, { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM, - CPU_I586_FLAGS, 0, 0 }, + CPU_I586_FLAGS, 0 }, { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO, - CPU_I686_FLAGS, 0, 0 }, + CPU_I686_FLAGS, 0 }, { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM, - CPU_I586_FLAGS, 0, 0 }, + CPU_I586_FLAGS, 0 }, { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO, - CPU_PENTIUMPRO_FLAGS, 0, 0 }, + CPU_PENTIUMPRO_FLAGS, 0 }, { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO, - CPU_P2_FLAGS, 0, 0 }, + CPU_P2_FLAGS, 0 }, { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO, - CPU_P3_FLAGS, 0, 0 }, + CPU_P3_FLAGS, 0 }, { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4, - CPU_P4_FLAGS, 0, 0 }, + CPU_P4_FLAGS, 0 }, { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA, - CPU_CORE_FLAGS, 0, 0 }, + CPU_CORE_FLAGS, 0 }, { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA, - CPU_NOCONA_FLAGS, 0, 0 }, + CPU_NOCONA_FLAGS, 0 }, { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE, - CPU_CORE_FLAGS, 1, 0 }, + CPU_CORE_FLAGS, 1 }, { STRING_COMMA_LEN ("core"), PROCESSOR_CORE, - CPU_CORE_FLAGS, 0, 0 }, + CPU_CORE_FLAGS, 0 }, { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2, - CPU_CORE2_FLAGS, 1, 0 }, + CPU_CORE2_FLAGS, 1 }, { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2, - CPU_CORE2_FLAGS, 0, 0 }, + CPU_CORE2_FLAGS, 0 }, { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7, - CPU_COREI7_FLAGS, 0, 0 }, + CPU_COREI7_FLAGS, 0 }, { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM, - CPU_L1OM_FLAGS, 0, 0 }, + CPU_L1OM_FLAGS, 0 }, { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM, - CPU_K1OM_FLAGS, 0, 0 }, + CPU_K1OM_FLAGS, 0 }, { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU, - CPU_IAMCU_FLAGS, 0, 0 }, + CPU_IAMCU_FLAGS, 0 }, { STRING_COMMA_LEN ("k6"), PROCESSOR_K6, - CPU_K6_FLAGS, 0, 0 }, + CPU_K6_FLAGS, 0 }, { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6, - CPU_K6_2_FLAGS, 0, 0 }, + CPU_K6_2_FLAGS, 0 }, { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON, - CPU_ATHLON_FLAGS, 0, 0 }, + CPU_ATHLON_FLAGS, 0 }, { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8, - CPU_K8_FLAGS, 1, 0 }, + CPU_K8_FLAGS, 1 }, { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8, - CPU_K8_FLAGS, 0, 0 }, + CPU_K8_FLAGS, 0 }, { STRING_COMMA_LEN ("k8"), PROCESSOR_K8, - CPU_K8_FLAGS, 0, 0 }, + CPU_K8_FLAGS, 0 }, { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10, - CPU_AMDFAM10_FLAGS, 0, 0 }, + CPU_AMDFAM10_FLAGS, 0 }, { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD, - CPU_BDVER1_FLAGS, 0, 0 }, + CPU_BDVER1_FLAGS, 0 }, { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD, - CPU_BDVER2_FLAGS, 0, 0 }, + CPU_BDVER2_FLAGS, 0 }, { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD, - CPU_BDVER3_FLAGS, 0, 0 }, + CPU_BDVER3_FLAGS, 0 }, { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD, - CPU_BDVER4_FLAGS, 0, 0 }, + CPU_BDVER4_FLAGS, 0 }, { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER, - CPU_ZNVER1_FLAGS, 0, 0 }, + CPU_ZNVER1_FLAGS, 0 }, { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT, - CPU_BTVER1_FLAGS, 0, 0 }, + CPU_BTVER1_FLAGS, 0 }, { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT, - CPU_BTVER2_FLAGS, 0, 0 }, + CPU_BTVER2_FLAGS, 0 }, { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN, - CPU_8087_FLAGS, 0, 0 }, + CPU_8087_FLAGS, 0 }, { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN, - CPU_287_FLAGS, 0, 0 }, + CPU_287_FLAGS, 0 }, { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN, - CPU_387_FLAGS, 0, 0 }, - { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN, - CPU_ANY87_FLAGS, 0, 1 }, + CPU_387_FLAGS, 0 }, { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN, - CPU_MMX_FLAGS, 0, 0 }, - { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN, - CPU_3DNOWA_FLAGS, 0, 1 }, + CPU_MMX_FLAGS, 0 }, { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN, - CPU_SSE_FLAGS, 0, 0 }, + CPU_SSE_FLAGS, 0 }, { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN, - CPU_SSE2_FLAGS, 0, 0 }, + CPU_SSE2_FLAGS, 0 }, { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN, - CPU_SSE3_FLAGS, 0, 0 }, + CPU_SSE3_FLAGS, 0 }, { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN, - CPU_SSSE3_FLAGS, 0, 0 }, + CPU_SSSE3_FLAGS, 0 }, { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN, - CPU_SSE4_1_FLAGS, 0, 0 }, + CPU_SSE4_1_FLAGS, 0 }, { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN, - CPU_SSE4_2_FLAGS, 0, 0 }, + CPU_SSE4_2_FLAGS, 0 }, { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN, - CPU_SSE4_2_FLAGS, 0, 0 }, - { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN, - CPU_ANY_SSE_FLAGS, 0, 1 }, + CPU_SSE4_2_FLAGS, 0 }, { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN, - CPU_AVX_FLAGS, 0, 0 }, + CPU_AVX_FLAGS, 0 }, { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN, - CPU_AVX2_FLAGS, 0, 0 }, + CPU_AVX2_FLAGS, 0 }, { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN, - CPU_AVX512F_FLAGS, 0, 0 }, + CPU_AVX512F_FLAGS, 0 }, { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN, - CPU_AVX512CD_FLAGS, 0, 0 }, + CPU_AVX512CD_FLAGS, 0 }, { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN, - CPU_AVX512ER_FLAGS, 0, 0 }, + CPU_AVX512ER_FLAGS, 0 }, { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN, - CPU_AVX512PF_FLAGS, 0, 0 }, + CPU_AVX512PF_FLAGS, 0 }, { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN, - CPU_AVX512DQ_FLAGS, 0, 0 }, + CPU_AVX512DQ_FLAGS, 0 }, { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN, - CPU_AVX512BW_FLAGS, 0, 0 }, + CPU_AVX512BW_FLAGS, 0 }, { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN, - CPU_AVX512VL_FLAGS, 0, 0 }, - { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN, - CPU_ANY_AVX_FLAGS, 0, 1 }, + CPU_AVX512VL_FLAGS, 0 }, { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN, - CPU_VMX_FLAGS, 0, 0 }, + CPU_VMX_FLAGS, 0 }, { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN, - CPU_VMFUNC_FLAGS, 0, 0 }, + CPU_VMFUNC_FLAGS, 0 }, { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN, - CPU_SMX_FLAGS, 0, 0 }, + CPU_SMX_FLAGS, 0 }, { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN, - CPU_XSAVE_FLAGS, 0, 0 }, + CPU_XSAVE_FLAGS, 0 }, { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN, - CPU_XSAVEOPT_FLAGS, 0, 0 }, + CPU_XSAVEOPT_FLAGS, 0 }, { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN, - CPU_XSAVEC_FLAGS, 0, 0 }, + CPU_XSAVEC_FLAGS, 0 }, { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN, - CPU_XSAVES_FLAGS, 0, 0 }, + CPU_XSAVES_FLAGS, 0 }, { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN, - CPU_AES_FLAGS, 0, 0 }, + CPU_AES_FLAGS, 0 }, { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN, - CPU_PCLMUL_FLAGS, 0, 0 }, + CPU_PCLMUL_FLAGS, 0 }, { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN, - CPU_PCLMUL_FLAGS, 1, 0 }, + CPU_PCLMUL_FLAGS, 1 }, { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN, - CPU_FSGSBASE_FLAGS, 0, 0 }, + CPU_FSGSBASE_FLAGS, 0 }, { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN, - CPU_RDRND_FLAGS, 0, 0 }, + CPU_RDRND_FLAGS, 0 }, { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN, - CPU_F16C_FLAGS, 0, 0 }, + CPU_F16C_FLAGS, 0 }, { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN, - CPU_BMI2_FLAGS, 0, 0 }, + CPU_BMI2_FLAGS, 0 }, { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN, - CPU_FMA_FLAGS, 0, 0 }, + CPU_FMA_FLAGS, 0 }, { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN, - CPU_FMA4_FLAGS, 0, 0 }, + CPU_FMA4_FLAGS, 0 }, { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN, - CPU_XOP_FLAGS, 0, 0 }, + CPU_XOP_FLAGS, 0 }, { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN, - CPU_LWP_FLAGS, 0, 0 }, + CPU_LWP_FLAGS, 0 }, { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN, - CPU_MOVBE_FLAGS, 0, 0 }, + CPU_MOVBE_FLAGS, 0 }, { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN, - CPU_CX16_FLAGS, 0, 0 }, + CPU_CX16_FLAGS, 0 }, { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN, - CPU_EPT_FLAGS, 0, 0 }, + CPU_EPT_FLAGS, 0 }, { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN, - CPU_LZCNT_FLAGS, 0, 0 }, + CPU_LZCNT_FLAGS, 0 }, { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN, - CPU_HLE_FLAGS, 0, 0 }, + CPU_HLE_FLAGS, 0 }, { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN, - CPU_RTM_FLAGS, 0, 0 }, + CPU_RTM_FLAGS, 0 }, { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN, - CPU_INVPCID_FLAGS, 0, 0 }, + CPU_INVPCID_FLAGS, 0 }, { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN, - CPU_CLFLUSH_FLAGS, 0, 0 }, + CPU_CLFLUSH_FLAGS, 0 }, { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN, - CPU_NOP_FLAGS, 0, 0 }, + CPU_NOP_FLAGS, 0 }, { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN, - CPU_SYSCALL_FLAGS, 0, 0 }, + CPU_SYSCALL_FLAGS, 0 }, { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN, - CPU_RDTSCP_FLAGS, 0, 0 }, + CPU_RDTSCP_FLAGS, 0 }, { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN, - CPU_3DNOW_FLAGS, 0, 0 }, + CPU_3DNOW_FLAGS, 0 }, { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN, - CPU_3DNOWA_FLAGS, 0, 0 }, + CPU_3DNOWA_FLAGS, 0 }, { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN, - CPU_PADLOCK_FLAGS, 0, 0 }, + CPU_PADLOCK_FLAGS, 0 }, { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN, - CPU_SVME_FLAGS, 1, 0 }, + CPU_SVME_FLAGS, 1 }, { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN, - CPU_SVME_FLAGS, 0, 0 }, + CPU_SVME_FLAGS, 0 }, { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN, - CPU_SSE4A_FLAGS, 0, 0 }, + CPU_SSE4A_FLAGS, 0 }, { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN, - CPU_ABM_FLAGS, 0, 0 }, + CPU_ABM_FLAGS, 0 }, { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN, - CPU_BMI_FLAGS, 0, 0 }, + CPU_BMI_FLAGS, 0 }, { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN, - CPU_TBM_FLAGS, 0, 0 }, + CPU_TBM_FLAGS, 0 }, { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN, - CPU_ADX_FLAGS, 0, 0 }, + CPU_ADX_FLAGS, 0 }, { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN, - CPU_RDSEED_FLAGS, 0, 0 }, + CPU_RDSEED_FLAGS, 0 }, { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN, - CPU_PRFCHW_FLAGS, 0, 0 }, + CPU_PRFCHW_FLAGS, 0 }, { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN, - CPU_SMAP_FLAGS, 0, 0 }, + CPU_SMAP_FLAGS, 0 }, { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN, - CPU_MPX_FLAGS, 0, 0 }, + CPU_MPX_FLAGS, 0 }, { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN, - CPU_SHA_FLAGS, 0, 0 }, + CPU_SHA_FLAGS, 0 }, { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN, - CPU_CLFLUSHOPT_FLAGS, 0, 0 }, + CPU_CLFLUSHOPT_FLAGS, 0 }, { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN, - CPU_PREFETCHWT1_FLAGS, 0, 0 }, + CPU_PREFETCHWT1_FLAGS, 0 }, { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN, - CPU_SE1_FLAGS, 0, 0 }, + CPU_SE1_FLAGS, 0 }, { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN, - CPU_CLWB_FLAGS, 0, 0 }, + CPU_CLWB_FLAGS, 0 }, { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN, - CPU_PCOMMIT_FLAGS, 0, 0 }, + CPU_PCOMMIT_FLAGS, 0 }, { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN, - CPU_AVX512IFMA_FLAGS, 0, 0 }, + CPU_AVX512IFMA_FLAGS, 0 }, { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN, - CPU_AVX512VBMI_FLAGS, 0, 0 }, + CPU_AVX512VBMI_FLAGS, 0 }, { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN, - CPU_CLZERO_FLAGS, 0, 0 }, + CPU_CLZERO_FLAGS, 0 }, { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN, - CPU_MWAITX_FLAGS, 0, 0 }, + CPU_MWAITX_FLAGS, 0 }, { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN, - CPU_OSPKE_FLAGS, 0, 0 }, + CPU_OSPKE_FLAGS, 0 }, { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN, - CPU_RDPID_FLAGS, 0, 0 }, + CPU_RDPID_FLAGS, 0 }, +}; + +static const noarch_entry cpu_noarch[] = +{ + { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS }, + { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS }, + { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS }, + { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS }, }; #ifdef I386COFF @@ -2370,12 +2378,8 @@ set_cpu_arch (int dummy ATTRIBUTE_UNUSED) break; } - if (!cpu_arch[j].negated) - flags = cpu_flags_or (cpu_arch_flags, - cpu_arch[j].flags); - else - flags = cpu_flags_and_not (cpu_arch_flags, - cpu_arch[j].flags); + flags = cpu_flags_or (cpu_arch_flags, + cpu_arch[j].flags); if (!valid_iamcu_cpu_flags (&flags)) as_fatal (_("`%s' isn't valid for Intel MCU"), @@ -2400,6 +2404,37 @@ set_cpu_arch (int dummy ATTRIBUTE_UNUSED) return; } } + + if (*string == '.' && j >= ARRAY_SIZE (cpu_arch)) + { + /* Disable an ISA entension. */ + for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) + if (strcmp (string + 1, cpu_noarch [j].name) == 0) + { + flags = cpu_flags_and_not (cpu_arch_flags, + cpu_noarch[j].flags); + if (!cpu_flags_equal (&flags, &cpu_arch_flags)) + { + if (cpu_sub_arch_name) + { + char *name = cpu_sub_arch_name; + cpu_sub_arch_name = concat (name, string, + (const char *) NULL); + free (name); + } + else + cpu_sub_arch_name = xstrdup (string); + cpu_arch_flags = flags; + cpu_arch_isa_flags = flags; + } + (void) restore_line_pointer (e); + demand_empty_rest_of_line (); + return; + } + + j = ARRAY_SIZE (cpu_arch); + } + if (j >= ARRAY_SIZE (cpu_arch)) as_bad (_("no such architecture: `%s'"), string); @@ -9700,7 +9735,7 @@ int md_parse_option (int c, const char *arg) { unsigned int j; - char *arch, *next; + char *arch, *next, *saved; switch (c) { @@ -9804,7 +9839,11 @@ md_parse_option (int c, const char *arg) break; case OPTION_MARCH: - arch = xstrdup (arg); + saved = xstrdup (arg); + arch = saved; + /* Allow -march=+nosse. */ + if (*arch == '+') + arch++; do { if (*arch == '.') @@ -9838,12 +9877,8 @@ md_parse_option (int c, const char *arg) /* ISA entension. */ i386_cpu_flags flags; - if (!cpu_arch[j].negated) - flags = cpu_flags_or (cpu_arch_flags, - cpu_arch[j].flags); - else - flags = cpu_flags_and_not (cpu_arch_flags, - cpu_arch[j].flags); + flags = cpu_flags_or (cpu_arch_flags, + cpu_arch[j].flags); if (!valid_iamcu_cpu_flags (&flags)) as_fatal (_("`%s' isn't valid for Intel MCU"), arch); @@ -9867,11 +9902,43 @@ md_parse_option (int c, const char *arg) } if (j >= ARRAY_SIZE (cpu_arch)) + { + /* Disable an ISA entension. */ + for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) + if (strcmp (arch, cpu_noarch [j].name) == 0) + { + i386_cpu_flags flags; + + flags = cpu_flags_and_not (cpu_arch_flags, + cpu_noarch[j].flags); + if (!cpu_flags_equal (&flags, &cpu_arch_flags)) + { + if (cpu_sub_arch_name) + { + char *name = cpu_sub_arch_name; + cpu_sub_arch_name = concat (arch, + (const char *) NULL); + free (name); + } + else + cpu_sub_arch_name = xstrdup (arch); + cpu_arch_flags = flags; + cpu_arch_isa_flags = flags; + } + break; + } + + if (j >= ARRAY_SIZE (cpu_noarch)) + j = ARRAY_SIZE (cpu_arch); + } + + if (j >= ARRAY_SIZE (cpu_arch)) as_fatal (_("invalid -march= option: `%s'"), arg); arch = next; } - while (next != NULL ); + while (next != NULL); + free (saved); break; case OPTION_MTUNE: @@ -10049,6 +10116,44 @@ md_parse_option (int c, const char *arg) #define MESSAGE_TEMPLATE \ " " +static char * +output_message (FILE *stream, char *p, char *message, char *start, + int *left_p, const char *name, int len) +{ + int size = sizeof (MESSAGE_TEMPLATE); + int left = *left_p; + + /* Reserve 2 spaces for ", " or ",\0" */ + left -= len + 2; + + /* Check if there is any room. */ + if (left >= 0) + { + if (p != start) + { + *p++ = ','; + *p++ = ' '; + } + p = mempcpy (p, name, len); + } + else + { + /* Output the current message now and start a new one. */ + *p++ = ','; + *p = '\0'; + fprintf (stream, "%s\n", message); + p = start; + left = size - (start - message) - len - 2; + + gas_assert (left >= 0); + + p = mempcpy (p, name, len); + } + + *left_p = left; + return p; +} + static void show_arch (FILE *stream, int ext, int check) { @@ -10093,34 +10198,19 @@ show_arch (FILE *stream, int ext, int check) continue; } - /* Reserve 2 spaces for ", " or ",\0" */ - left -= len + 2; - - /* Check if there is any room. */ - if (left >= 0) - { - if (p != start) - { - *p++ = ','; - *p++ = ' '; - } - p = mempcpy (p, name, len); - } - else - { - /* Output the current message now and start a new one. */ - *p++ = ','; - *p = '\0'; - fprintf (stream, "%s\n", message); - p = start; - left = size - (start - message) - len - 2; - - gas_assert (left >= 0); - - p = mempcpy (p, name, len); - } + p = output_message (stream, p, message, start, &left, name, len); } + /* Display disabled extensions. */ + if (ext) + for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) + { + name = cpu_noarch [j].name; + len = cpu_noarch [j].len; + p = output_message (stream, p, message, start, &left, name, + len); + } + *p = '\0'; fprintf (stream, "%s\n", message); } diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index a18200e..716ec43 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -165,6 +165,14 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]] run_dump_test "387" run_list_test "no87" "-al" run_list_test "no87-2" "-march=i686+no87 -al" + run_list_test "nommx-1" "-al" + run_list_test "nommx-2" "-march=core+nommx -al" + run_list_test "nommx-3" "-march=+nommx -al" + run_list_test "nosse-1" "-al" + run_list_test "nosse-2" "-march=core+nosse -al" + run_list_test "nosse-3" "-march=+nosse -al" + run_list_test "noavx-1" "-al" + run_list_test "noavx-2" "-march=+noavx -al" run_dump_test "xsave" run_dump_test "xsave-intel" run_dump_test "aes" diff --git a/gas/testsuite/gas/i386/noavx-1.l b/gas/testsuite/gas/i386/noavx-1.l new file mode 100644 index 0000000..f4e2840 --- /dev/null +++ b/gas/testsuite/gas/i386/noavx-1.l @@ -0,0 +1,13 @@ +.*: Assembler messages: +.*:4: Error: .*generic.* +.*:8: Error: .*noavx.* +GAS LISTING .* +#... +[ ]*1[ ]+\# Test \.arch \.noavx +[ ]*2[ ]+\.text +[ ]*3[ ]+\.arch generic32 +[ ]*4[ ]+vzeroupper +[ ]*5[ ]+\.arch \.avx +[ ]*6[ ]+\?\?\?\? C5F877 vzeroupper +[ ]*7[ ]+\.arch \.noavx +[ ]*8[ ]+vzeroupper diff --git a/gas/testsuite/gas/i386/noavx-1.s b/gas/testsuite/gas/i386/noavx-1.s new file mode 100644 index 0000000..759b429 --- /dev/null +++ b/gas/testsuite/gas/i386/noavx-1.s @@ -0,0 +1,8 @@ +# Test .arch .noavx + .text + .arch generic32 + vzeroupper + .arch .avx + vzeroupper + .arch .noavx + vzeroupper diff --git a/gas/testsuite/gas/i386/noavx-2.l b/gas/testsuite/gas/i386/noavx-2.l new file mode 100644 index 0000000..32cc140 --- /dev/null +++ b/gas/testsuite/gas/i386/noavx-2.l @@ -0,0 +1,7 @@ +.*: Assembler messages: +.*:3: Error: .*noavx.* +GAS LISTING .* +#... +[ ]*1[ ]+\# Test -march=\+noavx +[ ]*2[ ]+\.text +[ ]*3[ ]+vzeroupper diff --git a/gas/testsuite/gas/i386/noavx-2.s b/gas/testsuite/gas/i386/noavx-2.s new file mode 100644 index 0000000..82ffa3e --- /dev/null +++ b/gas/testsuite/gas/i386/noavx-2.s @@ -0,0 +1,3 @@ +# Test -march=+noavx + .text + vzeroupper diff --git a/gas/testsuite/gas/i386/nommx-1.l b/gas/testsuite/gas/i386/nommx-1.l new file mode 100644 index 0000000..2b7a6ca --- /dev/null +++ b/gas/testsuite/gas/i386/nommx-1.l @@ -0,0 +1,21 @@ +.*: Assembler messages: +.*:4: Error: .*generic.* +.*:7: Error: .*mmx.* +.*:10: Error: .*3dnow.* +.*:14: Error: .*nommx.* +GAS LISTING .* +#... +[ ]*1[ ]+\# Test \.arch \.nommx +[ ]*2[ ]+\.text +[ ]*3[ ]+\.arch generic32 +[ ]*4[ ]+emms +[ ]*5[ ]+\.arch \.mmx +[ ]*6[ ]+\?\?\?\? 0F7EC0 movd %mm0, %eax +[ ]*7[ ]+femms +[ ]*8[ ]+\.arch \.3dnow +[ ]*9[ ]+\?\?\?\? 0F0E femms +[ ]*10[ ]+pswapd %mm1,%mm0 +[ ]*11[ ]+\.arch \.3dnowa +[ ]*12[ ]+\?\?\?\? 0F0FC1BB pswapd %mm1,%mm0 +[ ]*13[ ]+\.arch \.nommx +[ ]*14[ ]+emms diff --git a/gas/testsuite/gas/i386/nommx-1.s b/gas/testsuite/gas/i386/nommx-1.s new file mode 100644 index 0000000..f87edda --- /dev/null +++ b/gas/testsuite/gas/i386/nommx-1.s @@ -0,0 +1,14 @@ +# Test .arch .nommx + .text + .arch generic32 + emms + .arch .mmx + movd %mm0, %eax + femms + .arch .3dnow + femms + pswapd %mm1,%mm0 + .arch .3dnowa + pswapd %mm1,%mm0 + .arch .nommx + emms diff --git a/gas/testsuite/gas/i386/nommx-2.l b/gas/testsuite/gas/i386/nommx-2.l new file mode 100644 index 0000000..a94b0a8 --- /dev/null +++ b/gas/testsuite/gas/i386/nommx-2.l @@ -0,0 +1,7 @@ +.*: Assembler messages: +.*:3: Error: .*nommx.* +GAS LISTING .* +#... +[ ]*1[ ]+\# Test -march=\.\.\.\+nommx +[ ]*2[ ]+\.text +[ ]*3[ ]+emms diff --git a/gas/testsuite/gas/i386/nommx-2.s b/gas/testsuite/gas/i386/nommx-2.s new file mode 100644 index 0000000..266ab8d --- /dev/null +++ b/gas/testsuite/gas/i386/nommx-2.s @@ -0,0 +1,3 @@ +# Test -march=...+nommx + .text + emms diff --git a/gas/testsuite/gas/i386/nommx-3.l b/gas/testsuite/gas/i386/nommx-3.l new file mode 100644 index 0000000..0d2e1f1 --- /dev/null +++ b/gas/testsuite/gas/i386/nommx-3.l @@ -0,0 +1,7 @@ +.*: Assembler messages: +.*:3: Error: .*nommx.* +GAS LISTING .* +#... +[ ]*1[ ]+\# Test -march=\+nommx +[ ]*2[ ]+\.text +[ ]*3[ ]+emms diff --git a/gas/testsuite/gas/i386/nommx-3.s b/gas/testsuite/gas/i386/nommx-3.s new file mode 100644 index 0000000..4641c1d --- /dev/null +++ b/gas/testsuite/gas/i386/nommx-3.s @@ -0,0 +1,3 @@ +# Test -march=+nommx + .text + emms diff --git a/gas/testsuite/gas/i386/nosse-1.l b/gas/testsuite/gas/i386/nosse-1.l new file mode 100644 index 0000000..486241b --- /dev/null +++ b/gas/testsuite/gas/i386/nosse-1.l @@ -0,0 +1,13 @@ +.*: Assembler messages: +.*:4: Error: .*generic.* +.*:8: Error: .*nosse.* +GAS LISTING .* +#... +[ ]*1[ ]+\# Test \.arch \.nosse +[ ]*2[ ]+\.text +[ ]*3[ ]+\.arch generic32 +[ ]*4[ ]+lfence +[ ]*5[ ]+\.arch \.sse2 +[ ]*6[ ]+\?\?\?\? 0FAEE8 lfence +[ ]*7[ ]+\.arch \.nosse +[ ]*8[ ]+lfence diff --git a/gas/testsuite/gas/i386/nosse-1.s b/gas/testsuite/gas/i386/nosse-1.s new file mode 100644 index 0000000..27f2528 --- /dev/null +++ b/gas/testsuite/gas/i386/nosse-1.s @@ -0,0 +1,8 @@ +# Test .arch .nosse + .text + .arch generic32 + lfence + .arch .sse2 + lfence + .arch .nosse + lfence diff --git a/gas/testsuite/gas/i386/nosse-2.l b/gas/testsuite/gas/i386/nosse-2.l new file mode 100644 index 0000000..45652b5 --- /dev/null +++ b/gas/testsuite/gas/i386/nosse-2.l @@ -0,0 +1,7 @@ +.*: Assembler messages: +.*:3: Error: .*nosse.* +GAS LISTING .* +#... +[ ]*1[ ]+\# Test -march=\.\.\.\+nosse +[ ]*2[ ]+\.text +[ ]*3[ ]+lfence diff --git a/gas/testsuite/gas/i386/nosse-2.s b/gas/testsuite/gas/i386/nosse-2.s new file mode 100644 index 0000000..bceb0c4 --- /dev/null +++ b/gas/testsuite/gas/i386/nosse-2.s @@ -0,0 +1,3 @@ +# Test -march=...+nosse + .text + lfence diff --git a/gas/testsuite/gas/i386/nosse-3.l b/gas/testsuite/gas/i386/nosse-3.l new file mode 100644 index 0000000..6626928 --- /dev/null +++ b/gas/testsuite/gas/i386/nosse-3.l @@ -0,0 +1,7 @@ +.*: Assembler messages: +.*:3: Error: .*nosse.* +GAS LISTING .* +#... +[ ]*1[ ]+\# Test -march=\+nosse +[ ]*2[ ]+\.text +[ ]*3[ ]+lfence diff --git a/gas/testsuite/gas/i386/nosse-3.s b/gas/testsuite/gas/i386/nosse-3.s new file mode 100644 index 0000000..b2ba5f7 --- /dev/null +++ b/gas/testsuite/gas/i386/nosse-3.s @@ -0,0 +1,3 @@ +# Test -march=+nosse + .text + lfence diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index 5b997f9..542ec6a 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -107,7 +107,7 @@ static initializer cpu_flag_init[] = "Cpu287" }, { "CPU_387_FLAGS", "Cpu387" }, - { "CPU_ANY87_FLAGS", + { "CPU_ANY_X87_FLAGS", "Cpu8087|Cpu287|Cpu387|Cpu687|CpuFISTTP" }, { "CPU_CLFLUSH_FLAGS", "CpuClflush" }, @@ -185,6 +185,8 @@ static initializer cpu_flag_init[] = "CpuMMX|Cpu3dnow" }, { "CPU_3DNOWA_FLAGS", "CpuMMX|Cpu3dnow|Cpu3dnowA" }, + { "CPU_ANY_MMX_FLAGS", + "CpuMMX|Cpu3dnow|Cpu3dnowA" }, { "CPU_PADLOCK_FLAGS", "CpuPadLock" }, { "CPU_SVME_FLAGS", diff --git a/opcodes/i386-init.h b/opcodes/i386-init.h index de68c22..f553d43 100644 --- a/opcodes/i386-init.h +++ b/opcodes/i386-init.h @@ -249,7 +249,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } -#define CPU_ANY87_FLAGS \ +#define CPU_ANY_X87_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -522,6 +522,13 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } +#define CPU_ANY_MMX_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + #define CPU_PADLOCK_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ -- 2.5.5 ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH] Allow setting CpuVRex bit in .arch directive 2016-05-24 20:36 ` H.J. Lu 2016-05-25 16:35 ` H.J. Lu @ 2016-05-25 17:54 ` H.J. Lu 2016-05-25 17:58 ` Jakub Jelinek 1 sibling, 1 reply; 18+ messages in thread From: H.J. Lu @ 2016-05-25 17:54 UTC (permalink / raw) To: Jakub Jelinek; +Cc: Binutils, Uros Bizjak, Kirill Yukhin [-- Attachment #1: Type: text/plain, Size: 313 bytes --] On Tue, May 24, 2016 at 1:36 PM, H.J. Lu <hjl.tools@gmail.com> wrote: > >> Anyway, still it would be good to be able to change (both set and remove) >> the CpuVRex bit. >> > > CpuVRex should be cleared/set automatically based on ISA. > I am checking in this patch to enable VREX for AVX512 directives. -- H.J. [-- Attachment #2: 0001-Enable-VREX-for-AVX512-directives.patch --] [-- Type: text/x-patch, Size: 6691 bytes --] From f1360d5830fc7695cd26214257c62f34b73070c8 Mon Sep 17 00:00:00 2001 From: "H.J. Lu" <hjl.tools@gmail.com> Date: Wed, 25 May 2016 10:49:25 -0700 Subject: [PATCH] Enable VREX for AVX512 directives Enable VREX for AVX512 instructions with upper 16 vector registers. gas/ PR gas/20141 * testsuite/gas/i386/i386.exp: Run x86-64-pr20141. * testsuite/gas/i386/x86-64-pr20141.d: New file. * testsuite/gas/i386/x86-64-pr20141.s: Likewise. opcodes/ PR gas/20141 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. * i386-init.h: Regenerated. --- gas/ChangeLog | 7 +++++++ gas/testsuite/gas/i386/i386.exp | 1 + gas/testsuite/gas/i386/x86-64-pr20141.d | 10 ++++++++++ gas/testsuite/gas/i386/x86-64-pr20141.s | 5 +++++ opcodes/ChangeLog | 7 +++++++ opcodes/i386-gen.c | 8 ++++---- opcodes/i386-init.h | 8 ++++---- 7 files changed, 38 insertions(+), 8 deletions(-) create mode 100644 gas/testsuite/gas/i386/x86-64-pr20141.d create mode 100644 gas/testsuite/gas/i386/x86-64-pr20141.s diff --git a/gas/ChangeLog b/gas/ChangeLog index 54afd16..2d23b43 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,5 +1,12 @@ 2016-05-25 H.J. Lu <hongjiu.lu@intel.com> + PR gas/20141 + * testsuite/gas/i386/i386.exp: Run x86-64-pr20141. + * testsuite/gas/i386/x86-64-pr20141.d: New file. + * testsuite/gas/i386/x86-64-pr20141.s: Likewise. + +2016-05-25 H.J. Lu <hongjiu.lu@intel.com> + * config/tc-i386.c (arch_entry): Remove negated. (noarch_entry): New struct. (cpu_arch): Updated. Remove .no87, .nommx, .nosse and .noavx. diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index 716ec43..1aca467 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -753,6 +753,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t run_dump_test "x86-64-rdpid-intel" run_dump_test "x86-64-fence-as-lock-add-yes" run_dump_test "x86-64-fence-as-lock-add-no" + run_dump_test "x86-64-pr20141" if { ![istarget "*-*-aix*"] && ![istarget "*-*-beos*"] diff --git a/gas/testsuite/gas/i386/x86-64-pr20141.d b/gas/testsuite/gas/i386/x86-64-pr20141.d new file mode 100644 index 0000000..a8012b2 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-pr20141.d @@ -0,0 +1,10 @@ +#objdump: -dw + +.*: +file format .* + + +Disassembly of section .text: + +0+ <_start>: +[ ]*[a-f0-9]+: 62 e1 7d 48 e7 21 vmovntdq %zmm20,\(%rcx\) +#pass diff --git a/gas/testsuite/gas/i386/x86-64-pr20141.s b/gas/testsuite/gas/i386/x86-64-pr20141.s new file mode 100644 index 0000000..f8fa3df --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-pr20141.s @@ -0,0 +1,5 @@ + .text + .arch corei7 + .arch .avx512f +_start: + vmovntdq %zmm20, (%rcx) diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index f13f299..819c8ee 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,12 @@ 2016-05-25 H.J. Lu <hongjiu.lu@intel.com> + PR gas/20141 + * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS, + CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. + * i386-init.h: Regenerated. + +2016-05-25 H.J. Lu <hongjiu.lu@intel.com> + * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS. * i386-init.h: Regenerated. diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index 542ec6a..7a090e2 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -200,13 +200,13 @@ static initializer cpu_flag_init[] = { "CPU_AVX2_FLAGS", "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2" }, { "CPU_AVX512F_FLAGS", - "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F" }, + "CpuVREX|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F" }, { "CPU_AVX512CD_FLAGS", - "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512CD" }, + "CpuVREX|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512CD" }, { "CPU_AVX512ER_FLAGS", - "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512ER" }, + "CpuVREX|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512ER" }, { "CPU_AVX512PF_FLAGS", - "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512PF" }, + "CpuVREX|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512PF" }, { "CPU_ANY_AVX_FLAGS", "CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF" }, { "CPU_L1OM_FLAGS", diff --git a/opcodes/i386-init.h b/opcodes/i386-init.h index f553d43..b023f98 100644 --- a/opcodes/i386-init.h +++ b/opcodes/i386-init.h @@ -575,28 +575,28 @@ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \ 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } #define CPU_AVX512CD_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \ 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } #define CPU_AVX512ER_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \ 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } #define CPU_AVX512PF_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \ 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } #define CPU_ANY_AVX_FLAGS \ -- 2.5.5 ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH] Allow setting CpuVRex bit in .arch directive 2016-05-25 17:54 ` H.J. Lu @ 2016-05-25 17:58 ` Jakub Jelinek 2016-05-25 18:26 ` H.J. Lu 0 siblings, 1 reply; 18+ messages in thread From: Jakub Jelinek @ 2016-05-25 17:58 UTC (permalink / raw) To: H.J. Lu; +Cc: Binutils, Uros Bizjak, Kirill Yukhin On Wed, May 25, 2016 at 10:53:51AM -0700, H.J. Lu wrote: > I am checking in this patch to enable VREX for AVX512 directives. > --- a/opcodes/i386-gen.c > +++ b/opcodes/i386-gen.c > @@ -200,13 +200,13 @@ static initializer cpu_flag_init[] = > { "CPU_AVX2_FLAGS", > "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2" }, > { "CPU_AVX512F_FLAGS", > - "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F" }, > + "CpuVREX|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F" }, > { "CPU_AVX512CD_FLAGS", > - "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512CD" }, > + "CpuVREX|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512CD" }, > { "CPU_AVX512ER_FLAGS", > - "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512ER" }, > + "CpuVREX|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512ER" }, > { "CPU_AVX512PF_FLAGS", > - "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512PF" }, > + "CpuVREX|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512PF" }, > { "CPU_ANY_AVX_FLAGS", > "CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF" }, > { "CPU_L1OM_FLAGS", What about CPU_AVX512{DQ,BW,VL,IFMA,VBMI}_FLAGS ? Jakub ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH] Allow setting CpuVRex bit in .arch directive 2016-05-25 17:58 ` Jakub Jelinek @ 2016-05-25 18:26 ` H.J. Lu 2016-05-25 18:39 ` Jakub Jelinek 0 siblings, 1 reply; 18+ messages in thread From: H.J. Lu @ 2016-05-25 18:26 UTC (permalink / raw) To: Jakub Jelinek; +Cc: Binutils, Uros Bizjak, Kirill Yukhin [-- Attachment #1: Type: text/plain, Size: 1685 bytes --] On Wed, May 25, 2016 at 10:58 AM, Jakub Jelinek <jakub@redhat.com> wrote: > On Wed, May 25, 2016 at 10:53:51AM -0700, H.J. Lu wrote: >> I am checking in this patch to enable VREX for AVX512 directives. >> --- a/opcodes/i386-gen.c >> +++ b/opcodes/i386-gen.c >> @@ -200,13 +200,13 @@ static initializer cpu_flag_init[] = >> { "CPU_AVX2_FLAGS", >> "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2" }, >> { "CPU_AVX512F_FLAGS", >> - "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F" }, >> + "CpuVREX|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F" }, >> { "CPU_AVX512CD_FLAGS", >> - "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512CD" }, >> + "CpuVREX|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512CD" }, >> { "CPU_AVX512ER_FLAGS", >> - "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512ER" }, >> + "CpuVREX|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512ER" }, >> { "CPU_AVX512PF_FLAGS", >> - "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512PF" }, >> + "CpuVREX|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512PF" }, >> { "CPU_ANY_AVX_FLAGS", >> "CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF" }, >> { "CPU_L1OM_FLAGS", > > What about CPU_AVX512{DQ,BW,VL,IFMA,VBMI}_FLAGS ? > > Jakub I checked in this fix. Thanks. -- H.J. [-- Attachment #2: 0001-Enable-VREX-for-all-AVX512-directives.patch --] [-- Type: text/x-patch, Size: 8886 bytes --] From f3ad76370f8c79e4ae74ca6826e23bf417d5283a Mon Sep 17 00:00:00 2001 From: "H.J. Lu" <hjl.tools@gmail.com> Date: Wed, 25 May 2016 11:23:40 -0700 Subject: [PATCH] Enable VREX for all AVX512 directives Add all AVX512 bits to CPU_ANY_AVX_FLAGS. * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS, CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW, CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to CPU_ANY_AVX_FLAGS. * i386-init.h: Regenerated. --- opcodes/ChangeLog | 9 +++++++ opcodes/i386-gen.c | 22 ++++++++-------- opcodes/i386-init.h | 76 ++++++++++++++++++++++++++--------------------------- 3 files changed, 58 insertions(+), 49 deletions(-) diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 819c8ee..accee8e 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,14 @@ 2016-05-25 H.J. Lu <hongjiu.lu@intel.com> + * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS, + CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS + and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW, + CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to + CPU_ANY_AVX_FLAGS. + * i386-init.h: Regenerated. + +2016-05-25 H.J. Lu <hongjiu.lu@intel.com> + PR gas/20141 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index 7a090e2..b19bbe1 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -207,8 +207,18 @@ static initializer cpu_flag_init[] = "CpuVREX|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512ER" }, { "CPU_AVX512PF_FLAGS", "CpuVREX|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512PF" }, + { "CPU_AVX512DQ_FLAGS", + "CpuVREX|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512DQ" }, + { "CPU_AVX512BW_FLAGS", + "CpuVREX|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512BW" }, + { "CPU_AVX512VL_FLAGS", + "CpuVREX|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512VL" }, + { "CPU_AVX512IFMA_FLAGS", + "CpuVREX|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512IFMA" }, + { "CPU_AVX512VBMI_FLAGS", + "CpuVREX|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512VBMI" }, { "CPU_ANY_AVX_FLAGS", - "CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF" }, + "CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF|CpuAVX512DQ|CpuAVX512BW|CpuAVX512VL|CpuAVX512IFMA|CpuAVX512VBMI" }, { "CPU_L1OM_FLAGS", "unknown" }, { "CPU_K1OM_FLAGS", @@ -239,20 +249,10 @@ static initializer cpu_flag_init[] = "CpuPREFETCHWT1" }, { "CPU_SE1_FLAGS", "CpuSE1" }, - { "CPU_AVX512DQ_FLAGS", - "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512DQ" }, - { "CPU_AVX512BW_FLAGS", - "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512BW" }, - { "CPU_AVX512VL_FLAGS", - "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512VL" }, { "CPU_CLWB_FLAGS", "CpuCLWB" }, { "CPU_PCOMMIT_FLAGS", "CpuPCOMMIT" }, - { "CPU_AVX512IFMA_FLAGS", - "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512IFMA" }, - { "CPU_AVX512VBMI_FLAGS", - "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512VBMI" }, { "CPU_CLZERO_FLAGS", "CpuCLZERO" }, { "CPU_MWAITX_FLAGS", diff --git a/opcodes/i386-init.h b/opcodes/i386-init.h index b023f98..ee9f7b5 100644 --- a/opcodes/i386-init.h +++ b/opcodes/i386-init.h @@ -599,13 +599,48 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } -#define CPU_ANY_AVX_FLAGS \ - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, \ +#define CPU_AVX512DQ_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \ + 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_AVX512BW_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \ + 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_AVX512VL_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \ + 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } +#define CPU_AVX512IFMA_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \ + 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_AVX512VBMI_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \ + 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ + 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_ANY_AVX_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + #define CPU_L1OM_FLAGS \ { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ @@ -711,27 +746,6 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } -#define CPU_AVX512DQ_FLAGS \ - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \ - 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } - -#define CPU_AVX512BW_FLAGS \ - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \ - 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } - -#define CPU_AVX512VL_FLAGS \ - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \ - 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } - #define CPU_CLWB_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -746,20 +760,6 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } -#define CPU_AVX512IFMA_FLAGS \ - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \ - 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } - -#define CPU_AVX512VBMI_FLAGS \ - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \ - 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } - #define CPU_CLZERO_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ -- 2.5.5 ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH] Allow setting CpuVRex bit in .arch directive 2016-05-25 18:26 ` H.J. Lu @ 2016-05-25 18:39 ` Jakub Jelinek 2016-05-25 19:12 ` H.J. Lu 0 siblings, 1 reply; 18+ messages in thread From: Jakub Jelinek @ 2016-05-25 18:39 UTC (permalink / raw) To: H.J. Lu; +Cc: Binutils, Uros Bizjak, Kirill Yukhin On Wed, May 25, 2016 at 11:25:48AM -0700, H.J. Lu wrote: > { "CPU_ANY_AVX_FLAGS", > - "CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF" }, > + "CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF|CpuAVX512DQ|CpuAVX512BW|CpuAVX512VL|CpuAVX512IFMA|CpuAVX512VBMI" }, Shouldn't this also include other flags that imply AVX? Like CpuFMA|CpuFMA4|CpuXOP ? Shouldn't CPU_ANY_SSE_FLAGS include also all the new CPU_ANY_AVX_FLAGS? What about CPU_F16C_FLAGS and CpuF16C? E.g. in GCC -mf16c implies -mavx and -mno-avx implies -mno-f16c. So shouldn't CPU_F16C_FLAGS also include CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX and CPU_ANY_AVX_FLAGS include CpuF16C and similarly CPU_ANY_SSE_FLAGS? Jakub ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH] Allow setting CpuVRex bit in .arch directive 2016-05-25 18:39 ` Jakub Jelinek @ 2016-05-25 19:12 ` H.J. Lu 2016-05-26 0:09 ` H.J. Lu 0 siblings, 1 reply; 18+ messages in thread From: H.J. Lu @ 2016-05-25 19:12 UTC (permalink / raw) To: Jakub Jelinek; +Cc: Binutils, Uros Bizjak, Kirill Yukhin On Wed, May 25, 2016 at 11:38 AM, Jakub Jelinek <jakub@redhat.com> wrote: > On Wed, May 25, 2016 at 11:25:48AM -0700, H.J. Lu wrote: >> { "CPU_ANY_AVX_FLAGS", >> - "CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF" }, >> + "CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF|CpuAVX512DQ|CpuAVX512BW|CpuAVX512VL|CpuAVX512IFMA|CpuAVX512VBMI" }, > > Shouldn't this also include other flags that imply AVX? > Like CpuFMA|CpuFMA4|CpuXOP ? > > Shouldn't CPU_ANY_SSE_FLAGS include also all the new CPU_ANY_AVX_FLAGS? > > What about CPU_F16C_FLAGS and CpuF16C? E.g. in GCC -mf16c implies > -mavx and -mno-avx implies -mno-f16c. So shouldn't CPU_F16C_FLAGS also > include CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX > and CPU_ANY_AVX_FLAGS include CpuF16C and similarly CPU_ANY_SSE_FLAGS? > Let me think about it. -- H.J. ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH] Allow setting CpuVRex bit in .arch directive 2016-05-25 19:12 ` H.J. Lu @ 2016-05-26 0:09 ` H.J. Lu 2016-05-29 15:04 ` H.J. Lu 0 siblings, 1 reply; 18+ messages in thread From: H.J. Lu @ 2016-05-26 0:09 UTC (permalink / raw) To: Jakub Jelinek; +Cc: Binutils, Uros Bizjak, Kirill Yukhin On Wed, May 25, 2016 at 12:12 PM, H.J. Lu <hjl.tools@gmail.com> wrote: > On Wed, May 25, 2016 at 11:38 AM, Jakub Jelinek <jakub@redhat.com> wrote: >> On Wed, May 25, 2016 at 11:25:48AM -0700, H.J. Lu wrote: >>> { "CPU_ANY_AVX_FLAGS", >>> - "CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF" }, >>> + "CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF|CpuAVX512DQ|CpuAVX512BW|CpuAVX512VL|CpuAVX512IFMA|CpuAVX512VBMI" }, >> >> Shouldn't this also include other flags that imply AVX? >> Like CpuFMA|CpuFMA4|CpuXOP ? >> >> Shouldn't CPU_ANY_SSE_FLAGS include also all the new CPU_ANY_AVX_FLAGS? >> >> What about CPU_F16C_FLAGS and CpuF16C? E.g. in GCC -mf16c implies >> -mavx and -mno-avx implies -mno-f16c. So shouldn't CPU_F16C_FLAGS also >> include CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX >> and CPU_ANY_AVX_FLAGS include CpuF16C and similarly CPU_ANY_SSE_FLAGS? >> > > Let me think about it. I opened: https://sourceware.org/bugzilla/show_bug.cgi?id=20145 -- H.J. ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH] Allow setting CpuVRex bit in .arch directive 2016-05-26 0:09 ` H.J. Lu @ 2016-05-29 15:04 ` H.J. Lu 0 siblings, 0 replies; 18+ messages in thread From: H.J. Lu @ 2016-05-29 15:04 UTC (permalink / raw) To: Jakub Jelinek; +Cc: Binutils, Uros Bizjak, Kirill Yukhin [-- Attachment #1: Type: text/plain, Size: 1231 bytes --] On Wed, May 25, 2016 at 3:20 PM, H.J. Lu <hjl.tools@gmail.com> wrote: > On Wed, May 25, 2016 at 12:12 PM, H.J. Lu <hjl.tools@gmail.com> wrote: >> On Wed, May 25, 2016 at 11:38 AM, Jakub Jelinek <jakub@redhat.com> wrote: >>> On Wed, May 25, 2016 at 11:25:48AM -0700, H.J. Lu wrote: >>>> { "CPU_ANY_AVX_FLAGS", >>>> - "CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF" }, >>>> + "CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF|CpuAVX512DQ|CpuAVX512BW|CpuAVX512VL|CpuAVX512IFMA|CpuAVX512VBMI" }, >>> >>> Shouldn't this also include other flags that imply AVX? >>> Like CpuFMA|CpuFMA4|CpuXOP ? >>> >>> Shouldn't CPU_ANY_SSE_FLAGS include also all the new CPU_ANY_AVX_FLAGS? >>> >>> What about CPU_F16C_FLAGS and CpuF16C? E.g. in GCC -mf16c implies >>> -mavx and -mno-avx implies -mno-f16c. So shouldn't CPU_F16C_FLAGS also >>> include CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX >>> and CPU_ANY_AVX_FLAGS include CpuF16C and similarly CPU_ANY_SSE_FLAGS? >>> >> >> Let me think about it. > > I opened: > > https://sourceware.org/bugzilla/show_bug.cgi?id=20145 > I checked in this. I will close PR 20145. Please open a new PR if we need more .noXXX directives. -- H.J. [-- Attachment #2: 0001-Add-.noavx512XX-directives-to-x86-assembler.patch --] [-- Type: text/x-patch, Size: 45903 bytes --] From 144b71e2a88e02d0b54d4f09cc652f353b46e455 Mon Sep 17 00:00:00 2001 From: "H.J. Lu" <hjl.tools@gmail.com> Date: Fri, 27 May 2016 15:41:45 -0700 Subject: [PATCH] Add .noavx512XX directives to x86 assembler Add .noavx512f, .noavx512cd, .noavx512er, .noavx512pf, .noavx512dq, .noavx512bw, .noavx512vl, .noavx512ifma, .noavx512vbmi directives to x86 assembler. gas/ PR gas/20145 * config/tc-i386.c (cpu_noarch): Add noavx512f, noavx512cd, noavx512er, noavx512pf, noavx512dq, noavx512bw, noavx512vl, noavx512ifma and noavx512vbmi. * doc/c-i386.texi: Mention noavx512f, noavx512cd, noavx512er, noavx512pf, noavx512dq, noavx512bw, noavx512vl, noavx512ifma and noavx512vbmi. * testsuite/gas/i386/i386.exp: Run noavx512-1 and noavx512-2. * testsuite/gas/i386/noavx512-1.l: New file. * testsuite/gas/i386/noavx512-1.s: Likewise. * testsuite/gas/i386/noavx512-2.l: Likewise. * testsuite/gas/i386/noavx512-2.s: Likewise. opcodes/ PR gas/20145 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS, CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS, CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS, CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS, CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS. * i386-init.h: Regenerated. --- gas/config/tc-i386.c | 9 + gas/doc/c-i386.texi | 9 + gas/testsuite/gas/i386/i386.exp | 2 + gas/testsuite/gas/i386/noavx512-1.l | 416 ++++++++++++++++++++++++++++++++++++ gas/testsuite/gas/i386/noavx512-1.s | 207 ++++++++++++++++++ gas/testsuite/gas/i386/noavx512-2.l | 105 +++++++++ gas/testsuite/gas/i386/noavx512-2.s | 53 +++++ opcodes/i386-gen.c | 18 ++ opcodes/i386-init.h | 63 ++++++ 9 files changed, 882 insertions(+) create mode 100644 gas/testsuite/gas/i386/noavx512-1.l create mode 100644 gas/testsuite/gas/i386/noavx512-1.s create mode 100644 gas/testsuite/gas/i386/noavx512-2.l create mode 100644 gas/testsuite/gas/i386/noavx512-2.s diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index b69130a..457f557 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -987,6 +987,15 @@ static const noarch_entry cpu_noarch[] = { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS }, { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS }, { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS }, + { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS }, + { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS }, + { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS }, + { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS }, + { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS }, + { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS }, + { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS }, + { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS }, + { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS }, }; #ifdef I386COFF diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index 696cadf..30e29f6 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -180,6 +180,15 @@ accept various extension mnemonics. For example, @code{avx512dq}, @code{avx512ifma}, @code{avx512vbmi}, +@code{noavx512f}, +@code{noavx512cd}, +@code{noavx512er}, +@code{noavx512pf}, +@code{noavx512vl}, +@code{noavx512bw}, +@code{noavx512dq}, +@code{noavx512ifma}, +@code{noavx512vbmi}, @code{vmx}, @code{vmfunc}, @code{smx}, diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index 0c22498..959cd14 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -178,6 +178,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]] run_list_test "noavx-2" "-march=+noavx -al" run_list_test "noavx-3" "-al" run_dump_test "noavx-4" + run_list_test "noavx512-1" "-al" + run_list_test "noavx512-2" "-al" run_dump_test "xsave" run_dump_test "xsave-intel" run_dump_test "aes" diff --git a/gas/testsuite/gas/i386/noavx512-1.l b/gas/testsuite/gas/i386/noavx512-1.l new file mode 100644 index 0000000..ece9211 --- /dev/null +++ b/gas/testsuite/gas/i386/noavx512-1.l @@ -0,0 +1,416 @@ +.*: Assembler messages: +.*:25: Error: .*unsupported instruction.* +.*:26: Error: .*unsupported masking.* +.*:27: Error: .*unsupported masking.* +.*:47: Error: .*unsupported instruction.* +.*:48: Error: .*unsupported masking.* +.*:49: Error: .*unsupported masking.* +.*:50: Error: .*not supported.* +.*:51: Error: .*not supported.* +.*:52: Error: .*not supported.* +.*:69: Error: .*unsupported instruction.* +.*:70: Error: .*unsupported masking.* +.*:71: Error: .*unsupported masking.* +.*:72: Error: .*not supported.* +.*:73: Error: .*not supported.* +.*:74: Error: .*not supported.* +.*:75: Error: .*not supported.* +.*:76: Error: .*not supported.* +.*:77: Error: .*not supported.* +.*:91: Error: .*unsupported instruction.* +.*:92: Error: .*unsupported masking.* +.*:93: Error: .*unsupported masking.* +.*:94: Error: .*not supported.* +.*:95: Error: .*not supported.* +.*:96: Error: .*not supported.* +.*:97: Error: .*not supported.* +.*:98: Error: .*not supported.* +.*:99: Error: .*not supported.* +.*:100: Error: .*not supported.* +.*:113: Error: .*unsupported instruction.* +.*:114: Error: .*unsupported masking.* +.*:115: Error: .*unsupported masking.* +.*:116: Error: .*not supported.* +.*:117: Error: .*not supported.* +.*:118: Error: .*not supported.* +.*:119: Error: .*not supported.* +.*:120: Error: .*not supported.* +.*:121: Error: .*not supported.* +.*:122: Error: .*not supported.* +.*:126: Error: .*not supported.* +.*:127: Error: .*not supported.* +.*:128: Error: .*not supported.* +.*:135: Error: .*unsupported instruction.* +.*:136: Error: .*unsupported masking.* +.*:137: Error: .*unsupported masking.* +.*:138: Error: .*not supported.* +.*:139: Error: .*not supported.* +.*:140: Error: .*not supported.* +.*:141: Error: .*not supported.* +.*:142: Error: .*not supported.* +.*:143: Error: .*not supported.* +.*:144: Error: .*not supported.* +.*:148: Error: .*not supported.* +.*:149: Error: .*not supported.* +.*:150: Error: .*not supported.* +.*:151: Error: .*not supported.* +.*:157: Error: .*unsupported instruction.* +.*:158: Error: .*unsupported masking.* +.*:159: Error: .*unsupported masking.* +.*:160: Error: .*not supported.* +.*:161: Error: .*not supported.* +.*:162: Error: .*not supported.* +.*:163: Error: .*not supported.* +.*:164: Error: .*not supported.* +.*:165: Error: .*not supported.* +.*:166: Error: .*not supported.* +.*:170: Error: .*not supported.* +.*:171: Error: .*not supported.* +.*:172: Error: .*not supported.* +.*:173: Error: .*not supported.* +.*:174: Error: .*not supported.* +.*:175: Error: .*not supported.* +.*:176: Error: .*not supported.* +.*:179: Error: .*bad register name.* +.*:180: Error: .*unknown vector operation.* +.*:181: Error: .*unknown vector operation.* +.*:182: Error: .*not supported.* +.*:183: Error: .*not supported.* +.*:184: Error: .*not supported.* +.*:185: Error: .*not supported.* +.*:186: Error: .*not supported.* +.*:187: Error: .*not supported.* +.*:188: Error: .*not supported.* +.*:189: Error: .*bad register name.* +.*:190: Error: .*unknown vector operation.* +.*:191: Error: .*unknown vector operation.* +.*:192: Error: .*not supported.* +.*:193: Error: .*not supported.* +.*:194: Error: .*not supported.* +.*:195: Error: .*not supported.* +.*:196: Error: .*not supported.* +.*:197: Error: .*not supported.* +.*:198: Error: .*not supported.* +GAS LISTING .* +#... +[ ]*1[ ]+\# Test \.arch \.noavx512XX +[ ]*2[ ]+\.text +[ ]*3[ ]+\?\?\?\? 62F27D4F vpabsb %zmm5, %zmm6\{%k7\} \# AVX512BW +[ ]*3[ ]+1CF5 +[ ]*4[ ]+\?\?\?\? 62F27D0F vpabsb %xmm5, %xmm6\{%k7\} \# AVX512BW \+ AVX512VL +[ ]*4[ ]+1CF5 +[ ]*5[ ]+\?\?\?\? 62F27D2F vpabsb %ymm5, %ymm6\{%k7\} \# AVX512BW \+ AVX512VL +[ ]*5[ ]+1CF5 +[ ]*6[ ]+\?\?\?\? 62F27D48 vpconflictd %zmm5, %zmm6 \# AVX412CD +[ ]*6[ ]+C4F5 +[ ]*7[ ]+\?\?\?\? 62F27D08 vpconflictd %xmm5, %xmm6 \# AVX412CD \+ AVX512VL +[ ]*7[ ]+C4F5 +[ ]*8[ ]+\?\?\?\? 62F27D28 vpconflictd %ymm5, %ymm6 \# AVX412CD \+ AVX512VL +[ ]*8[ ]+C4F5 +[ ]*9[ ]+\?\?\?\? 62F1FD4F vcvtpd2qq \(%ecx\), %zmm6\{%k7\} \# AVX512DQ +[ ]*9[ ]+7B31 +[ ]*10[ ]+\?\?\?\? 62F1FD0F vcvtpd2qq \(%ecx\), %xmm6\{%k7\} \# AVX512DQ \+ AVX512VL +[ ]*10[ ]+7B31 +[ ]*11[ ]+\?\?\?\? 62F1FD2F vcvtpd2qq \(%ecx\), %ymm6\{%k7\} \# AVX512DQ \+ AVX512VL +[ ]*11[ ]+7B31 +[ ]*12[ ]+\?\?\?\? 62F27D4F vexp2ps %zmm5, %zmm6\{%k7\} \# AVX512ER +[ ]*12[ ]+C8F5 +[ ]*13[ ]+\?\?\?\? 62F1D54F vaddpd %zmm4, %zmm5, %zmm6\{%k7\} \# AVX512F +[ ]*13[ ]+58F4 +[ ]*14[ ]+\?\?\?\? 62F1D50F vaddpd %xmm4, %xmm5, %xmm6\{%k7\} \# AVX512F \+ AVX512VL +[ ]*14[ ]+58F4 +[ ]*15[ ]+\?\?\?\? 62F1D52F vaddpd %ymm4, %ymm5, %ymm6\{%k7\} \# AVX512F \+ AVX512VL +[ ]*15[ ]+58F4 +[ ]*16[ ]+\?\?\?\? 62F2D54F vpmadd52luq %zmm4, %zmm5, %zmm6\{%k7\} \# AVX512IFMA +[ ]*16[ ]+B4F4 +[ ]*17[ ]+\?\?\?\? 62F2D50F vpmadd52luq %xmm4, %xmm5, %xmm6\{%k7\} \# AVX512IFMA \+ AVX512VL +[ ]*17[ ]+B4F4 +[ ]*18[ ]+\?\?\?\? 62F2D52F vpmadd52luq %ymm4, %ymm5, %ymm6\{%k7\} \# AVX512IFMA \+ AVX512VL +[ ]*18[ ]+B4F4 +[ ]*19[ ]+\?\?\?\? 62F2FD49 vgatherpf0dpd 23\(%ebp,%ymm7,8\)\{%k1\} \# AVX512PF +[ ]*19[ ]+C68CFD17 +[ ]*19[ ]+000000 +[ ]*20[ ]+\?\?\?\? 62F2554F vpermb %zmm4, %zmm5, %zmm6\{%k7\} \# AVX512VBMI +[ ]*20[ ]+8DF4 +[ ]*21[ ]+\?\?\?\? 62F2550F vpermb %xmm4, %xmm5, %xmm6\{%k7\} \# AVX512VBMI \+ AVX512VL +[ ]*21[ ]+8DF4 +[ ]*22[ ]+\?\?\?\? 62F2552F vpermb %ymm4, %ymm5, %ymm6\{%k7\} \# AVX512VBMI \+ AVX512VL +[ ]*22[ ]+8DF4 +[ ]*23[ ]+ +[ ]*24[ ]+\.arch \.noavx512bw +[ ]*25[ ]+vpabsb %zmm5, %zmm6\{%k7\} \# AVX512BW +[ ]*26[ ]+vpabsb %xmm5, %xmm6\{%k7\} \# AVX512BW \+ AVX512VL +[ ]*27[ ]+vpabsb %ymm5, %ymm6\{%k7\} \# AVX512BW \+ AVX512VL +[ ]*28[ ]+\?\?\?\? 62F27D48 vpconflictd %zmm5, %zmm6 \# AVX412CD +[ ]*28[ ]+C4F5 +[ ]*29[ ]+\?\?\?\? 62F27D08 vpconflictd %xmm5, %xmm6 \# AVX412CD \+ AVX512VL +[ ]*29[ ]+C4F5 +[ ]*30[ ]+\?\?\?\? 62F27D28 vpconflictd %ymm5, %ymm6 \# AVX412CD \+ AVX512VL +[ ]*30[ ]+C4F5 +[ ]*31[ ]+\?\?\?\? 62F1FD4F vcvtpd2qq \(%ecx\), %zmm6\{%k7\} \# AVX512DQ +[ ]*31[ ]+7B31 +[ ]*32[ ]+\?\?\?\? 62F1FD0F vcvtpd2qq \(%ecx\), %xmm6\{%k7\} \# AVX512DQ \+ AVX512VL +\fGAS LISTING .* + + +[ ]*32[ ]+7B31 +[ ]*33[ ]+\?\?\?\? 62F1FD2F vcvtpd2qq \(%ecx\), %ymm6\{%k7\} \# AVX512DQ \+ AVX512VL +[ ]*33[ ]+7B31 +[ ]*34[ ]+\?\?\?\? 62F27D4F vexp2ps %zmm5, %zmm6\{%k7\} \# AVX512ER +[ ]*34[ ]+C8F5 +[ ]*35[ ]+\?\?\?\? 62F1D54F vaddpd %zmm4, %zmm5, %zmm6\{%k7\} \# AVX512F +[ ]*35[ ]+58F4 +[ ]*36[ ]+\?\?\?\? 62F1D50F vaddpd %xmm4, %xmm5, %xmm6\{%k7\} \# AVX512F \+ AVX512VL +[ ]*36[ ]+58F4 +[ ]*37[ ]+\?\?\?\? 62F1D52F vaddpd %ymm4, %ymm5, %ymm6\{%k7\} \# AVX512F \+ AVX512VL +[ ]*37[ ]+58F4 +[ ]*38[ ]+\?\?\?\? 62F2D54F vpmadd52luq %zmm4, %zmm5, %zmm6\{%k7\} \# AVX512IFMA +[ ]*38[ ]+B4F4 +[ ]*39[ ]+\?\?\?\? 62F2D50F vpmadd52luq %xmm4, %xmm5, %xmm6\{%k7\} \# AVX512IFMA \+ AVX512VL +[ ]*39[ ]+B4F4 +[ ]*40[ ]+\?\?\?\? 62F2D52F vpmadd52luq %ymm4, %ymm5, %ymm6\{%k7\} \# AVX512IFMA \+ AVX512VL +[ ]*40[ ]+B4F4 +[ ]*41[ ]+\?\?\?\? 62F2FD49 vgatherpf0dpd 23\(%ebp,%ymm7,8\)\{%k1\} \# AVX512PF +[ ]*41[ ]+C68CFD17 +[ ]*41[ ]+000000 +[ ]*42[ ]+\?\?\?\? 62F2554F vpermb %zmm4, %zmm5, %zmm6\{%k7\} \# AVX512VBMI +[ ]*42[ ]+8DF4 +[ ]*43[ ]+\?\?\?\? 62F2550F vpermb %xmm4, %xmm5, %xmm6\{%k7\} \# AVX512VBMI \+ AVX512VL +[ ]*43[ ]+8DF4 +[ ]*44[ ]+\?\?\?\? 62F2552F vpermb %ymm4, %ymm5, %ymm6\{%k7\} \# AVX512VBMI \+ AVX512VL +[ ]*44[ ]+8DF4 +[ ]*45[ ]+ +[ ]*46[ ]+\.arch \.noavx512cd +[ ]*47[ ]+vpabsb %zmm5, %zmm6\{%k7\} \# AVX512BW +[ ]*48[ ]+vpabsb %xmm5, %xmm6\{%k7\} \# AVX512BW \+ AVX512VL +[ ]*49[ ]+vpabsb %ymm5, %ymm6\{%k7\} \# AVX512BW \+ AVX512VL +[ ]*50[ ]+vpconflictd %zmm5, %zmm6 \# AVX412CD +[ ]*51[ ]+vpconflictd %xmm5, %xmm6 \# AVX412CD \+ AVX512VL +[ ]*52[ ]+vpconflictd %ymm5, %ymm6 \# AVX412CD \+ AVX512VL +[ ]*53[ ]+\?\?\?\? 62F1FD4F vcvtpd2qq \(%ecx\), %zmm6\{%k7\} \# AVX512DQ +[ ]*53[ ]+7B31 +[ ]*54[ ]+\?\?\?\? 62F1FD0F vcvtpd2qq \(%ecx\), %xmm6\{%k7\} \# AVX512DQ \+ AVX512VL +[ ]*54[ ]+7B31 +[ ]*55[ ]+\?\?\?\? 62F1FD2F vcvtpd2qq \(%ecx\), %ymm6\{%k7\} \# AVX512DQ \+ AVX512VL +[ ]*55[ ]+7B31 +[ ]*56[ ]+\?\?\?\? 62F27D4F vexp2ps %zmm5, %zmm6\{%k7\} \# AVX512ER +[ ]*56[ ]+C8F5 +[ ]*57[ ]+\?\?\?\? 62F1D54F vaddpd %zmm4, %zmm5, %zmm6\{%k7\} \# AVX512F +[ ]*57[ ]+58F4 +[ ]*58[ ]+\?\?\?\? 62F1D50F vaddpd %xmm4, %xmm5, %xmm6\{%k7\} \# AVX512F \+ AVX512VL +[ ]*58[ ]+58F4 +[ ]*59[ ]+\?\?\?\? 62F1D52F vaddpd %ymm4, %ymm5, %ymm6\{%k7\} \# AVX512F \+ AVX512VL +[ ]*59[ ]+58F4 +[ ]*60[ ]+\?\?\?\? 62F2D54F vpmadd52luq %zmm4, %zmm5, %zmm6\{%k7\} \# AVX512IFMA +[ ]*60[ ]+B4F4 +[ ]*61[ ]+\?\?\?\? 62F2D50F vpmadd52luq %xmm4, %xmm5, %xmm6\{%k7\} \# AVX512IFMA \+ AVX512VL +[ ]*61[ ]+B4F4 +[ ]*62[ ]+\?\?\?\? 62F2D52F vpmadd52luq %ymm4, %ymm5, %ymm6\{%k7\} \# AVX512IFMA \+ AVX512VL +[ ]*62[ ]+B4F4 +[ ]*63[ ]+\?\?\?\? 62F2FD49 vgatherpf0dpd 23\(%ebp,%ymm7,8\)\{%k1\} \# AVX512PF +[ ]*63[ ]+C68CFD17 +[ ]*63[ ]+000000 +\fGAS LISTING .* + + +[ ]*64[ ]+\?\?\?\? 62F2554F vpermb %zmm4, %zmm5, %zmm6\{%k7\} \# AVX512VBMI +[ ]*64[ ]+8DF4 +[ ]*65[ ]+\?\?\?\? 62F2550F vpermb %xmm4, %xmm5, %xmm6\{%k7\} \# AVX512VBMI \+ AVX512VL +[ ]*65[ ]+8DF4 +[ ]*66[ ]+\?\?\?\? 62F2552F vpermb %ymm4, %ymm5, %ymm6\{%k7\} \# AVX512VBMI \+ AVX512VL +[ ]*66[ ]+8DF4 +[ ]*67[ ]+ +[ ]*68[ ]+\.arch \.noavx512dq +[ ]*69[ ]+vpabsb %zmm5, %zmm6\{%k7\} \# AVX512BW +[ ]*70[ ]+vpabsb %xmm5, %xmm6\{%k7\} \# AVX512BW \+ AVX512VL +[ ]*71[ ]+vpabsb %ymm5, %ymm6\{%k7\} \# AVX512BW \+ AVX512VL +[ ]*72[ ]+vpconflictd %zmm5, %zmm6 \# AVX412CD +[ ]*73[ ]+vpconflictd %xmm5, %xmm6 \# AVX412CD \+ AVX512VL +[ ]*74[ ]+vpconflictd %ymm5, %ymm6 \# AVX412CD \+ AVX512VL +[ ]*75[ ]+vcvtpd2qq \(%ecx\), %zmm6\{%k7\} \# AVX512DQ +[ ]*76[ ]+vcvtpd2qq \(%ecx\), %xmm6\{%k7\} \# AVX512DQ \+ AVX512VL +[ ]*77[ ]+vcvtpd2qq \(%ecx\), %ymm6\{%k7\} \# AVX512DQ \+ AVX512VL +[ ]*78[ ]+\?\?\?\? 62F27D4F vexp2ps %zmm5, %zmm6\{%k7\} \# AVX512ER +[ ]*78[ ]+C8F5 +[ ]*79[ ]+\?\?\?\? 62F1D54F vaddpd %zmm4, %zmm5, %zmm6\{%k7\} \# AVX512F +[ ]*79[ ]+58F4 +[ ]*80[ ]+\?\?\?\? 62F1D50F vaddpd %xmm4, %xmm5, %xmm6\{%k7\} \# AVX512F \+ AVX512VL +[ ]*80[ ]+58F4 +[ ]*81[ ]+\?\?\?\? 62F1D52F vaddpd %ymm4, %ymm5, %ymm6\{%k7\} \# AVX512F \+ AVX512VL +[ ]*81[ ]+58F4 +[ ]*82[ ]+\?\?\?\? 62F2D54F vpmadd52luq %zmm4, %zmm5, %zmm6\{%k7\} \# AVX512IFMA +[ ]*82[ ]+B4F4 +[ ]*83[ ]+\?\?\?\? 62F2D50F vpmadd52luq %xmm4, %xmm5, %xmm6\{%k7\} \# AVX512IFMA \+ AVX512VL +[ ]*83[ ]+B4F4 +[ ]*84[ ]+\?\?\?\? 62F2D52F vpmadd52luq %ymm4, %ymm5, %ymm6\{%k7\} \# AVX512IFMA \+ AVX512VL +[ ]*84[ ]+B4F4 +[ ]*85[ ]+\?\?\?\? 62F2FD49 vgatherpf0dpd 23\(%ebp,%ymm7,8\)\{%k1\} \# AVX512PF +[ ]*85[ ]+C68CFD17 +[ ]*85[ ]+000000 +[ ]*86[ ]+\?\?\?\? 62F2554F vpermb %zmm4, %zmm5, %zmm6\{%k7\} \# AVX512VBMI +[ ]*86[ ]+8DF4 +[ ]*87[ ]+\?\?\?\? 62F2550F vpermb %xmm4, %xmm5, %xmm6\{%k7\} \# AVX512VBMI \+ AVX512VL +[ ]*87[ ]+8DF4 +[ ]*88[ ]+\?\?\?\? 62F2552F vpermb %ymm4, %ymm5, %ymm6\{%k7\} \# AVX512VBMI \+ AVX512VL +[ ]*88[ ]+8DF4 +[ ]*89[ ]+ +[ ]*90[ ]+\.arch \.noavx512er +[ ]*91[ ]+vpabsb %zmm5, %zmm6\{%k7\} \# AVX512BW +[ ]*92[ ]+vpabsb %xmm5, %xmm6\{%k7\} \# AVX512BW \+ AVX512VL +[ ]*93[ ]+vpabsb %ymm5, %ymm6\{%k7\} \# AVX512BW \+ AVX512VL +[ ]*94[ ]+vpconflictd %zmm5, %zmm6 \# AVX412CD +[ ]*95[ ]+vpconflictd %xmm5, %xmm6 \# AVX412CD \+ AVX512VL +[ ]*96[ ]+vpconflictd %ymm5, %ymm6 \# AVX412CD \+ AVX512VL +[ ]*97[ ]+vcvtpd2qq \(%ecx\), %zmm6\{%k7\} \# AVX512DQ +[ ]*98[ ]+vcvtpd2qq \(%ecx\), %xmm6\{%k7\} \# AVX512DQ \+ AVX512VL +[ ]*99[ ]+vcvtpd2qq \(%ecx\), %ymm6\{%k7\} \# AVX512DQ \+ AVX512VL +[ ]*100[ ]+vexp2ps %zmm5, %zmm6\{%k7\} \# AVX512ER +[ ]*101[ ]+\?\?\?\? 62F1D54F vaddpd %zmm4, %zmm5, %zmm6\{%k7\} \# AVX512F +[ ]*101[ ]+58F4 +[ ]*102[ ]+\?\?\?\? 62F1D50F vaddpd %xmm4, %xmm5, %xmm6\{%k7\} \# AVX512F \+ AVX512VL +[ ]*102[ ]+58F4 +[ ]*103[ ]+\?\?\?\? 62F1D52F vaddpd %ymm4, %ymm5, %ymm6\{%k7\} \# AVX512F \+ AVX512VL +\fGAS LISTING .* + + +[ ]*103[ ]+58F4 +[ ]*104[ ]+\?\?\?\? 62F2D54F vpmadd52luq %zmm4, %zmm5, %zmm6\{%k7\} \# AVX512IFMA +[ ]*104[ ]+B4F4 +[ ]*105[ ]+\?\?\?\? 62F2D50F vpmadd52luq %xmm4, %xmm5, %xmm6\{%k7\} \# AVX512IFMA \+ AVX512VL +[ ]*105[ ]+B4F4 +[ ]*106[ ]+\?\?\?\? 62F2D52F vpmadd52luq %ymm4, %ymm5, %ymm6\{%k7\} \# AVX512IFMA \+ AVX512VL +[ ]*106[ ]+B4F4 +[ ]*107[ ]+\?\?\?\? 62F2FD49 vgatherpf0dpd 23\(%ebp,%ymm7,8\)\{%k1\} \# AVX512PF +[ ]*107[ ]+C68CFD17 +[ ]*107[ ]+000000 +[ ]*108[ ]+\?\?\?\? 62F2554F vpermb %zmm4, %zmm5, %zmm6\{%k7\} \# AVX512VBMI +[ ]*108[ ]+8DF4 +[ ]*109[ ]+\?\?\?\? 62F2550F vpermb %xmm4, %xmm5, %xmm6\{%k7\} \# AVX512VBMI \+ AVX512VL +[ ]*109[ ]+8DF4 +[ ]*110[ ]+\?\?\?\? 62F2552F vpermb %ymm4, %ymm5, %ymm6\{%k7\} \# AVX512VBMI \+ AVX512VL +[ ]*110[ ]+8DF4 +[ ]*111[ ]+ +[ ]*112[ ]+\.arch \.noavx512ifma +[ ]*113[ ]+vpabsb %zmm5, %zmm6\{%k7\} \# AVX512BW +[ ]*114[ ]+vpabsb %xmm5, %xmm6\{%k7\} \# AVX512BW \+ AVX512VL +[ ]*115[ ]+vpabsb %ymm5, %ymm6\{%k7\} \# AVX512BW \+ AVX512VL +[ ]*116[ ]+vpconflictd %zmm5, %zmm6 \# AVX412CD +[ ]*117[ ]+vpconflictd %xmm5, %xmm6 \# AVX412CD \+ AVX512VL +[ ]*118[ ]+vpconflictd %ymm5, %ymm6 \# AVX412CD \+ AVX512VL +[ ]*119[ ]+vcvtpd2qq \(%ecx\), %zmm6\{%k7\} \# AVX512DQ +[ ]*120[ ]+vcvtpd2qq \(%ecx\), %xmm6\{%k7\} \# AVX512DQ \+ AVX512VL +[ ]*121[ ]+vcvtpd2qq \(%ecx\), %ymm6\{%k7\} \# AVX512DQ \+ AVX512VL +[ ]*122[ ]+vexp2ps %zmm5, %zmm6\{%k7\} \# AVX512ER +[ ]*123[ ]+\?\?\?\? 62F1D54F vaddpd %zmm4, %zmm5, %zmm6\{%k7\} \# AVX512F +[ ]*123[ ]+58F4 +[ ]*124[ ]+\?\?\?\? 62F1D50F vaddpd %xmm4, %xmm5, %xmm6\{%k7\} \# AVX512F \+ AVX512VL +[ ]*124[ ]+58F4 +[ ]*125[ ]+\?\?\?\? 62F1D52F vaddpd %ymm4, %ymm5, %ymm6\{%k7\} \# AVX512F \+ AVX512VL +[ ]*125[ ]+58F4 +[ ]*126[ ]+vpmadd52luq %zmm4, %zmm5, %zmm6\{%k7\} \# AVX512IFMA +[ ]*127[ ]+vpmadd52luq %xmm4, %xmm5, %xmm6\{%k7\} \# AVX512IFMA \+ AVX512VL +[ ]*128[ ]+vpmadd52luq %ymm4, %ymm5, %ymm6\{%k7\} \# AVX512IFMA \+ AVX512VL +[ ]*129[ ]+\?\?\?\? 62F2FD49 vgatherpf0dpd 23\(%ebp,%ymm7,8\)\{%k1\} \# AVX512PF +[ ]*129[ ]+C68CFD17 +[ ]*129[ ]+000000 +[ ]*130[ ]+\?\?\?\? 62F2554F vpermb %zmm4, %zmm5, %zmm6\{%k7\} \# AVX512VBMI +[ ]*130[ ]+8DF4 +[ ]*131[ ]+\?\?\?\? 62F2550F vpermb %xmm4, %xmm5, %xmm6\{%k7\} \# AVX512VBMI \+ AVX512VL +[ ]*131[ ]+8DF4 +[ ]*132[ ]+\?\?\?\? 62F2552F vpermb %ymm4, %ymm5, %ymm6\{%k7\} \# AVX512VBMI \+ AVX512VL +[ ]*132[ ]+8DF4 +[ ]*133[ ]+ +[ ]*134[ ]+\.arch \.noavx512pf +[ ]*135[ ]+vpabsb %zmm5, %zmm6\{%k7\} \# AVX512BW +[ ]*136[ ]+vpabsb %xmm5, %xmm6\{%k7\} \# AVX512BW \+ AVX512VL +[ ]*137[ ]+vpabsb %ymm5, %ymm6\{%k7\} \# AVX512BW \+ AVX512VL +[ ]*138[ ]+vpconflictd %zmm5, %zmm6 \# AVX412CD +[ ]*139[ ]+vpconflictd %xmm5, %xmm6 \# AVX412CD \+ AVX512VL +[ ]*140[ ]+vpconflictd %ymm5, %ymm6 \# AVX412CD \+ AVX512VL +[ ]*141[ ]+vcvtpd2qq \(%ecx\), %zmm6\{%k7\} \# AVX512DQ +[ ]*142[ ]+vcvtpd2qq \(%ecx\), %xmm6\{%k7\} \# AVX512DQ \+ AVX512VL +[ ]*143[ ]+vcvtpd2qq \(%ecx\), %ymm6\{%k7\} \# AVX512DQ \+ AVX512VL +\fGAS LISTING .* + + +[ ]*144[ ]+vexp2ps %zmm5, %zmm6\{%k7\} \# AVX512ER +[ ]*145[ ]+\?\?\?\? 62F1D54F vaddpd %zmm4, %zmm5, %zmm6\{%k7\} \# AVX512F +[ ]*145[ ]+58F4 +[ ]*146[ ]+\?\?\?\? 62F1D50F vaddpd %xmm4, %xmm5, %xmm6\{%k7\} \# AVX512F \+ AVX512VL +[ ]*146[ ]+58F4 +[ ]*147[ ]+\?\?\?\? 62F1D52F vaddpd %ymm4, %ymm5, %ymm6\{%k7\} \# AVX512F \+ AVX512VL +[ ]*147[ ]+58F4 +[ ]*148[ ]+vpmadd52luq %zmm4, %zmm5, %zmm6\{%k7\} \# AVX512IFMA +[ ]*149[ ]+vpmadd52luq %xmm4, %xmm5, %xmm6\{%k7\} \# AVX512IFMA \+ AVX512VL +[ ]*150[ ]+vpmadd52luq %ymm4, %ymm5, %ymm6\{%k7\} \# AVX512IFMA \+ AVX512VL +[ ]*151[ ]+vgatherpf0dpd 23\(%ebp,%ymm7,8\)\{%k1\} \# AVX512PF +[ ]*152[ ]+\?\?\?\? 62F2554F vpermb %zmm4, %zmm5, %zmm6\{%k7\} \# AVX512VBMI +[ ]*152[ ]+8DF4 +[ ]*153[ ]+\?\?\?\? 62F2550F vpermb %xmm4, %xmm5, %xmm6\{%k7\} \# AVX512VBMI \+ AVX512VL +[ ]*153[ ]+8DF4 +[ ]*154[ ]+\?\?\?\? 62F2552F vpermb %ymm4, %ymm5, %ymm6\{%k7\} \# AVX512VBMI \+ AVX512VL +[ ]*154[ ]+8DF4 +[ ]*155[ ]+ +[ ]*156[ ]+\.arch \.noavx512vbmi +[ ]*157[ ]+vpabsb %zmm5, %zmm6\{%k7\} \# AVX512BW +[ ]*158[ ]+vpabsb %xmm5, %xmm6\{%k7\} \# AVX512BW \+ AVX512VL +[ ]*159[ ]+vpabsb %ymm5, %ymm6\{%k7\} \# AVX512BW \+ AVX512VL +[ ]*160[ ]+vpconflictd %zmm5, %zmm6 \# AVX412CD +[ ]*161[ ]+vpconflictd %xmm5, %xmm6 \# AVX412CD \+ AVX512VL +[ ]*162[ ]+vpconflictd %ymm5, %ymm6 \# AVX412CD \+ AVX512VL +[ ]*163[ ]+vcvtpd2qq \(%ecx\), %zmm6\{%k7\} \# AVX512DQ +[ ]*164[ ]+vcvtpd2qq \(%ecx\), %xmm6\{%k7\} \# AVX512DQ \+ AVX512VL +[ ]*165[ ]+vcvtpd2qq \(%ecx\), %ymm6\{%k7\} \# AVX512DQ \+ AVX512VL +[ ]*166[ ]+vexp2ps %zmm5, %zmm6\{%k7\} \# AVX512ER +[ ]*167[ ]+\?\?\?\? 62F1D54F vaddpd %zmm4, %zmm5, %zmm6\{%k7\} \# AVX512F +[ ]*167[ ]+58F4 +[ ]*168[ ]+\?\?\?\? 62F1D50F vaddpd %xmm4, %xmm5, %xmm6\{%k7\} \# AVX512F \+ AVX512VL +[ ]*168[ ]+58F4 +[ ]*169[ ]+\?\?\?\? 62F1D52F vaddpd %ymm4, %ymm5, %ymm6\{%k7\} \# AVX512F \+ AVX512VL +[ ]*169[ ]+58F4 +[ ]*170[ ]+vpmadd52luq %zmm4, %zmm5, %zmm6\{%k7\} \# AVX512IFMA +[ ]*171[ ]+vpmadd52luq %xmm4, %xmm5, %xmm6\{%k7\} \# AVX512IFMA \+ AVX512VL +[ ]*172[ ]+vpmadd52luq %ymm4, %ymm5, %ymm6\{%k7\} \# AVX512IFMA \+ AVX512VL +[ ]*173[ ]+vgatherpf0dpd 23\(%ebp,%ymm7,8\)\{%k1\} \# AVX512PF +[ ]*174[ ]+vpermb %zmm4, %zmm5, %zmm6\{%k7\} \# AVX512VBMI +[ ]*175[ ]+vpermb %xmm4, %xmm5, %xmm6\{%k7\} \# AVX512VBMI \+ AVX512VL +[ ]*176[ ]+vpermb %ymm4, %ymm5, %ymm6\{%k7\} \# AVX512VBMI \+ AVX512VL +[ ]*177[ ]+ +[ ]*178[ ]+\.arch \.noavx512f +[ ]*179[ ]+vpabsb %zmm5, %zmm6\{%k7\} \# AVX512BW +[ ]*180[ ]+vpabsb %xmm5, %xmm6\{%k7\} \# AVX512BW \+ AVX512VL +[ ]*181[ ]+vpabsb %ymm5, %ymm6\{%k7\} \# AVX512BW \+ AVX512VL +[ ]*182[ ]+vpconflictd %zmm5, %zmm6 \# AVX412CD +[ ]*183[ ]+vpconflictd %xmm5, %xmm6 \# AVX412CD \+ AVX512VL +[ ]*184[ ]+vpconflictd %ymm5, %ymm6 \# AVX412CD \+ AVX512VL +[ ]*185[ ]+vcvtpd2qq \(%ecx\), %zmm6\{%k7\} \# AVX512DQ +[ ]*186[ ]+vcvtpd2qq \(%ecx\), %xmm6\{%k7\} \# AVX512DQ \+ AVX512VL +[ ]*187[ ]+vcvtpd2qq \(%ecx\), %ymm6\{%k7\} \# AVX512DQ \+ AVX512VL +[ ]*188[ ]+vexp2ps %zmm5, %zmm6\{%k7\} \# AVX512ER +[ ]*189[ ]+vaddpd %zmm4, %zmm5, %zmm6\{%k7\} \# AVX512F +[ ]*190[ ]+vaddpd %xmm4, %xmm5, %xmm6\{%k7\} \# AVX512F \+ AVX512VL +[ ]*191[ ]+vaddpd %ymm4, %ymm5, %ymm6\{%k7\} \# AVX512F \+ AVX512VL +\fGAS LISTING .* + + +[ ]*192[ ]+vpmadd52luq %zmm4, %zmm5, %zmm6\{%k7\} \# AVX512IFMA +[ ]*193[ ]+vpmadd52luq %xmm4, %xmm5, %xmm6\{%k7\} \# AVX512IFMA \+ AVX512VL +[ ]*194[ ]+vpmadd52luq %ymm4, %ymm5, %ymm6\{%k7\} \# AVX512IFMA \+ AVX512VL +[ ]*195[ ]+vgatherpf0dpd 23\(%ebp,%ymm7,8\)\{%k1\} \# AVX512PF +[ ]*196[ ]+vpermb %zmm4, %zmm5, %zmm6\{%k7\} \# AVX512VBMI +[ ]*197[ ]+vpermb %xmm4, %xmm5, %xmm6\{%k7\} \# AVX512VBMI \+ AVX512VL +[ ]*198[ ]+vpermb %ymm4, %ymm5, %ymm6\{%k7\} \# AVX512VBMI \+ AVX512VL +[ ]*199[ ]+ +[ ]*200[ ]+\?\?\?\? C4E2791C vpabsb %xmm5, %xmm6 +[ ]*200[ ]+F5 +[ ]*201[ ]+\?\?\?\? C4E27D1C vpabsb %ymm5, %ymm6 +[ ]*201[ ]+F5 +[ ]*202[ ]+\?\?\?\? C5D158F4 vaddpd %xmm4, %xmm5, %xmm6 +[ ]*203[ ]+\?\?\?\? C5D558F4 vaddpd %ymm4, %ymm5, %ymm6 +[ ]*204[ ]+\?\?\?\? 660F381C pabsb %xmm5, %xmm6 +[ ]*204[ ]+F5 +[ ]*205[ ]+\?\?\?\? 660F58F4 addpd %xmm4, %xmm6 +[ ]*206[ ]+ +[ ]*207[ ]+\?\?\?\? 0F1F8000 \.p2align 4 +[ ]*207[ ]+000000 +#pass diff --git a/gas/testsuite/gas/i386/noavx512-1.s b/gas/testsuite/gas/i386/noavx512-1.s new file mode 100644 index 0000000..786f244 --- /dev/null +++ b/gas/testsuite/gas/i386/noavx512-1.s @@ -0,0 +1,207 @@ +# Test .arch .noavx512XX + .text + vpabsb %zmm5, %zmm6{%k7} # AVX512BW + vpabsb %xmm5, %xmm6{%k7} # AVX512BW + AVX512VL + vpabsb %ymm5, %ymm6{%k7} # AVX512BW + AVX512VL + vpconflictd %zmm5, %zmm6 # AVX412CD + vpconflictd %xmm5, %xmm6 # AVX412CD + AVX512VL + vpconflictd %ymm5, %ymm6 # AVX412CD + AVX512VL + vcvtpd2qq (%ecx), %zmm6{%k7} # AVX512DQ + vcvtpd2qq (%ecx), %xmm6{%k7} # AVX512DQ + AVX512VL + vcvtpd2qq (%ecx), %ymm6{%k7} # AVX512DQ + AVX512VL + vexp2ps %zmm5, %zmm6{%k7} # AVX512ER + vaddpd %zmm4, %zmm5, %zmm6{%k7} # AVX512F + vaddpd %xmm4, %xmm5, %xmm6{%k7} # AVX512F + AVX512VL + vaddpd %ymm4, %ymm5, %ymm6{%k7} # AVX512F + AVX512VL + vpmadd52luq %zmm4, %zmm5, %zmm6{%k7} # AVX512IFMA + vpmadd52luq %xmm4, %xmm5, %xmm6{%k7} # AVX512IFMA + AVX512VL + vpmadd52luq %ymm4, %ymm5, %ymm6{%k7} # AVX512IFMA + AVX512VL + vgatherpf0dpd 23(%ebp,%ymm7,8){%k1} # AVX512PF + vpermb %zmm4, %zmm5, %zmm6{%k7} # AVX512VBMI + vpermb %xmm4, %xmm5, %xmm6{%k7} # AVX512VBMI + AVX512VL + vpermb %ymm4, %ymm5, %ymm6{%k7} # AVX512VBMI + AVX512VL + + .arch .noavx512bw + vpabsb %zmm5, %zmm6{%k7} # AVX512BW + vpabsb %xmm5, %xmm6{%k7} # AVX512BW + AVX512VL + vpabsb %ymm5, %ymm6{%k7} # AVX512BW + AVX512VL + vpconflictd %zmm5, %zmm6 # AVX412CD + vpconflictd %xmm5, %xmm6 # AVX412CD + AVX512VL + vpconflictd %ymm5, %ymm6 # AVX412CD + AVX512VL + vcvtpd2qq (%ecx), %zmm6{%k7} # AVX512DQ + vcvtpd2qq (%ecx), %xmm6{%k7} # AVX512DQ + AVX512VL + vcvtpd2qq (%ecx), %ymm6{%k7} # AVX512DQ + AVX512VL + vexp2ps %zmm5, %zmm6{%k7} # AVX512ER + vaddpd %zmm4, %zmm5, %zmm6{%k7} # AVX512F + vaddpd %xmm4, %xmm5, %xmm6{%k7} # AVX512F + AVX512VL + vaddpd %ymm4, %ymm5, %ymm6{%k7} # AVX512F + AVX512VL + vpmadd52luq %zmm4, %zmm5, %zmm6{%k7} # AVX512IFMA + vpmadd52luq %xmm4, %xmm5, %xmm6{%k7} # AVX512IFMA + AVX512VL + vpmadd52luq %ymm4, %ymm5, %ymm6{%k7} # AVX512IFMA + AVX512VL + vgatherpf0dpd 23(%ebp,%ymm7,8){%k1} # AVX512PF + vpermb %zmm4, %zmm5, %zmm6{%k7} # AVX512VBMI + vpermb %xmm4, %xmm5, %xmm6{%k7} # AVX512VBMI + AVX512VL + vpermb %ymm4, %ymm5, %ymm6{%k7} # AVX512VBMI + AVX512VL + + .arch .noavx512cd + vpabsb %zmm5, %zmm6{%k7} # AVX512BW + vpabsb %xmm5, %xmm6{%k7} # AVX512BW + AVX512VL + vpabsb %ymm5, %ymm6{%k7} # AVX512BW + AVX512VL + vpconflictd %zmm5, %zmm6 # AVX412CD + vpconflictd %xmm5, %xmm6 # AVX412CD + AVX512VL + vpconflictd %ymm5, %ymm6 # AVX412CD + AVX512VL + vcvtpd2qq (%ecx), %zmm6{%k7} # AVX512DQ + vcvtpd2qq (%ecx), %xmm6{%k7} # AVX512DQ + AVX512VL + vcvtpd2qq (%ecx), %ymm6{%k7} # AVX512DQ + AVX512VL + vexp2ps %zmm5, %zmm6{%k7} # AVX512ER + vaddpd %zmm4, %zmm5, %zmm6{%k7} # AVX512F + vaddpd %xmm4, %xmm5, %xmm6{%k7} # AVX512F + AVX512VL + vaddpd %ymm4, %ymm5, %ymm6{%k7} # AVX512F + AVX512VL + vpmadd52luq %zmm4, %zmm5, %zmm6{%k7} # AVX512IFMA + vpmadd52luq %xmm4, %xmm5, %xmm6{%k7} # AVX512IFMA + AVX512VL + vpmadd52luq %ymm4, %ymm5, %ymm6{%k7} # AVX512IFMA + AVX512VL + vgatherpf0dpd 23(%ebp,%ymm7,8){%k1} # AVX512PF + vpermb %zmm4, %zmm5, %zmm6{%k7} # AVX512VBMI + vpermb %xmm4, %xmm5, %xmm6{%k7} # AVX512VBMI + AVX512VL + vpermb %ymm4, %ymm5, %ymm6{%k7} # AVX512VBMI + AVX512VL + + .arch .noavx512dq + vpabsb %zmm5, %zmm6{%k7} # AVX512BW + vpabsb %xmm5, %xmm6{%k7} # AVX512BW + AVX512VL + vpabsb %ymm5, %ymm6{%k7} # AVX512BW + AVX512VL + vpconflictd %zmm5, %zmm6 # AVX412CD + vpconflictd %xmm5, %xmm6 # AVX412CD + AVX512VL + vpconflictd %ymm5, %ymm6 # AVX412CD + AVX512VL + vcvtpd2qq (%ecx), %zmm6{%k7} # AVX512DQ + vcvtpd2qq (%ecx), %xmm6{%k7} # AVX512DQ + AVX512VL + vcvtpd2qq (%ecx), %ymm6{%k7} # AVX512DQ + AVX512VL + vexp2ps %zmm5, %zmm6{%k7} # AVX512ER + vaddpd %zmm4, %zmm5, %zmm6{%k7} # AVX512F + vaddpd %xmm4, %xmm5, %xmm6{%k7} # AVX512F + AVX512VL + vaddpd %ymm4, %ymm5, %ymm6{%k7} # AVX512F + AVX512VL + vpmadd52luq %zmm4, %zmm5, %zmm6{%k7} # AVX512IFMA + vpmadd52luq %xmm4, %xmm5, %xmm6{%k7} # AVX512IFMA + AVX512VL + vpmadd52luq %ymm4, %ymm5, %ymm6{%k7} # AVX512IFMA + AVX512VL + vgatherpf0dpd 23(%ebp,%ymm7,8){%k1} # AVX512PF + vpermb %zmm4, %zmm5, %zmm6{%k7} # AVX512VBMI + vpermb %xmm4, %xmm5, %xmm6{%k7} # AVX512VBMI + AVX512VL + vpermb %ymm4, %ymm5, %ymm6{%k7} # AVX512VBMI + AVX512VL + + .arch .noavx512er + vpabsb %zmm5, %zmm6{%k7} # AVX512BW + vpabsb %xmm5, %xmm6{%k7} # AVX512BW + AVX512VL + vpabsb %ymm5, %ymm6{%k7} # AVX512BW + AVX512VL + vpconflictd %zmm5, %zmm6 # AVX412CD + vpconflictd %xmm5, %xmm6 # AVX412CD + AVX512VL + vpconflictd %ymm5, %ymm6 # AVX412CD + AVX512VL + vcvtpd2qq (%ecx), %zmm6{%k7} # AVX512DQ + vcvtpd2qq (%ecx), %xmm6{%k7} # AVX512DQ + AVX512VL + vcvtpd2qq (%ecx), %ymm6{%k7} # AVX512DQ + AVX512VL + vexp2ps %zmm5, %zmm6{%k7} # AVX512ER + vaddpd %zmm4, %zmm5, %zmm6{%k7} # AVX512F + vaddpd %xmm4, %xmm5, %xmm6{%k7} # AVX512F + AVX512VL + vaddpd %ymm4, %ymm5, %ymm6{%k7} # AVX512F + AVX512VL + vpmadd52luq %zmm4, %zmm5, %zmm6{%k7} # AVX512IFMA + vpmadd52luq %xmm4, %xmm5, %xmm6{%k7} # AVX512IFMA + AVX512VL + vpmadd52luq %ymm4, %ymm5, %ymm6{%k7} # AVX512IFMA + AVX512VL + vgatherpf0dpd 23(%ebp,%ymm7,8){%k1} # AVX512PF + vpermb %zmm4, %zmm5, %zmm6{%k7} # AVX512VBMI + vpermb %xmm4, %xmm5, %xmm6{%k7} # AVX512VBMI + AVX512VL + vpermb %ymm4, %ymm5, %ymm6{%k7} # AVX512VBMI + AVX512VL + + .arch .noavx512ifma + vpabsb %zmm5, %zmm6{%k7} # AVX512BW + vpabsb %xmm5, %xmm6{%k7} # AVX512BW + AVX512VL + vpabsb %ymm5, %ymm6{%k7} # AVX512BW + AVX512VL + vpconflictd %zmm5, %zmm6 # AVX412CD + vpconflictd %xmm5, %xmm6 # AVX412CD + AVX512VL + vpconflictd %ymm5, %ymm6 # AVX412CD + AVX512VL + vcvtpd2qq (%ecx), %zmm6{%k7} # AVX512DQ + vcvtpd2qq (%ecx), %xmm6{%k7} # AVX512DQ + AVX512VL + vcvtpd2qq (%ecx), %ymm6{%k7} # AVX512DQ + AVX512VL + vexp2ps %zmm5, %zmm6{%k7} # AVX512ER + vaddpd %zmm4, %zmm5, %zmm6{%k7} # AVX512F + vaddpd %xmm4, %xmm5, %xmm6{%k7} # AVX512F + AVX512VL + vaddpd %ymm4, %ymm5, %ymm6{%k7} # AVX512F + AVX512VL + vpmadd52luq %zmm4, %zmm5, %zmm6{%k7} # AVX512IFMA + vpmadd52luq %xmm4, %xmm5, %xmm6{%k7} # AVX512IFMA + AVX512VL + vpmadd52luq %ymm4, %ymm5, %ymm6{%k7} # AVX512IFMA + AVX512VL + vgatherpf0dpd 23(%ebp,%ymm7,8){%k1} # AVX512PF + vpermb %zmm4, %zmm5, %zmm6{%k7} # AVX512VBMI + vpermb %xmm4, %xmm5, %xmm6{%k7} # AVX512VBMI + AVX512VL + vpermb %ymm4, %ymm5, %ymm6{%k7} # AVX512VBMI + AVX512VL + + .arch .noavx512pf + vpabsb %zmm5, %zmm6{%k7} # AVX512BW + vpabsb %xmm5, %xmm6{%k7} # AVX512BW + AVX512VL + vpabsb %ymm5, %ymm6{%k7} # AVX512BW + AVX512VL + vpconflictd %zmm5, %zmm6 # AVX412CD + vpconflictd %xmm5, %xmm6 # AVX412CD + AVX512VL + vpconflictd %ymm5, %ymm6 # AVX412CD + AVX512VL + vcvtpd2qq (%ecx), %zmm6{%k7} # AVX512DQ + vcvtpd2qq (%ecx), %xmm6{%k7} # AVX512DQ + AVX512VL + vcvtpd2qq (%ecx), %ymm6{%k7} # AVX512DQ + AVX512VL + vexp2ps %zmm5, %zmm6{%k7} # AVX512ER + vaddpd %zmm4, %zmm5, %zmm6{%k7} # AVX512F + vaddpd %xmm4, %xmm5, %xmm6{%k7} # AVX512F + AVX512VL + vaddpd %ymm4, %ymm5, %ymm6{%k7} # AVX512F + AVX512VL + vpmadd52luq %zmm4, %zmm5, %zmm6{%k7} # AVX512IFMA + vpmadd52luq %xmm4, %xmm5, %xmm6{%k7} # AVX512IFMA + AVX512VL + vpmadd52luq %ymm4, %ymm5, %ymm6{%k7} # AVX512IFMA + AVX512VL + vgatherpf0dpd 23(%ebp,%ymm7,8){%k1} # AVX512PF + vpermb %zmm4, %zmm5, %zmm6{%k7} # AVX512VBMI + vpermb %xmm4, %xmm5, %xmm6{%k7} # AVX512VBMI + AVX512VL + vpermb %ymm4, %ymm5, %ymm6{%k7} # AVX512VBMI + AVX512VL + + .arch .noavx512vbmi + vpabsb %zmm5, %zmm6{%k7} # AVX512BW + vpabsb %xmm5, %xmm6{%k7} # AVX512BW + AVX512VL + vpabsb %ymm5, %ymm6{%k7} # AVX512BW + AVX512VL + vpconflictd %zmm5, %zmm6 # AVX412CD + vpconflictd %xmm5, %xmm6 # AVX412CD + AVX512VL + vpconflictd %ymm5, %ymm6 # AVX412CD + AVX512VL + vcvtpd2qq (%ecx), %zmm6{%k7} # AVX512DQ + vcvtpd2qq (%ecx), %xmm6{%k7} # AVX512DQ + AVX512VL + vcvtpd2qq (%ecx), %ymm6{%k7} # AVX512DQ + AVX512VL + vexp2ps %zmm5, %zmm6{%k7} # AVX512ER + vaddpd %zmm4, %zmm5, %zmm6{%k7} # AVX512F + vaddpd %xmm4, %xmm5, %xmm6{%k7} # AVX512F + AVX512VL + vaddpd %ymm4, %ymm5, %ymm6{%k7} # AVX512F + AVX512VL + vpmadd52luq %zmm4, %zmm5, %zmm6{%k7} # AVX512IFMA + vpmadd52luq %xmm4, %xmm5, %xmm6{%k7} # AVX512IFMA + AVX512VL + vpmadd52luq %ymm4, %ymm5, %ymm6{%k7} # AVX512IFMA + AVX512VL + vgatherpf0dpd 23(%ebp,%ymm7,8){%k1} # AVX512PF + vpermb %zmm4, %zmm5, %zmm6{%k7} # AVX512VBMI + vpermb %xmm4, %xmm5, %xmm6{%k7} # AVX512VBMI + AVX512VL + vpermb %ymm4, %ymm5, %ymm6{%k7} # AVX512VBMI + AVX512VL + + .arch .noavx512f + vpabsb %zmm5, %zmm6{%k7} # AVX512BW + vpabsb %xmm5, %xmm6{%k7} # AVX512BW + AVX512VL + vpabsb %ymm5, %ymm6{%k7} # AVX512BW + AVX512VL + vpconflictd %zmm5, %zmm6 # AVX412CD + vpconflictd %xmm5, %xmm6 # AVX412CD + AVX512VL + vpconflictd %ymm5, %ymm6 # AVX412CD + AVX512VL + vcvtpd2qq (%ecx), %zmm6{%k7} # AVX512DQ + vcvtpd2qq (%ecx), %xmm6{%k7} # AVX512DQ + AVX512VL + vcvtpd2qq (%ecx), %ymm6{%k7} # AVX512DQ + AVX512VL + vexp2ps %zmm5, %zmm6{%k7} # AVX512ER + vaddpd %zmm4, %zmm5, %zmm6{%k7} # AVX512F + vaddpd %xmm4, %xmm5, %xmm6{%k7} # AVX512F + AVX512VL + vaddpd %ymm4, %ymm5, %ymm6{%k7} # AVX512F + AVX512VL + vpmadd52luq %zmm4, %zmm5, %zmm6{%k7} # AVX512IFMA + vpmadd52luq %xmm4, %xmm5, %xmm6{%k7} # AVX512IFMA + AVX512VL + vpmadd52luq %ymm4, %ymm5, %ymm6{%k7} # AVX512IFMA + AVX512VL + vgatherpf0dpd 23(%ebp,%ymm7,8){%k1} # AVX512PF + vpermb %zmm4, %zmm5, %zmm6{%k7} # AVX512VBMI + vpermb %xmm4, %xmm5, %xmm6{%k7} # AVX512VBMI + AVX512VL + vpermb %ymm4, %ymm5, %ymm6{%k7} # AVX512VBMI + AVX512VL + + vpabsb %xmm5, %xmm6 + vpabsb %ymm5, %ymm6 + vaddpd %xmm4, %xmm5, %xmm6 + vaddpd %ymm4, %ymm5, %ymm6 + pabsb %xmm5, %xmm6 + addpd %xmm4, %xmm6 + + .p2align 4 diff --git a/gas/testsuite/gas/i386/noavx512-2.l b/gas/testsuite/gas/i386/noavx512-2.l new file mode 100644 index 0000000..08febef --- /dev/null +++ b/gas/testsuite/gas/i386/noavx512-2.l @@ -0,0 +1,105 @@ +.*: Assembler messages: +.*:26: Error: .*unsupported masking.* +.*:27: Error: .*unsupported masking.* +.*:29: Error: .*unsupported instruction.* +.*:30: Error: .*unsupported instruction.* +.*:32: Error: .*unsupported instruction.* +.*:33: Error: .*unsupported instruction.* +.*:36: Error: .*unsupported masking.* +.*:37: Error: .*unsupported masking.* +.*:39: Error: .*unsupported instruction.* +.*:40: Error: .*unsupported instruction.* +.*:43: Error: .*unsupported instruction.* +.*:44: Error: .*unsupported instruction.* +GAS LISTING .* +#... +[ ]*1[ ]+\# Test \.arch \.noavx512vl +[ ]*2[ ]+\.text +[ ]*3[ ]+\?\?\?\? 62F27D4F vpabsb %zmm5, %zmm6\{%k7\} \# AVX512BW +[ ]*3[ ]+1CF5 +[ ]*4[ ]+\?\?\?\? 62F27D0F vpabsb %xmm5, %xmm6\{%k7\} \# AVX512BW \+ AVX512VL +[ ]*4[ ]+1CF5 +[ ]*5[ ]+\?\?\?\? 62F27D2F vpabsb %ymm5, %ymm6\{%k7\} \# AVX512BW \+ AVX512VL +[ ]*5[ ]+1CF5 +[ ]*6[ ]+\?\?\?\? 62F27D48 vpconflictd %zmm5, %zmm6 \# AVX412CD +[ ]*6[ ]+C4F5 +[ ]*7[ ]+\?\?\?\? 62F27D08 vpconflictd %xmm5, %xmm6 \# AVX412CD \+ AVX512VL +[ ]*7[ ]+C4F5 +[ ]*8[ ]+\?\?\?\? 62F27D28 vpconflictd %ymm5, %ymm6 \# AVX412CD \+ AVX512VL +[ ]*8[ ]+C4F5 +[ ]*9[ ]+\?\?\?\? 62F1FD4F vcvtpd2qq \(%ecx\), %zmm6\{%k7\} \# AVX512DQ +[ ]*9[ ]+7B31 +[ ]*10[ ]+\?\?\?\? 62F1FD0F vcvtpd2qq \(%ecx\), %xmm6\{%k7\} \# AVX512DQ \+ AVX512VL +[ ]*10[ ]+7B31 +[ ]*11[ ]+\?\?\?\? 62F1FD2F vcvtpd2qq \(%ecx\), %ymm6\{%k7\} \# AVX512DQ \+ AVX512VL +[ ]*11[ ]+7B31 +[ ]*12[ ]+\?\?\?\? 62F27D4F vexp2ps %zmm5, %zmm6\{%k7\} \# AVX512ER +[ ]*12[ ]+C8F5 +[ ]*13[ ]+\?\?\?\? 62F1D54F vaddpd %zmm4, %zmm5, %zmm6\{%k7\} \# AVX512F +[ ]*13[ ]+58F4 +[ ]*14[ ]+\?\?\?\? 62F1D50F vaddpd %xmm4, %xmm5, %xmm6\{%k7\} \# AVX512F \+ AVX512VL +[ ]*14[ ]+58F4 +[ ]*15[ ]+\?\?\?\? 62F1D52F vaddpd %ymm4, %ymm5, %ymm6\{%k7\} \# AVX512F \+ AVX512VL +[ ]*15[ ]+58F4 +[ ]*16[ ]+\?\?\?\? 62F2D54F vpmadd52luq %zmm4, %zmm5, %zmm6\{%k7\} \# AVX512IFMA +[ ]*16[ ]+B4F4 +[ ]*17[ ]+\?\?\?\? 62F2D50F vpmadd52luq %xmm4, %xmm5, %xmm6\{%k7\} \# AVX512IFMA \+ AVX512VL +[ ]*17[ ]+B4F4 +[ ]*18[ ]+\?\?\?\? 62F2D52F vpmadd52luq %ymm4, %ymm5, %ymm6\{%k7\} \# AVX512IFMA \+ AVX512VL +[ ]*18[ ]+B4F4 +[ ]*19[ ]+\?\?\?\? 62F2FD49 vgatherpf0dpd 23\(%ebp,%ymm7,8\)\{%k1\} \# AVX512PF +[ ]*19[ ]+C68CFD17 +[ ]*19[ ]+000000 +[ ]*20[ ]+\?\?\?\? 62F2554F vpermb %zmm4, %zmm5, %zmm6\{%k7\} \# AVX512VBMI +[ ]*20[ ]+8DF4 +[ ]*21[ ]+\?\?\?\? 62F2550F vpermb %xmm4, %xmm5, %xmm6\{%k7\} \# AVX512VBMI \+ AVX512VL +[ ]*21[ ]+8DF4 +[ ]*22[ ]+\?\?\?\? 62F2552F vpermb %ymm4, %ymm5, %ymm6\{%k7\} \# AVX512VBMI \+ AVX512VL +[ ]*22[ ]+8DF4 +[ ]*23[ ]+ +[ ]*24[ ]+\.arch \.noavx512vl +[ ]*25[ ]+\?\?\?\? 62F27D4F vpabsb %zmm5, %zmm6\{%k7\} \# AVX512BW +[ ]*25[ ]+1CF5 +[ ]*26[ ]+vpabsb %xmm5, %xmm6\{%k7\} \# AVX512BW \+ AVX512VL +[ ]*27[ ]+vpabsb %ymm5, %ymm6\{%k7\} \# AVX512BW \+ AVX512VL +[ ]*28[ ]+\?\?\?\? 62F27D48 vpconflictd %zmm5, %zmm6 \# AVX412CD +[ ]*28[ ]+C4F5 +[ ]*29[ ]+vpconflictd %xmm5, %xmm6 \# AVX412CD \+ AVX512VL +[ ]*30[ ]+vpconflictd %ymm5, %ymm6 \# AVX412CD \+ AVX512VL +[ ]*31[ ]+\?\?\?\? 62F1FD4F vcvtpd2qq \(%ecx\), %zmm6\{%k7\} \# AVX512DQ +[ ]*31[ ]+7B31 +[ ]*32[ ]+vcvtpd2qq \(%ecx\), %xmm6\{%k7\} \# AVX512DQ \+ AVX512VL +[ ]*33[ ]+vcvtpd2qq \(%ecx\), %ymm6\{%k7\} \# AVX512DQ \+ AVX512VL +\fGAS LISTING .* + + +[ ]*34[ ]+\?\?\?\? 62F27D4F vexp2ps %zmm5, %zmm6\{%k7\} \# AVX512ER +[ ]*34[ ]+C8F5 +[ ]*35[ ]+\?\?\?\? 62F1D54F vaddpd %zmm4, %zmm5, %zmm6\{%k7\} \# AVX512F +[ ]*35[ ]+58F4 +[ ]*36[ ]+vaddpd %xmm4, %xmm5, %xmm6\{%k7\} \# AVX512F \+ AVX512VL +[ ]*37[ ]+vaddpd %ymm4, %ymm5, %ymm6\{%k7\} \# AVX512F \+ AVX512VL +[ ]*38[ ]+\?\?\?\? 62F2D54F vpmadd52luq %zmm4, %zmm5, %zmm6\{%k7\} \# AVX512IFMA +[ ]*38[ ]+B4F4 +[ ]*39[ ]+vpmadd52luq %xmm4, %xmm5, %xmm6\{%k7\} \# AVX512IFMA \+ AVX512VL +[ ]*40[ ]+vpmadd52luq %ymm4, %ymm5, %ymm6\{%k7\} \# AVX512IFMA \+ AVX512VL +[ ]*41[ ]+\?\?\?\? 62F2FD49 vgatherpf0dpd 23\(%ebp,%ymm7,8\)\{%k1\} \# AVX512PF +[ ]*41[ ]+C68CFD17 +[ ]*41[ ]+000000 +[ ]*42[ ]+\?\?\?\? 62F2554F vpermb %zmm4, %zmm5, %zmm6\{%k7\} \# AVX512VBMI +[ ]*42[ ]+8DF4 +[ ]*43[ ]+vpermb %xmm4, %xmm5, %xmm6\{%k7\} \# AVX512VBMI \+ AVX512VL +[ ]*44[ ]+vpermb %ymm4, %ymm5, %ymm6\{%k7\} \# AVX512VBMI \+ AVX512VL +[ ]*45[ ]+ +[ ]*46[ ]+\?\?\?\? C4E2791C vpabsb %xmm5, %xmm6 +[ ]*46[ ]+F5 +[ ]*47[ ]+\?\?\?\? C4E27D1C vpabsb %ymm5, %ymm6 +[ ]*47[ ]+F5 +[ ]*48[ ]+\?\?\?\? C5D158F4 vaddpd %xmm4, %xmm5, %xmm6 +[ ]*49[ ]+\?\?\?\? C5D558F4 vaddpd %ymm4, %ymm5, %ymm6 +[ ]*50[ ]+\?\?\?\? 660F381C pabsb %xmm5, %xmm6 +[ ]*50[ ]+F5 +[ ]*51[ ]+\?\?\?\? 660F58F4 addpd %xmm4, %xmm6 +[ ]*52[ ]+ +[ ]*53[ ]+\?\?\?\? 0F1F00 \.p2align 4 +#pass diff --git a/gas/testsuite/gas/i386/noavx512-2.s b/gas/testsuite/gas/i386/noavx512-2.s new file mode 100644 index 0000000..b9ef95c --- /dev/null +++ b/gas/testsuite/gas/i386/noavx512-2.s @@ -0,0 +1,53 @@ +# Test .arch .noavx512vl + .text + vpabsb %zmm5, %zmm6{%k7} # AVX512BW + vpabsb %xmm5, %xmm6{%k7} # AVX512BW + AVX512VL + vpabsb %ymm5, %ymm6{%k7} # AVX512BW + AVX512VL + vpconflictd %zmm5, %zmm6 # AVX412CD + vpconflictd %xmm5, %xmm6 # AVX412CD + AVX512VL + vpconflictd %ymm5, %ymm6 # AVX412CD + AVX512VL + vcvtpd2qq (%ecx), %zmm6{%k7} # AVX512DQ + vcvtpd2qq (%ecx), %xmm6{%k7} # AVX512DQ + AVX512VL + vcvtpd2qq (%ecx), %ymm6{%k7} # AVX512DQ + AVX512VL + vexp2ps %zmm5, %zmm6{%k7} # AVX512ER + vaddpd %zmm4, %zmm5, %zmm6{%k7} # AVX512F + vaddpd %xmm4, %xmm5, %xmm6{%k7} # AVX512F + AVX512VL + vaddpd %ymm4, %ymm5, %ymm6{%k7} # AVX512F + AVX512VL + vpmadd52luq %zmm4, %zmm5, %zmm6{%k7} # AVX512IFMA + vpmadd52luq %xmm4, %xmm5, %xmm6{%k7} # AVX512IFMA + AVX512VL + vpmadd52luq %ymm4, %ymm5, %ymm6{%k7} # AVX512IFMA + AVX512VL + vgatherpf0dpd 23(%ebp,%ymm7,8){%k1} # AVX512PF + vpermb %zmm4, %zmm5, %zmm6{%k7} # AVX512VBMI + vpermb %xmm4, %xmm5, %xmm6{%k7} # AVX512VBMI + AVX512VL + vpermb %ymm4, %ymm5, %ymm6{%k7} # AVX512VBMI + AVX512VL + + .arch .noavx512vl + vpabsb %zmm5, %zmm6{%k7} # AVX512BW + vpabsb %xmm5, %xmm6{%k7} # AVX512BW + AVX512VL + vpabsb %ymm5, %ymm6{%k7} # AVX512BW + AVX512VL + vpconflictd %zmm5, %zmm6 # AVX412CD + vpconflictd %xmm5, %xmm6 # AVX412CD + AVX512VL + vpconflictd %ymm5, %ymm6 # AVX412CD + AVX512VL + vcvtpd2qq (%ecx), %zmm6{%k7} # AVX512DQ + vcvtpd2qq (%ecx), %xmm6{%k7} # AVX512DQ + AVX512VL + vcvtpd2qq (%ecx), %ymm6{%k7} # AVX512DQ + AVX512VL + vexp2ps %zmm5, %zmm6{%k7} # AVX512ER + vaddpd %zmm4, %zmm5, %zmm6{%k7} # AVX512F + vaddpd %xmm4, %xmm5, %xmm6{%k7} # AVX512F + AVX512VL + vaddpd %ymm4, %ymm5, %ymm6{%k7} # AVX512F + AVX512VL + vpmadd52luq %zmm4, %zmm5, %zmm6{%k7} # AVX512IFMA + vpmadd52luq %xmm4, %xmm5, %xmm6{%k7} # AVX512IFMA + AVX512VL + vpmadd52luq %ymm4, %ymm5, %ymm6{%k7} # AVX512IFMA + AVX512VL + vgatherpf0dpd 23(%ebp,%ymm7,8){%k1} # AVX512PF + vpermb %zmm4, %zmm5, %zmm6{%k7} # AVX512VBMI + vpermb %xmm4, %xmm5, %xmm6{%k7} # AVX512VBMI + AVX512VL + vpermb %ymm4, %ymm5, %ymm6{%k7} # AVX512VBMI + AVX512VL + + vpabsb %xmm5, %xmm6 + vpabsb %ymm5, %ymm6 + vaddpd %xmm4, %xmm5, %xmm6 + vaddpd %ymm4, %ymm5, %ymm6 + pabsb %xmm5, %xmm6 + addpd %xmm4, %xmm6 + + .p2align 4 diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index f1e8142..6ebad47 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -285,6 +285,24 @@ static initializer cpu_flag_init[] = "CPU_ANY_AVX2_FLAGS|CpuF16C|CpuFMA|CpuFMA4|CpuXOP|CpuAVX" }, { "CPU_ANY_AVX2_FLAGS", "CpuAVX2" }, + { "CPU_ANY_AVX512F_FLAGS", + "CpuVREX|CpuRegZMM|CpuRegMask|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF|CpuAVX512DQ|CpuAVX512BW|CpuAVX512VL|CpuAVX512IFMA|CpuAVX512VBMI|CpuAVX512F" }, + { "CPU_ANY_AVX512CD_FLAGS", + "CpuAVX512CD" }, + { "CPU_ANY_AVX512ER_FLAGS", + "CpuAVX512ER" }, + { "CPU_ANY_AVX512PF_FLAGS", + "CpuAVX512PF" }, + { "CPU_ANY_AVX512DQ_FLAGS", + "CpuAVX512DQ" }, + { "CPU_ANY_AVX512BW_FLAGS", + "CpuAVX512BW" }, + { "CPU_ANY_AVX512VL_FLAGS", + "CpuAVX512VL" }, + { "CPU_ANY_AVX512IFMA_FLAGS", + "CpuAVX512IFMA" }, + { "CPU_ANY_AVX512VBMI_FLAGS", + "CpuAVX512VBMI" }, }; static initializer operand_type_init[] = diff --git a/opcodes/i386-init.h b/opcodes/i386-init.h index e522d61..10bc4f0 100644 --- a/opcodes/i386-init.h +++ b/opcodes/i386-init.h @@ -858,6 +858,69 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } +#define CPU_ANY_AVX512F_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, \ + 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0 } } + +#define CPU_ANY_AVX512CD_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_ANY_AVX512ER_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_ANY_AVX512PF_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_ANY_AVX512DQ_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_ANY_AVX512BW_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_ANY_AVX512VL_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_ANY_AVX512IFMA_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_ANY_AVX512VBMI_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + #define OPERAND_TYPE_NONE \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ -- 2.5.5 ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH] Allow setting CpuVRex bit in .arch directive 2016-05-24 19:02 ` H.J. Lu 2016-05-24 19:07 ` Jakub Jelinek @ 2016-05-25 23:22 ` H.J. Lu 2016-05-26 0:57 ` Alan Modra 1 sibling, 1 reply; 18+ messages in thread From: H.J. Lu @ 2016-05-25 23:22 UTC (permalink / raw) To: Jakub Jelinek; +Cc: Binutils, Uros Bizjak, Kirill Yukhin [-- Attachment #1: Type: text/plain, Size: 3000 bytes --] On Tue, May 24, 2016 at 12:02 PM, H.J. Lu <hjl.tools@gmail.com> wrote: > On Tue, May 24, 2016 at 10:49 AM, Jakub Jelinek <jakub@redhat.com> wrote: >>> Since vinsertf64x2 is an CpuAVX512VL instruction, I don't see >>> why it shouldn't assemble. >> >> Is it? I believe only vinsertf32x4 is, vinsertf64x2 is >> CpuAVX512VL & CpuAVX512DQ: >> >> EVEX.NDS.256.66.0F3A.W0 18 /r ib T4 V/V AVX512VL Insert 128 bits of packed single-precision floating- >> VINSERTF32X4 ymm1 {k1}{z}, ymm2, AVX512F point values from xmm3/m128 and the remaining >> xmm3/m128, imm8 values from ymm2 into ymm1 under writemask k1. >> >> EVEX.NDS.512.66.0F3A.W0 18 /r ib T4 V/V AVX512F Insert 128 bits of packed single-precision floating- >> VINSERTF32X4 zmm1 {k1}{z}, zmm2, point values from xmm3/m128 and the remaining >> xmm3/m128, imm8 values from zmm2 into zmm1 under writemask k1. >> >> EVEX.NDS.256.66.0F3A.W1 18 /r ib T2 V/V AVX512VL Insert 128 bits of packed double-precision floating- >> VINSERTF64X2 ymm1 {k1}{z}, ymm2, AVX512DQ point values from xmm3/m128 and the remaining >> xmm3/m128, imm8 values from ymm2 into ymm1 under writemask k1. >> >> EVEX.NDS.512.66.0F3A.W1 18 /r ib T2 V/V AVX512DQ Insert 128 bits of packed double-precision floating- >> VINSERTF64X2 zmm1 {k1}{z}, zmm2, point values from xmm3/m128 and the remaining >> xmm3/m128, imm8 values from zmm2 into zmm1 under writemask k1. >> >> vinsertf64x2, 4, 0x6618, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM } >> >> At least in 319433-024.pdf I see in 5.1.5: >> >> The fourth column holds abbreviated CPUID feature flags (e.g. appropriate >> bits in CPUID.1:ECX, CPUID.1:EDX for SSE/SSE2/SSE3/SSSE3/SSE4.1/SSE4.2/AVX/F16C support; bits in >> CPUID.(EAX=07H,ECX=0):BCX for AVX2/AVX512F etc) that indicate processor support for the instruction. If >> the corresponding flag is ‘0’, the instruction will #UD. >> >> Therefore, my understanding is that you need all the mentioned flags enabled >> or it will #UD. Does binutils treat CpuAVX512DQ|CpuAVX512VL instead >> as the insn being enabled in either .arch .avx512vl, or .arch .avx512dq >> alone, rather than only in .arch .avx512vl; .arch .avx512dq ? >> > > I opened: > > https://sourceware.org/bugzilla/show_bug.cgi?id=20140 > This is what I checked in. -- H.J. [-- Attachment #2: 0001-Require-another-match-for-AVX512VL.patch --] [-- Type: text/x-patch, Size: 13324 bytes --] From 8ab4e8bfc05d8d7d92e62a439d20190ea1814b5c Mon Sep 17 00:00:00 2001 From: "H.J. Lu" <hjl.tools@gmail.com> Date: Wed, 25 May 2016 14:59:05 -0700 Subject: [PATCH] Require another match for AVX512VL The AVX512VL bit alone isn't sufficient to select a 128-bit or 256-bit AVX512 instruction. We must match another AVX512 bit. PR gas/20140 * config/tc-i386.c (cpu_flags_match): Require another match for AVX512VL. * testsuite/gas/i386/i386.exp: Run avx512vl-1, avx512vl-2, x86-64-avx512vl-1 and x86-64-avx512vl-2. * testsuite/gas/i386/avx512vl-1.l: New file. * testsuite/gas/i386/avx512vl-1.s: Likewise. * testsuite/gas/i386/avx512vl-2.l: Likewise. * testsuite/gas/i386/avx512vl-2.s: Likewise. * testsuite/gas/i386/x86-64-avx512vl-1.l: Likewise. * testsuite/gas/i386/x86-64-avx512vl-1.s: Likewise. * testsuite/gas/i386/x86-64-avx512vl-2.l: Likewise. * testsuite/gas/i386/x86-64-avx512vl-2.s: Likewise. --- gas/ChangeLog | 16 ++++++++++++ gas/config/tc-i386.c | 15 ++++++++++++ gas/testsuite/gas/i386/avx512vl-1.l | 39 ++++++++++++++++++++++++++++++ gas/testsuite/gas/i386/avx512vl-1.s | 24 ++++++++++++++++++ gas/testsuite/gas/i386/avx512vl-2.l | 27 +++++++++++++++++++++ gas/testsuite/gas/i386/avx512vl-2.s | 15 ++++++++++++ gas/testsuite/gas/i386/i386.exp | 4 +++ gas/testsuite/gas/i386/x86-64-avx512vl-1.l | 39 ++++++++++++++++++++++++++++++ gas/testsuite/gas/i386/x86-64-avx512vl-1.s | 24 ++++++++++++++++++ gas/testsuite/gas/i386/x86-64-avx512vl-2.l | 27 +++++++++++++++++++++ gas/testsuite/gas/i386/x86-64-avx512vl-2.s | 15 ++++++++++++ 11 files changed, 245 insertions(+) create mode 100644 gas/testsuite/gas/i386/avx512vl-1.l create mode 100644 gas/testsuite/gas/i386/avx512vl-1.s create mode 100644 gas/testsuite/gas/i386/avx512vl-2.l create mode 100644 gas/testsuite/gas/i386/avx512vl-2.s create mode 100644 gas/testsuite/gas/i386/x86-64-avx512vl-1.l create mode 100644 gas/testsuite/gas/i386/x86-64-avx512vl-1.s create mode 100644 gas/testsuite/gas/i386/x86-64-avx512vl-2.l create mode 100644 gas/testsuite/gas/i386/x86-64-avx512vl-2.s diff --git a/gas/ChangeLog b/gas/ChangeLog index 2d23b43..da0cdc0 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,5 +1,21 @@ 2016-05-25 H.J. Lu <hongjiu.lu@intel.com> + PR gas/20140 + * config/tc-i386.c (cpu_flags_match): Require another match + for AVX512VL. + * testsuite/gas/i386/i386.exp: Run avx512vl-1, avx512vl-2, + x86-64-avx512vl-1 and x86-64-avx512vl-2. + * testsuite/gas/i386/avx512vl-1.l: New file. + * testsuite/gas/i386/avx512vl-1.s: Likewise. + * testsuite/gas/i386/avx512vl-2.l: Likewise. + * testsuite/gas/i386/avx512vl-2.s: Likewise. + * testsuite/gas/i386/x86-64-avx512vl-1.l: Likewise. + * testsuite/gas/i386/x86-64-avx512vl-1.s: Likewise. + * testsuite/gas/i386/x86-64-avx512vl-2.l: Likewise. + * testsuite/gas/i386/x86-64-avx512vl-2.s: Likewise. + +2016-05-25 H.J. Lu <hongjiu.lu@intel.com> + PR gas/20141 * testsuite/gas/i386/i386.exp: Run x86-64-pr20141. * testsuite/gas/i386/x86-64-pr20141.d: New file. diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 13041ea..af94f72 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -1564,6 +1564,21 @@ cpu_flags_match (const insn_template *t) else match |= CPU_FLAGS_ARCH_MATCH; } + else if (x.bitfield.cpuavx512vl) + { + /* Match AVX512VL. */ + if (cpu.bitfield.cpuavx512vl) + { + /* Need another match. */ + cpu.bitfield.cpuavx512vl = 0; + if (!cpu_flags_all_zero (&cpu)) + match |= CPU_FLAGS_32BIT_MATCH; + else + match |= CPU_FLAGS_ARCH_MATCH; + } + else + match |= CPU_FLAGS_ARCH_MATCH; + } else match |= CPU_FLAGS_32BIT_MATCH; } diff --git a/gas/testsuite/gas/i386/avx512vl-1.l b/gas/testsuite/gas/i386/avx512vl-1.l new file mode 100644 index 0000000..183c21d --- /dev/null +++ b/gas/testsuite/gas/i386/avx512vl-1.l @@ -0,0 +1,39 @@ +.*: Assembler messages: +.*:7: Error: .*bad register name.* +.*:8: Error: .*corei7\.avx.* +.*:9: Error: .*corei7\.avx.* +.*:10: Error: .*corei7\.avx.* +.*:15: Error: .*unsupported.* +.*:16: Error: .*unsupported.* +GAS LISTING .* +#... +[ ]*1[ ]+\.text +[ ]*2[ ]+\.arch corei7 +[ ]*3[ ]+_start: +[ ]*4[ ]+\.arch \.avx +[ ]*5[ ]+\?\?\?\? C5F9E711 vmovntdq %xmm2, \(%ecx\) +[ ]*6[ ]+\?\?\?\? C5FDE711 vmovntdq %ymm2, \(%ecx\) +[ ]*7[ ]+vmovntdq %zmm2, \(%ecx\) +[ ]*8[ ]+vpternlogq \$0xab, %xmm6, %xmm2, %xmm0 +[ ]*9[ ]+vpternlogq \$0xab, %ymm6, %ymm2, %ymm0 +[ ]*10[ ]+vpternlogq \$0xab, %zmm6, %zmm2, %zmm0 +[ ]*11[ ]+\.arch \.avx512f +[ ]*12[ ]+\?\?\?\? C5F9E701 vmovntdq %xmm0, \(%ecx\) +[ ]*13[ ]+\?\?\?\? C5FDE701 vmovntdq %ymm0, \(%ecx\) +[ ]*14[ ]+\?\?\?\? 62F17D48 vmovntdq %zmm0, \(%ecx\) +[ ]*14[ ]+E701 +[ ]*15[ ]+vpternlogq \$0xab, %xmm6, %xmm2, %xmm0 +[ ]*16[ ]+vpternlogq \$0xab, %ymm6, %ymm2, %ymm0 +[ ]*17[ ]+\?\?\?\? 62F3ED48 vpternlogq \$0xab, %zmm6, %zmm2, %zmm0 +[ ]*17[ ]+25C6AB +[ ]*18[ ]+\.arch \.avx512vl +[ ]*19[ ]+\?\?\?\? C5F9E701 vmovntdq %xmm0, \(%ecx\) +[ ]*20[ ]+\?\?\?\? C5FDE701 vmovntdq %ymm0, \(%ecx\) +[ ]*21[ ]+\?\?\?\? 62F17D48 vmovntdq %zmm0, \(%ecx\) +[ ]*21[ ]+E701 +[ ]*22[ ]+\?\?\?\? 62F3ED08 vpternlogq \$0xab, %xmm6, %xmm2, %xmm0 +[ ]*22[ ]+25C6AB +[ ]*23[ ]+\?\?\?\? 62F3ED28 vpternlogq \$0xab, %ymm6, %ymm2, %ymm0 +[ ]*23[ ]+25C6AB +[ ]*24[ ]+\?\?\?\? 62F3ED48 vpternlogq \$0xab, %zmm6, %zmm2, %zmm0 +[ ]*24[ ]+25C6AB diff --git a/gas/testsuite/gas/i386/avx512vl-1.s b/gas/testsuite/gas/i386/avx512vl-1.s new file mode 100644 index 0000000..62bae08 --- /dev/null +++ b/gas/testsuite/gas/i386/avx512vl-1.s @@ -0,0 +1,24 @@ + .text + .arch corei7 +_start: + .arch .avx + vmovntdq %xmm2, (%ecx) + vmovntdq %ymm2, (%ecx) + vmovntdq %zmm2, (%ecx) + vpternlogq $0xab, %xmm6, %xmm2, %xmm0 + vpternlogq $0xab, %ymm6, %ymm2, %ymm0 + vpternlogq $0xab, %zmm6, %zmm2, %zmm0 + .arch .avx512f + vmovntdq %xmm0, (%ecx) + vmovntdq %ymm0, (%ecx) + vmovntdq %zmm0, (%ecx) + vpternlogq $0xab, %xmm6, %xmm2, %xmm0 + vpternlogq $0xab, %ymm6, %ymm2, %ymm0 + vpternlogq $0xab, %zmm6, %zmm2, %zmm0 + .arch .avx512vl + vmovntdq %xmm0, (%ecx) + vmovntdq %ymm0, (%ecx) + vmovntdq %zmm0, (%ecx) + vpternlogq $0xab, %xmm6, %xmm2, %xmm0 + vpternlogq $0xab, %ymm6, %ymm2, %ymm0 + vpternlogq $0xab, %zmm6, %zmm2, %zmm0 diff --git a/gas/testsuite/gas/i386/avx512vl-2.l b/gas/testsuite/gas/i386/avx512vl-2.l new file mode 100644 index 0000000..2f1f7b3 --- /dev/null +++ b/gas/testsuite/gas/i386/avx512vl-2.l @@ -0,0 +1,27 @@ +.*: Assembler messages: +.*:5: Error: .*corei7.* +.*:6: Error: .*corei7.* +.*:7: Error: .*corei7.* +.*:9: Error: .*corei7\.avx\.avx512vl.* +.*:10: Error: .*corei7\.avx\.avx512vl.* +.*:11: Error: .*corei7\.avx\.avx512vl.* +GAS LISTING .* +#... +[ ]*1[ ]+\.text +[ ]*2[ ]+\.arch corei7 +[ ]*3[ ]+_start: +[ ]*4[ ]+\.arch \.avx +[ ]*5[ ]+vpconflictd %xmm0, %xmm5 +[ ]*6[ ]+vpconflictd %ymm0, %ymm5 +[ ]*7[ ]+vpconflictd %ymm0, %zmm5 +[ ]*8[ ]+\.arch \.avx512vl +[ ]*9[ ]+vpconflictd %xmm0, %xmm5 +[ ]*10[ ]+vpconflictd %ymm0, %ymm5 +[ ]*11[ ]+vpconflictd %zmm0, %zmm5 +[ ]*12[ ]+\.arch \.avx512cd +[ ]*13[ ]+\?\?\?\? 62F27D08 vpconflictd %xmm0, %xmm5 +[ ]*13[ ]+C4E8 +[ ]*14[ ]+\?\?\?\? 62F27D28 vpconflictd %ymm0, %ymm5 +[ ]*14[ ]+C4E8 +[ ]*15[ ]+\?\?\?\? 62F27D48 vpconflictd %zmm0, %zmm5 +[ ]*15[ ]+C4E8 diff --git a/gas/testsuite/gas/i386/avx512vl-2.s b/gas/testsuite/gas/i386/avx512vl-2.s new file mode 100644 index 0000000..6a24a1f --- /dev/null +++ b/gas/testsuite/gas/i386/avx512vl-2.s @@ -0,0 +1,15 @@ + .text + .arch corei7 +_start: + .arch .avx + vpconflictd %xmm0, %xmm5 + vpconflictd %ymm0, %ymm5 + vpconflictd %ymm0, %zmm5 + .arch .avx512vl + vpconflictd %xmm0, %xmm5 + vpconflictd %ymm0, %ymm5 + vpconflictd %zmm0, %zmm5 + .arch .avx512cd + vpconflictd %xmm0, %xmm5 + vpconflictd %ymm0, %ymm5 + vpconflictd %zmm0, %zmm5 diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index 1aca467..624674d 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -356,6 +356,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]] run_dump_test "ospke" run_dump_test "rdpid" run_dump_test "rdpid-intel" + run_list_test "avx512vl-1" "-al" + run_list_test "avx512vl-2" "-al" # These tests require support for 8 and 16 bit relocs, # so we only run them for ELF and COFF targets. @@ -754,6 +756,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t run_dump_test "x86-64-fence-as-lock-add-yes" run_dump_test "x86-64-fence-as-lock-add-no" run_dump_test "x86-64-pr20141" + run_list_test "x86-64-avx512vl-1" "-al" + run_list_test "x86-64-avx512vl-2" "-al" if { ![istarget "*-*-aix*"] && ![istarget "*-*-beos*"] diff --git a/gas/testsuite/gas/i386/x86-64-avx512vl-1.l b/gas/testsuite/gas/i386/x86-64-avx512vl-1.l new file mode 100644 index 0000000..c5982e7 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-avx512vl-1.l @@ -0,0 +1,39 @@ +.*: Assembler messages: +.*:7: Error: .*bad register name.* +.*:8: Error: .*corei7\.avx.* +.*:9: Error: .*corei7\.avx.* +.*:10: Error: .*corei7\.avx.* +.*:15: Error: .*unsupported.* +.*:16: Error: .*unsupported.* +GAS LISTING .* +#... +[ ]*1[ ]+\.text +[ ]*2[ ]+\.arch corei7 +[ ]*3[ ]+_start: +[ ]*4[ ]+\.arch \.avx +[ ]*5[ ]+\?\?\?\? C5F9E711 vmovntdq %xmm2, \(%rcx\) +[ ]*6[ ]+\?\?\?\? C5FDE711 vmovntdq %ymm2, \(%rcx\) +[ ]*7[ ]+vmovntdq %zmm2, \(%rcx\) +[ ]*8[ ]+vpternlogq \$0xab, %xmm16, %xmm2, %xmm0 +[ ]*9[ ]+vpternlogq \$0xab, %ymm16, %ymm2, %ymm0 +[ ]*10[ ]+vpternlogq \$0xab, %zmm16, %zmm2, %zmm0 +[ ]*11[ ]+\.arch \.avx512f +[ ]*12[ ]+\?\?\?\? C5F9E701 vmovntdq %xmm0, \(%rcx\) +[ ]*13[ ]+\?\?\?\? C5FDE701 vmovntdq %ymm0, \(%rcx\) +[ ]*14[ ]+\?\?\?\? 62F17D48 vmovntdq %zmm0, \(%rcx\) +[ ]*14[ ]+E701 +[ ]*15[ ]+vpternlogq \$0xab, %xmm16, %xmm2, %xmm0 +[ ]*16[ ]+vpternlogq \$0xab, %ymm16, %ymm2, %ymm0 +[ ]*17[ ]+\?\?\?\? 62B3ED48 vpternlogq \$0xab, %zmm16, %zmm2, %zmm0 +[ ]*17[ ]+25C0AB +[ ]*18[ ]+\.arch \.avx512vl +[ ]*19[ ]+\?\?\?\? C5F9E701 vmovntdq %xmm0, \(%rcx\) +[ ]*20[ ]+\?\?\?\? C5FDE701 vmovntdq %ymm0, \(%rcx\) +[ ]*21[ ]+\?\?\?\? 62F17D48 vmovntdq %zmm0, \(%rcx\) +[ ]*21[ ]+E701 +[ ]*22[ ]+\?\?\?\? 62B3ED08 vpternlogq \$0xab, %xmm16, %xmm2, %xmm0 +[ ]*22[ ]+25C0AB +[ ]*23[ ]+\?\?\?\? 62B3ED28 vpternlogq \$0xab, %ymm16, %ymm2, %ymm0 +[ ]*23[ ]+25C0AB +[ ]*24[ ]+\?\?\?\? 62B3ED48 vpternlogq \$0xab, %zmm16, %zmm2, %zmm0 +[ ]*24[ ]+25C0AB diff --git a/gas/testsuite/gas/i386/x86-64-avx512vl-1.s b/gas/testsuite/gas/i386/x86-64-avx512vl-1.s new file mode 100644 index 0000000..8a5f2f9 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-avx512vl-1.s @@ -0,0 +1,24 @@ + .text + .arch corei7 +_start: + .arch .avx + vmovntdq %xmm2, (%rcx) + vmovntdq %ymm2, (%rcx) + vmovntdq %zmm2, (%rcx) + vpternlogq $0xab, %xmm16, %xmm2, %xmm0 + vpternlogq $0xab, %ymm16, %ymm2, %ymm0 + vpternlogq $0xab, %zmm16, %zmm2, %zmm0 + .arch .avx512f + vmovntdq %xmm0, (%rcx) + vmovntdq %ymm0, (%rcx) + vmovntdq %zmm0, (%rcx) + vpternlogq $0xab, %xmm16, %xmm2, %xmm0 + vpternlogq $0xab, %ymm16, %ymm2, %ymm0 + vpternlogq $0xab, %zmm16, %zmm2, %zmm0 + .arch .avx512vl + vmovntdq %xmm0, (%rcx) + vmovntdq %ymm0, (%rcx) + vmovntdq %zmm0, (%rcx) + vpternlogq $0xab, %xmm16, %xmm2, %xmm0 + vpternlogq $0xab, %ymm16, %ymm2, %ymm0 + vpternlogq $0xab, %zmm16, %zmm2, %zmm0 diff --git a/gas/testsuite/gas/i386/x86-64-avx512vl-2.l b/gas/testsuite/gas/i386/x86-64-avx512vl-2.l new file mode 100644 index 0000000..10833f6 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-avx512vl-2.l @@ -0,0 +1,27 @@ +.*: Assembler messages: +.*:5: Error: .*corei7.* +.*:6: Error: .*corei7.* +.*:7: Error: .*corei7.* +.*:9: Error: .*corei7\.avx\.avx512vl.* +.*:10: Error: .*corei7\.avx\.avx512vl.* +.*:11: Error: .*corei7\.avx\.avx512vl.* +GAS LISTING .* +#... +[ ]*1[ ]+\.text +[ ]*2[ ]+\.arch corei7 +[ ]*3[ ]+_start: +[ ]*4[ ]+\.arch \.avx +[ ]*5[ ]+vpconflictd %xmm0, %xmm25 +[ ]*6[ ]+vpconflictd %ymm0, %ymm25 +[ ]*7[ ]+vpconflictd %ymm0, %zmm25 +[ ]*8[ ]+\.arch \.avx512vl +[ ]*9[ ]+vpconflictd %xmm0, %xmm25 +[ ]*10[ ]+vpconflictd %ymm0, %ymm25 +[ ]*11[ ]+vpconflictd %zmm0, %zmm25 +[ ]*12[ ]+\.arch \.avx512cd +[ ]*13[ ]+\?\?\?\? 62627D08 vpconflictd %xmm0, %xmm25 +[ ]*13[ ]+C4C8 +[ ]*14[ ]+\?\?\?\? 62627D28 vpconflictd %ymm0, %ymm25 +[ ]*14[ ]+C4C8 +[ ]*15[ ]+\?\?\?\? 62627D48 vpconflictd %zmm0, %zmm25 +[ ]*15[ ]+C4C8 diff --git a/gas/testsuite/gas/i386/x86-64-avx512vl-2.s b/gas/testsuite/gas/i386/x86-64-avx512vl-2.s new file mode 100644 index 0000000..2b64c70 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-avx512vl-2.s @@ -0,0 +1,15 @@ + .text + .arch corei7 +_start: + .arch .avx + vpconflictd %xmm0, %xmm25 + vpconflictd %ymm0, %ymm25 + vpconflictd %ymm0, %zmm25 + .arch .avx512vl + vpconflictd %xmm0, %xmm25 + vpconflictd %ymm0, %ymm25 + vpconflictd %zmm0, %zmm25 + .arch .avx512cd + vpconflictd %xmm0, %xmm25 + vpconflictd %ymm0, %ymm25 + vpconflictd %zmm0, %zmm25 -- 2.5.5 ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH] Allow setting CpuVRex bit in .arch directive 2016-05-25 23:22 ` H.J. Lu @ 2016-05-26 0:57 ` Alan Modra 0 siblings, 0 replies; 18+ messages in thread From: Alan Modra @ 2016-05-26 0:57 UTC (permalink / raw) To: H.J. Lu; +Cc: Jakub Jelinek, Binutils, Uros Bizjak, Kirill Yukhin i386-linuxaout +FAIL: i386 nommx-1 i386-linuxaout +FAIL: i386 nosse-1 i386-linuxaout +FAIL: i386 noavx-1 i386-linuxaout +FAIL: i386 avx512vl-2 i586-aout +FAIL: i386 nommx-1 i586-aout +FAIL: i386 nosse-1 i586-aout +FAIL: i386 noavx-1 i586-aout +FAIL: i386 avx512vl-2 i586-coff +FAIL: i386 nommx-1 i586-coff +FAIL: i386 nosse-1 i586-coff +FAIL: i386 noavx-1 i586-coff +FAIL: i386 avx512vl-2 i686-pe +FAIL: i386 nommx-1 i686-pe +FAIL: i386 nosse-1 i686-pe +FAIL: i386 noavx-1 i686-pe +FAIL: i386 avx512vl-2 x86_64-mingw32 +FAIL: i386 nommx-1 x86_64-mingw32 +FAIL: i386 nosse-1 x86_64-mingw32 +FAIL: i386 noavx-1 x86_64-mingw32 +FAIL: i386 avx512vl-2 x86_64-mingw32 +FAIL: i386 x86-64-avx512vl-2 -- Alan Modra Australia Development Lab, IBM ^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2016-05-29 15:04 UTC | newest] Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2016-05-21 16:54 [PATCH] Allow setting CpuVRex bit in .arch directive Jakub Jelinek 2016-05-21 17:06 ` Jakub Jelinek 2016-05-24 17:24 ` H.J. Lu 2016-05-24 17:49 ` Jakub Jelinek 2016-05-24 19:02 ` H.J. Lu 2016-05-24 19:07 ` Jakub Jelinek 2016-05-24 20:36 ` H.J. Lu 2016-05-25 16:35 ` H.J. Lu 2016-05-25 17:26 ` H.J. Lu 2016-05-25 17:54 ` H.J. Lu 2016-05-25 17:58 ` Jakub Jelinek 2016-05-25 18:26 ` H.J. Lu 2016-05-25 18:39 ` Jakub Jelinek 2016-05-25 19:12 ` H.J. Lu 2016-05-26 0:09 ` H.J. Lu 2016-05-29 15:04 ` H.J. Lu 2016-05-25 23:22 ` H.J. Lu 2016-05-26 0:57 ` Alan Modra
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