* [PATCH 0/6] x86: various MPX fixes
@ 2013-10-08 14:36 Jan Beulich
2013-10-08 14:41 ` [PATCH 2/6] x86/MPX: fix address size handling Jan Beulich
` (5 more replies)
0 siblings, 6 replies; 33+ messages in thread
From: Jan Beulich @ 2013-10-08 14:36 UTC (permalink / raw)
To: H.J. Lu; +Cc: kirill.yukhin, binutils
The first of these patches adjusts the testsuite such that invalid
things get checked to be invalid, and valid things get checked to
be valid. This will by itself introduce testsuite failures which get
addressed by the subsequent patches (the order of which doesn't
really matter).
1: testsuite adjustments
2: fix address size handling
3: suppress base/index swapping in Intel mode for bndmk, bndldx, and bndstx
4: bndmk, bndldx, and bndstx only allow a memory operand
5: fix operand size handling
6: bndmk, bndldx, and bndstx don't allow RIP-relative addressing
Jan
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 1/6] x86/MPX: testsuite adjustments
2013-10-08 14:36 [PATCH 0/6] x86: various MPX fixes Jan Beulich
2013-10-08 14:41 ` [PATCH 2/6] x86/MPX: fix address size handling Jan Beulich
@ 2013-10-08 14:41 ` Jan Beulich
2013-10-08 14:42 ` [PATCH 3/6] x86/MPX: suppress base/index swapping in Intel mode for bndmk, bndldx, and bndstx Jan Beulich
` (3 subsequent siblings)
5 siblings, 0 replies; 33+ messages in thread
From: Jan Beulich @ 2013-10-08 14:41 UTC (permalink / raw)
To: H.J. Lu; +Cc: kirill.yukhin, binutils
[-- Attachment #1: Type: text/plain, Size: 44592 bytes --]
This will by itself introduce testsuite failures which get addressed
by subsequent patches.
gas/testsuite/
2013-10-08 Jan Beulich <jbeulich@suse.com>
* gas/i386/mpx-inval-2.[sl]: New.
* gas/i386/i386.exp: Run new test.
* gas/i386/mpx.s: Remove invalid tests involving 16-bit register
operands to bndc[lnu].
* gas/i386/mpx.d: Adjust accordingly.
* gas/i386/x86-64-mpx.s: Remove invalid tests involving 16-bit
register operands to bndc[lnu].
* gas/i386/x86-64-mpx.d: Adjust accordingly.
* gas/i386/x86-64-mpx-inval-2.s: Add tests for invalid uses of RIP-
relative addressing, 16- and 32-bit register operands, as well as a
special case of Intel mode memory operands.
* gas/i386/x86-64-mpx-inval-2.l: Adjust accordingly and generalize.
--- 2013-10-07/gas/testsuite/gas/i386/i386.exp
+++ 2013-10-07/gas/testsuite/gas/i386/i386.exp
@@ -267,6 +267,7 @@ if [expr ([istarget "i*86-*-*"] || [ist
run_dump_test "smap"
run_dump_test "mpx"
run_list_test "mpx-inval-1" "-al"
+ run_list_test "mpx-inval-2" "-al"
run_dump_test "mpx-add-bnd-prefix"
run_dump_test "sha"
--- /dev/null
+++ 2013-10-07/gas/testsuite/gas/i386/mpx-inval-2.l
@@ -0,0 +1,145 @@
+.*: Assembler messages:
+.*:5: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:6: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:7: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:8: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:9: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:10: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:11: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:12: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:14: Error: operand type mismatch for `bndcl'
+.*:15: Error: operand type mismatch for `bndcn'
+.*:16: Error: operand type mismatch for `bndcu'
+.*:19: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:20: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:21: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:22: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:23: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:24: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:25: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:26: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:28: Error: operand type mismatch for `bndcl'
+.*:29: Error: operand type mismatch for `bndcn'
+.*:30: Error: operand type mismatch for `bndcu'
+.*:35: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:36: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:37: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:38: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:39: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:40: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:41: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:42: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:44: Error: operand type mismatch for `bndcl'
+.*:45: Error: operand type mismatch for `bndcn'
+.*:46: Error: operand type mismatch for `bndcu'
+.*:49: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:50: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:51: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:52: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:53: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:54: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:55: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:56: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:58: Error: operand type mismatch for `bndcl'
+.*:59: Error: operand type mismatch for `bndcn'
+.*:60: Error: operand type mismatch for `bndcu'
+GAS LISTING .*
+#...
+[ ]*[1-9][0-9]*[ ]+mpx32:
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndcl \(%bx,%si\), %bnd0
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndcn \(%bx,%di\), %bnd0
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndcu \(%bp,%si\), %bnd0
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndldx \(%bp,%di\), %bnd0
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndmk \(%bx\), %bnd0
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndmov \(%bp\), %bnd0
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndmov %bnd0, \(%si\)
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndstx %bnd0, \(%di\)
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndcl bnd0, \[bx\]
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndcn bnd0, \[bp\]
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndcu bnd0, \[si\]
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndldx bnd0, \[di\]
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndmk bnd0, \[bx\+si\]
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndmov bnd0, \[bx\+di\]
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndmov \[bp\+si\], bnd0
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndstx \[bp\+di\], bnd0
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+mpx16:
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndcl \(%bx,%si\), %bnd0
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndcn \(%bx,%di\), %bnd0
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndcu \(%bp,%si\), %bnd0
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndldx \(%bp,%di\), %bnd0
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndmk \(%bx\), %bnd0
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndmov \(%bp\), %bnd0
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndmov %bnd0, \(%si\)
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndstx %bnd0, \(%di\)
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndcl bnd0, \[bx\]
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndcn bnd0, \[bp\]
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndcu bnd0, \[si\]
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndldx bnd0, \[di\]
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndmk bnd0, \[bx\+si\]
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndmov bnd0, \[bx\+di\]
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndmov \[bp\+si\], bnd0
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndstx \[bp\+di\], bnd0
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
--- /dev/null
+++ 2013-10-07/gas/testsuite/gas/i386/mpx-inval-2.s
@@ -0,0 +1,60 @@
+# MPX instructions
+ .text
+ .code32
+mpx32:
+ bndcl (%bx,%si), %bnd0
+ bndcn (%bx,%di), %bnd0
+ bndcu (%bp,%si), %bnd0
+ bndldx (%bp,%di), %bnd0
+ bndmk (%bx), %bnd0
+ bndmov (%bp), %bnd0
+ bndmov %bnd0, (%si)
+ bndstx %bnd0, (%di)
+
+ bndcl %di, %bnd1
+ bndcn %si, %bnd2
+ bndcu %bp, %bnd3
+
+ .intel_syntax noprefix
+ bndcl bnd0, [bx]
+ bndcn bnd0, [bp]
+ bndcu bnd0, [si]
+ bndldx bnd0, [di]
+ bndmk bnd0, [bx+si]
+ bndmov bnd0, [bx+di]
+ bndmov [bp+si], bnd0
+ bndstx [bp+di], bnd0
+
+ bndcl bnd3, ax
+ bndcn bnd2, cx
+ bndcu bnd1, dx
+
+ .att_syntax prefix
+ .code16
+mpx16:
+ bndcl (%bx,%si), %bnd0
+ bndcn (%bx,%di), %bnd0
+ bndcu (%bp,%si), %bnd0
+ bndldx (%bp,%di), %bnd0
+ bndmk (%bx), %bnd0
+ bndmov (%bp), %bnd0
+ bndmov %bnd0, (%si)
+ bndstx %bnd0, (%di)
+
+ bndcl %di, %bnd1
+ bndcn %si, %bnd2
+ bndcu %bp, %bnd3
+
+ .intel_syntax noprefix
+ bndcl bnd0, [bx]
+ bndcn bnd0, [bp]
+ bndcu bnd0, [si]
+ bndldx bnd0, [di]
+ bndmk bnd0, [bx+si]
+ bndmov bnd0, [bx+di]
+ bndmov [bp+si], bnd0
+ bndstx [bp+di], bnd0
+
+ bndcl bnd3, ax
+ bndcn bnd2, cx
+ bndcu bnd1, dx
--- 2013-10-07/gas/testsuite/gas/i386/mpx.d
+++ 2013-10-07/gas/testsuite/gas/i386/mpx.d
@@ -6,7 +6,7 @@
Disassembly of section .text:
-0+ <foo-0x2c1>:
+0+ <foo-0x[0-9a-f]+>:
[ ]*[a-f0-9]+: f3 0f 1b 08 bndmk \(%eax\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1b 0d 99 03 00 00 bndmk 0x399,%bnd1
[ ]*[a-f0-9]+: f3 0f 1b 4a 03 bndmk 0x3\(%edx\),%bnd1
@@ -29,7 +29,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 0f 1a d0 bndmov %bnd0,%bnd2
[ ]*[a-f0-9]+: f3 0f 1a 09 bndcl \(%ecx\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1a c9 bndcl %ecx,%bnd1
-[ ]*[a-f0-9]+: f3 0f 1a c8 bndcl %eax,%bnd1
[ ]*[a-f0-9]+: f3 0f 1a 0d 99 03 00 00 bndcl 0x399,%bnd1
[ ]*[a-f0-9]+: f3 0f 1a 4a 03 bndcl 0x3\(%edx\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1a 0c 08 bndcl \(%eax,%ecx,1\),%bnd1
@@ -37,7 +36,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: f3 0f 1a 4c 01 03 bndcl 0x3\(%ecx,%eax,1\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1a 09 bndcu \(%ecx\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1a c9 bndcu %ecx,%bnd1
-[ ]*[a-f0-9]+: f2 0f 1a c8 bndcu %eax,%bnd1
[ ]*[a-f0-9]+: f2 0f 1a 0d 99 03 00 00 bndcu 0x399,%bnd1
[ ]*[a-f0-9]+: f2 0f 1a 4a 03 bndcu 0x3\(%edx\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1a 0c 08 bndcu \(%eax,%ecx,1\),%bnd1
@@ -45,7 +43,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: f2 0f 1a 4c 01 03 bndcu 0x3\(%ecx,%eax,1\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1b 09 bndcn \(%ecx\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1b c9 bndcn %ecx,%bnd1
-[ ]*[a-f0-9]+: f2 0f 1b c8 bndcn %eax,%bnd1
[ ]*[a-f0-9]+: f2 0f 1b 0d 99 03 00 00 bndcn 0x399,%bnd1
[ ]*[a-f0-9]+: f2 0f 1b 4a 03 bndcn 0x3\(%edx\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1b 0c 08 bndcn \(%eax,%ecx,1\),%bnd1
@@ -65,10 +62,10 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f 1a 93 34 12 00 00 bndldx 0x1234\(%ebx\),%bnd2
[ ]*[a-f0-9]+: 0f 1a 53 03 bndldx 0x3\(%ebx\),%bnd2
[ ]*[a-f0-9]+: 0f 1a 0a bndldx \(%edx\),%bnd1
-[ ]*[a-f0-9]+: f2 e8 6f 01 00 00 bnd call 2c1 <foo>
+[ ]*[a-f0-9]+: f2 e8 .. .. 00 00 bnd call [0-9a-f]+ <foo>
[ ]*[a-f0-9]+: f2 ff 10 bnd call \*\(%eax\)
-[ ]*[a-f0-9]+: f2 0f 84 65 01 00 00 bnd je 2c1 <foo>
-[ ]*[a-f0-9]+: f2 e9 5f 01 00 00 bnd jmp 2c1 <foo>
+[ ]*[a-f0-9]+: f2 0f 84 .. .. 00 00 bnd je [0-9a-f]+ <foo>
+[ ]*[a-f0-9]+: f2 e9 .. .. 00 00 bnd jmp [0-9a-f]+ <foo>
[ ]*[a-f0-9]+: f2 ff 21 bnd jmp \*\(%ecx\)
[ ]*[a-f0-9]+: f2 c3 bnd ret
[ ]*[a-f0-9]+: f3 0f 1b 08 bndmk \(%eax\),%bnd1
@@ -93,7 +90,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 0f 1a c8 bndmov %bnd0,%bnd1
[ ]*[a-f0-9]+: f3 0f 1a 08 bndcl \(%eax\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1a c9 bndcl %ecx,%bnd1
-[ ]*[a-f0-9]+: f3 0f 1a c8 bndcl %eax,%bnd1
[ ]*[a-f0-9]+: f3 0f 1a 0d 99 03 00 00 bndcl 0x399,%bnd1
[ ]*[a-f0-9]+: f3 0f 1a 49 03 bndcl 0x3\(%ecx\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1a 0c 08 bndcl \(%eax,%ecx,1\),%bnd1
@@ -101,7 +97,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: f3 0f 1a 4c 02 03 bndcl 0x3\(%edx,%eax,1\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1a 08 bndcu \(%eax\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1a c9 bndcu %ecx,%bnd1
-[ ]*[a-f0-9]+: f2 0f 1a c8 bndcu %eax,%bnd1
[ ]*[a-f0-9]+: f2 0f 1a 0d 99 03 00 00 bndcu 0x399,%bnd1
[ ]*[a-f0-9]+: f2 0f 1a 49 03 bndcu 0x3\(%ecx\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1a 0c 08 bndcu \(%eax,%ecx,1\),%bnd1
@@ -109,7 +104,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: f2 0f 1a 4c 02 03 bndcu 0x3\(%edx,%eax,1\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1b 08 bndcn \(%eax\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1b c9 bndcn %ecx,%bnd1
-[ ]*[a-f0-9]+: f2 0f 1b c8 bndcn %eax,%bnd1
[ ]*[a-f0-9]+: f2 0f 1b 0d 99 03 00 00 bndcn 0x399,%bnd1
[ ]*[a-f0-9]+: f2 0f 1b 49 03 bndcn 0x3\(%ecx\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1b 0c 08 bndcn \(%eax,%ecx,1\),%bnd1
@@ -127,13 +121,13 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f 1a 9a 99 03 00 00 bndldx 0x399\(%edx\),%bnd3
[ ]*[a-f0-9]+: 0f 1a 14 1d 03 00 00 00 bndldx 0x3\(,%ebx,1\),%bnd2
[ ]*[a-f0-9]+: 0f 1a 0a bndldx \(%edx\),%bnd1
-[ ]*[a-f0-9]+: f2 e8 0e 00 00 00 bnd call 2c1 <foo>
+[ ]*[a-f0-9]+: f2 e8 .. 00 00 00 bnd call [0-9a-f]+ <foo>
[ ]*[a-f0-9]+: f2 ff d0 bnd call \*%eax
-[ ]*[a-f0-9]+: f2 74 08 bnd je 2c1 <foo>
-[ ]*[a-f0-9]+: f2 eb 05 bnd jmp 2c1 <foo>
+[ ]*[a-f0-9]+: f2 74 .. bnd je [0-9a-f]+ <foo>
+[ ]*[a-f0-9]+: f2 eb .. bnd jmp [0-9a-f]+ <foo>
[ ]*[a-f0-9]+: f2 ff e1 bnd jmp \*%ecx
[ ]*[a-f0-9]+: f2 c3 bnd ret
-0+2c1 <foo>:
+[0-9a-f]+ <foo>:
[ ]*[a-f0-9]+: f2 c3 bnd ret
#pass
--- 2013-10-07/gas/testsuite/gas/i386/mpx.s
+++ 2013-10-07/gas/testsuite/gas/i386/mpx.s
@@ -30,7 +30,6 @@
### bndcl
bndcl (%ecx), %bnd1
bndcl %ecx, %bnd1
- bndcl %ax, %bnd1
bndcl (0x399), %bnd1
bndcl 0x3(%edx), %bnd1
bndcl (%eax,%ecx), %bnd1
@@ -40,7 +39,6 @@
### bndcu
bndcu (%ecx), %bnd1
bndcu %ecx, %bnd1
- bndcu %ax, %bnd1
bndcu (0x399), %bnd1
bndcu 0x3(%edx), %bnd1
bndcu (%eax,%ecx), %bnd1
@@ -50,7 +48,6 @@
### bndcn
bndcn (%ecx), %bnd1
bndcn %ecx, %bnd1
- bndcn %ax, %bnd1
bndcn (0x399), %bnd1
bndcn 0x3(%edx), %bnd1
bndcn (%eax,%ecx), %bnd1
@@ -111,7 +108,6 @@
### bndcl
bndcl bnd1, [eax]
bndcl bnd1, ecx
- bndcl bnd1, ax
bndcl bnd1, [0x399]
bndcl bnd1, [ecx+0x3]
bndcl bnd1, [eax+ecx]
@@ -121,7 +117,6 @@
### bndcu
bndcu bnd1, [eax]
bndcu bnd1, ecx
- bndcu bnd1, ax
bndcu bnd1, [0x399]
bndcu bnd1, [ecx+0x3]
bndcu bnd1, [eax+ecx]
@@ -131,7 +126,6 @@
### bndcn
bndcn bnd1, [eax]
bndcn bnd1, ecx
- bndcn bnd1, ax
bndcn bnd1, [0x399]
bndcn bnd1, [ecx+0x3]
bndcn bnd1, [eax+ecx]
--- 2013-10-07/gas/testsuite/gas/i386/x86-64-mpx-inval-2.l
+++ 2013-10-07/gas/testsuite/gas/i386/x86-64-mpx-inval-2.l
@@ -1,173 +1,213 @@
.*: Assembler messages:
-.*:6: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:7: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:10: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:11: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:13: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:14: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:17: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:18: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:21: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:22: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:25: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:26: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:29: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:30: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:33: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:34: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:37: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:38: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:41: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:42: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:44: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:45: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:48: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:49: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:52: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:53: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:56: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:57: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:60: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:61: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:64: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:65: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
+.*:6: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:7: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:8: Error: `\(%rip\)' cannot be used here
+.*:11: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:12: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:14: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:15: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:18: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:19: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:20: Warning: using `%rcx' instead of `%ecx' for `bndcl'
+.*:21: Error: operand type mismatch for `bndcl'
+.*:24: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:25: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:26: Warning: using `%rcx' instead of `%ecx' for `bndcu'
+.*:27: Error: operand type mismatch for `bndcu'
+.*:30: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:31: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:32: Warning: using `%rcx' instead of `%ecx' for `bndcn'
+.*:33: Error: operand type mismatch for `bndcn'
+.*:36: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:37: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:38: Warning: register scaling is being ignored here
+.*:39: Error: `base\(%rip\)' cannot be used here
+.*:42: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:43: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:44: Warning: register scaling is being ignored here
+.*:45: Error: `base\(%rip\)' cannot be used here
+.*:48: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:49: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:50: Error: `\[rip\]' cannot be used here
+.*:51: Error: `\[rax\+rsp\]' is not a valid base/index expression
+.*:54: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:55: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:57: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:58: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:61: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:62: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:63: Warning: using `rax' instead of `eax' for `bndcl'
+.*:64: Error: operand type mismatch for `bndcl'
+.*:67: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:68: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:69: Warning: using `rax' instead of `eax' for `bndcu'
+.*:70: Error: operand type mismatch for `bndcu'
+.*:73: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:74: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:75: Warning: using `rax' instead of `eax' for `bndcn'
+.*:76: Error: operand type mismatch for `bndcn'
+.*:79: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:80: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:81: Warning: register scaling is being ignored here
+.*:82: Error: `\[rip\+base\]' cannot be used here
+.*:83: Error: `\[rax\+rsp\]' is not a valid base/index expression
+.*:86: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:87: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:88: Warning: register scaling is being ignored here
+.*:89: Error: `\[rip\+base\]' cannot be used here
+.*:90: Error: `\[rax\+rsp\]' is not a valid base/index expression
GAS LISTING .*
-
-
-[ ]*1[ ]+\# MPX instructions
-[ ]*2[ ]+\.allow_index_reg
-[ ]*3[ ]+\.text
-[ ]*4[ ]+
-[ ]*5[ ]+\#\#\# bndmk
-[ ]*6[ ]+\?\?\?\? 67F30F1B bndmk \(%eax\), %bnd1
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*6[ ]+08
-[ ]*7[ ]+\?\?\?\? 67F30F1B bndmk 0x3\(%ecx,%ebx,1\), %bnd1
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*7[ ]+4C1903
-[ ]*8[ ]+
-[ ]*9[ ]+\#\#\# bndmov
-[ ]*10[ ]+\?\?\?\? 6766410F bndmov \(%r8d\), %bnd1
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*10[ ]+1A08
-[ ]*11[ ]+\?\?\?\? 6766410F bndmov 0x3\(%r9d,%edx,1\), %bnd1
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*11[ ]+1A4C1103
-[ ]*12[ ]+
-[ ]*13[ ]+\?\?\?\? 67660F1B bndmov %bnd1, \(%eax\)
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*13[ ]+08
-[ ]*14[ ]+\?\?\?\? 67660F1B bndmov %bnd1, 0x3\(%ecx,%eax,1\)
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*14[ ]+4C0103
-[ ]*15[ ]+
-[ ]*16[ ]+\#\#\# bndcl
-[ ]*17[ ]+\?\?\?\? 67F30F1A bndcl \(%ecx\), %bnd1
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*17[ ]+09
-[ ]*18[ ]+\?\?\?\? 67F30F1A bndcl 0x3\(%ecx,%eax,1\), %bnd1
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*18[ ]+4C0103
-[ ]*19[ ]+
-[ ]*20[ ]+\#\#\# bndcu
-[ ]*21[ ]+\?\?\?\? 67F20F1A bndcu \(%ecx\), %bnd1
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*21[ ]+09
-[ ]*22[ ]+\?\?\?\? 67F20F1A bndcu 0x3\(%ecx,%eax,1\), %bnd1
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*22[ ]+4C0103
-[ ]*23[ ]+
-[ ]*24[ ]+\#\#\# bndcn
-[ ]*25[ ]+\?\?\?\? 67F20F1B bndcn \(%ecx\), %bnd1
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*25[ ]+09
-[ ]*26[ ]+\?\?\?\? 67F20F1B bndcn 0x3\(%ecx,%eax,1\), %bnd1
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*26[ ]+4C0103
-[ ]*27[ ]+
-[ ]*28[ ]+\#\#\# bndstx
-[ ]*29[ ]+\?\?\?\? 670F1B44 bndstx %bnd0, 0x3\(%eax,%ebx,1\)
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*29[ ]+1803
-[ ]*30[ ]+\?\?\?\? 670F1B53 bndstx %bnd2, 3\(%ebx,1\)
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-\fGAS LISTING .*
-
-
-[ ]*30[ ]+03
-[ ]*31[ ]+
-[ ]*32[ ]+\#\#\# bndldx
-[ ]*33[ ]+\?\?\?\? 670F1A44 bndldx 0x3\(%eax,%ebx,1\), %bnd0
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*33[ ]+1803
-[ ]*34[ ]+\?\?\?\? 670F1A53 bndldx 3\(%ebx,1\), %bnd2
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*34[ ]+03
-[ ]*35[ ]+
-[ ]*36[ ]+\.intel_syntax noprefix
-[ ]*37[ ]+\?\?\?\? 67F30F1B bndmk bnd1, \[eax\]
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*37[ ]+08
-[ ]*38[ ]+\?\?\?\? 67F30F1B bndmk bnd1, \[edx\+1\*eax\+0x3\]
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*38[ ]+4C0203
-[ ]*39[ ]+
-[ ]*40[ ]+\#\#\# bndmov
-[ ]*41[ ]+\?\?\?\? 67660F1A bndmov bnd1, \[eax\]
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*41[ ]+08
-[ ]*42[ ]+\?\?\?\? 67660F1A bndmov bnd1, \[edx\+1\*eax\+0x3\]
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*42[ ]+4C0203
-[ ]*43[ ]+
-[ ]*44[ ]+\?\?\?\? 67660F1B bndmov \[eax\], bnd1
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*44[ ]+08
-[ ]*45[ ]+\?\?\?\? 67660F1B bndmov \[edx\+1\*eax\+0x3\], bnd1
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*45[ ]+4C0203
-[ ]*46[ ]+
-[ ]*47[ ]+\#\#\# bndcl
-[ ]*48[ ]+\?\?\?\? 67F30F1A bndcl bnd1, \[eax\]
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*48[ ]+08
-[ ]*49[ ]+\?\?\?\? 67F30F1A bndcl bnd1, \[edx\+1\*eax\+0x3\]
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*49[ ]+4C0203
-[ ]*50[ ]+
-[ ]*51[ ]+\#\#\# bndcu
-[ ]*52[ ]+\?\?\?\? 67F20F1A bndcu bnd1, \[eax\]
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*52[ ]+08
-[ ]*53[ ]+\?\?\?\? 67F20F1A bndcu bnd1, \[edx\+1\*eax\+0x3\]
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*53[ ]+4C0203
-[ ]*54[ ]+
-[ ]*55[ ]+\#\#\# bndcn
-[ ]*56[ ]+\?\?\?\? 67F20F1B bndcn bnd1, \[eax\]
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*56[ ]+08
-[ ]*57[ ]+\?\?\?\? 67F20F1B bndcn bnd1, \[edx\+1\*eax\+0x3\]
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*57[ ]+4C0203
-[ ]*58[ ]+
-\fGAS LISTING .*
-
-
-[ ]*59[ ]+\#\#\# bndstx
-[ ]*60[ ]+\?\?\?\? 670F1B44 bndstx \[eax\+ebx\*1\+0x3\], bnd0
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*60[ ]+1803
-[ ]*61[ ]+\?\?\?\? 670F1B14 bndstx \[1\*ebx\+3\], bnd2
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*61[ ]+1D030000
-[ ]*61[ ]+00
-[ ]*62[ ]+
-[ ]*63[ ]+\#\#\# bndldx
-[ ]*64[ ]+\?\?\?\? 670F1A44 bndldx bnd0, \[eax\+ebx\*1\+0x3\]
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*64[ ]+1803
-[ ]*65[ ]+\?\?\?\? 670F1A14 bndldx bnd2, \[1\*ebx\+3\]
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*65[ ]+1D030000
-[ ]*65[ ]+00
+#...
+[ ]*[1-9][0-9]*[ ]+\#\#\# bndmk
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F30F1B bndmk \(%eax\), %bnd1
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F30F1B bndmk 0x3\(%ecx,%ebx,1\), %bnd1
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+bndmk \(%rip\), %bnd3
+#...
+[ ]*[1-9][0-9]*[ ]+\#\#\# bndmov
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 6766410F bndmov \(%r8d\), %bnd1
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 6766410F bndmov 0x3\(%r9d,%edx,1\), %bnd1
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67660F1B bndmov %bnd1, \(%eax\)
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67660F1B bndmov %bnd1, 0x3\(%ecx,%eax,1\)
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\#\#\# bndcl
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F30F1A bndcl \(%ecx\), %bnd1
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F30F1A bndcl 0x3\(%ecx,%eax,1\), %bnd1
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? F30F1AC9 bndcl %ecx, %bnd1
+\*\*\*\* Warning:using `%rcx' instead of `%ecx' for `bndcl'
+#...
+[ ]*[1-9][0-9]*[ ]+\#\#\# bndcu
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F20F1A bndcu \(%ecx\), %bnd1
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F20F1A bndcu 0x3\(%ecx,%eax,1\), %bnd1
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? F20F1AC9 bndcu %ecx, %bnd1
+\*\*\*\* Warning:using `%rcx' instead of `%ecx' for `bndcu'
+#...
+[ ]*[1-9][0-9]*[ ]+\#\#\# bndcn
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F20F1B bndcn \(%ecx\), %bnd1
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F20F1B bndcn 0x3\(%ecx,%eax,1\), %bnd1
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? F20F1BC9 bndcn %ecx, %bnd1
+\*\*\*\* Warning:using `%rcx' instead of `%ecx' for `bndcn'
+#...
+[ ]*[1-9][0-9]*[ ]+\#\#\# bndstx
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 670F1B44 bndstx %bnd0, 0x3\(%eax,%ebx,1\)
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 670F1B53 bndstx %bnd2, 3\(%ebx,1\)
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 410F1B0C bndstx %bnd1, \(%r15,%rax,2\)
+\*\*\*\* Warning:register scaling is being ignored here
+#...
+[ ]*[1-9][0-9]*[ ]+bndstx %bnd3, base\(%rip\)
+#...
+[ ]*[1-9][0-9]*[ ]+\#\#\# bndldx
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 670F1A44 bndldx 0x3\(%eax,%ebx,1\), %bnd0
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 670F1A53 bndldx 3\(%ebx,1\), %bnd2
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 420F1A1C bndldx \(%rax,%r15,4\), %bnd3
+\*\*\*\* Warning:register scaling is being ignored here
+#...
+[ ]*[1-9][0-9]*[ ]+bndldx base\(%rip\), %bnd1
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F30F1B bndmk bnd1, \[eax\]
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F30F1B bndmk bnd1, \[edx\+1\*eax\+0x3\]
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+bndmk bnd3, \[rip\]
+[ ]*[1-9][0-9]*[ ]+bndmk bnd2, \[rax\+rsp\]
+#...
+[ ]*[1-9][0-9]*[ ]+\#\#\# bndmov
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67660F1A bndmov bnd1, \[eax\]
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67660F1A bndmov bnd1, \[edx\+1\*eax\+0x3\]
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67660F1B bndmov \[eax\], bnd1
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67660F1B bndmov \[edx\+1\*eax\+0x3\], bnd1
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\#\#\# bndcl
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F30F1A bndcl bnd1, \[eax\]
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F30F1A bndcl bnd1, \[edx\+1\*eax\+0x3\]
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? F30F1AC8 bndcl bnd1, eax
+\*\*\*\* Warning:using `rax' instead of `eax' for `bndcl'
+#...
+[ ]*[1-9][0-9]*[ ]+\#\#\# bndcu
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F20F1A bndcu bnd1, \[eax\]
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F20F1A bndcu bnd1, \[edx\+1\*eax\+0x3\]
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? F20F1AC8 bndcu bnd1, eax
+\*\*\*\* Warning:using `rax' instead of `eax' for `bndcu'
+#...
+[ ]*[1-9][0-9]*[ ]+\#\#\# bndcn
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F20F1B bndcn bnd1, \[eax\]
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F20F1B bndcn bnd1, \[edx\+1\*eax\+0x3\]
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? F20F1BC8 bndcn bnd1, eax
+\*\*\*\* Warning:using `rax' instead of `eax' for `bndcn'
+#...
+[ ]*[1-9][0-9]*[ ]+\#\#\# bndstx
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 670F1B44 bndstx \[eax\+ebx\*1\+0x3\], bnd0
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 670F1B14 bndstx \[1\*ebx\+3\], bnd2
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 410F1B14 bndstx \[r8\+rdi\*4\], bnd2
+\*\*\*\* Warning:register scaling is being ignored here
+#...
+[ ]*[1-9][0-9]*[ ]+bndstx \[rip\+base\], bnd1
+[ ]*[1-9][0-9]*[ ]+bndstx \[rax\+rsp\], bnd3
+#...
+[ ]*[1-9][0-9]*[ ]+\#\#\# bndldx
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 670F1A44 bndldx bnd0, \[eax\+ebx\*1\+0x3\]
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 670F1A14 bndldx bnd2, \[1\*ebx\+3\]
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 420F1A14 bndldx bnd2, \[rdi\+r8\*8\]
+\*\*\*\* Warning:register scaling is being ignored here
+#...
+[ ]*[1-9][0-9]*[ ]+bndldx bnd1, \[rip\+base\]
+[ ]*[1-9][0-9]*[ ]+bndldx bnd3, \[rax\+rsp\]
--- 2013-10-07/gas/testsuite/gas/i386/x86-64-mpx-inval-2.s
+++ 2013-10-07/gas/testsuite/gas/i386/x86-64-mpx-inval-2.s
@@ -5,6 +5,7 @@
### bndmk
bndmk (%eax), %bnd1
bndmk 0x3(%ecx,%ebx,1), %bnd1
+ bndmk (%rip), %bnd3
### bndmov
bndmov (%r8d), %bnd1
@@ -16,26 +17,38 @@
### bndcl
bndcl (%ecx), %bnd1
bndcl 0x3(%ecx,%eax,1), %bnd1
+ bndcl %ecx, %bnd1
+ bndcl %cx, %bnd1
### bndcu
bndcu (%ecx), %bnd1
bndcu 0x3(%ecx,%eax,1), %bnd1
+ bndcu %ecx, %bnd1
+ bndcu %cx, %bnd1
### bndcn
bndcn (%ecx), %bnd1
bndcn 0x3(%ecx,%eax,1), %bnd1
+ bndcn %ecx, %bnd1
+ bndcn %cx, %bnd1
### bndstx
bndstx %bnd0, 0x3(%eax,%ebx,1)
bndstx %bnd2, 3(%ebx,1)
+ bndstx %bnd1, (%r15,%rax,2)
+ bndstx %bnd3, base(%rip)
### bndldx
bndldx 0x3(%eax,%ebx,1), %bnd0
bndldx 3(%ebx,1), %bnd2
+ bndldx (%rax,%r15,4), %bnd3
+ bndldx base(%rip), %bnd1
.intel_syntax noprefix
bndmk bnd1, [eax]
bndmk bnd1, [edx+1*eax+0x3]
+ bndmk bnd3, [rip]
+ bndmk bnd2, [rax+rsp]
### bndmov
bndmov bnd1, [eax]
@@ -47,19 +60,31 @@
### bndcl
bndcl bnd1, [eax]
bndcl bnd1, [edx+1*eax+0x3]
+ bndcl bnd1, eax
+ bndcl bnd1, dx
### bndcu
bndcu bnd1, [eax]
bndcu bnd1, [edx+1*eax+0x3]
+ bndcu bnd1, eax
+ bndcu bnd1, dx
### bndcn
bndcn bnd1, [eax]
bndcn bnd1, [edx+1*eax+0x3]
+ bndcn bnd1, eax
+ bndcn bnd1, dx
### bndstx
bndstx [eax+ebx*1+0x3], bnd0
bndstx [1*ebx+3], bnd2
+ bndstx [r8+rdi*4], bnd2
+ bndstx [rip+base], bnd1
+ bndstx [rax+rsp], bnd3
### bndldx
bndldx bnd0, [eax+ebx*1+0x3]
bndldx bnd2, [1*ebx+3]
+ bndldx bnd2, [rdi+r8*8]
+ bndldx bnd1, [rip+base]
+ bndldx bnd3, [rax+rsp]
--- 2013-10-07/gas/testsuite/gas/i386/x86-64-mpx.d
+++ 2013-10-07/gas/testsuite/gas/i386/x86-64-mpx.d
@@ -6,7 +6,7 @@
Disassembly of section .text:
-0+ <foo-0x434>:
+0+ <foo-0x[0-9a-f]+>:
[ ]*[a-f0-9]+: f3 41 0f 1b 0b bndmk \(%r11\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1b 08 bndmk \(%rax\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1b 0c 25 99 03 00 00 bndmk 0x399,%bnd1
@@ -38,9 +38,8 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 0f 1a d0 bndmov %bnd0,%bnd2
[ ]*[a-f0-9]+: f3 41 0f 1a 0b bndcl \(%r11\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1a 08 bndcl \(%rax\),%bnd1
-[ ]*[a-f0-9]+: f3 49 0f 1a cb bndcl %r11,%bnd1
-[ ]*[a-f0-9]+: f3 48 0f 1a c9 bndcl %rcx,%bnd1
-[ ]*[a-f0-9]+: f3 0f 1a c8 bndcl %eax,%bnd1
+[ ]*[a-f0-9]+: f3 41 0f 1a cb bndcl %r11,%bnd1
+[ ]*[a-f0-9]+: f3 0f 1a c9 bndcl %rcx,%bnd1
[ ]*[a-f0-9]+: f3 0f 1a 0c 25 99 03 00 00 bndcl 0x399,%bnd1
[ ]*[a-f0-9]+: f3 41 0f 1a 51 03 bndcl 0x3\(%r9\),%bnd2
[ ]*[a-f0-9]+: f3 0f 1a 50 03 bndcl 0x3\(%rax\),%bnd2
@@ -50,9 +49,8 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: f3 42 0f 1a 4c 0b 03 bndcl 0x3\(%rbx,%r9,1\),%bnd1
[ ]*[a-f0-9]+: f2 41 0f 1a 0b bndcu \(%r11\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1a 08 bndcu \(%rax\),%bnd1
-[ ]*[a-f0-9]+: f2 49 0f 1a cb bndcu %r11,%bnd1
-[ ]*[a-f0-9]+: f2 48 0f 1a c9 bndcu %rcx,%bnd1
-[ ]*[a-f0-9]+: f2 0f 1a c8 bndcu %eax,%bnd1
+[ ]*[a-f0-9]+: f2 41 0f 1a cb bndcu %r11,%bnd1
+[ ]*[a-f0-9]+: f2 0f 1a c9 bndcu %rcx,%bnd1
[ ]*[a-f0-9]+: f2 0f 1a 0c 25 99 03 00 00 bndcu 0x399,%bnd1
[ ]*[a-f0-9]+: f2 41 0f 1a 51 03 bndcu 0x3\(%r9\),%bnd2
[ ]*[a-f0-9]+: f2 0f 1a 50 03 bndcu 0x3\(%rax\),%bnd2
@@ -62,9 +60,8 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: f2 42 0f 1a 4c 0b 03 bndcu 0x3\(%rbx,%r9,1\),%bnd1
[ ]*[a-f0-9]+: f2 41 0f 1b 0b bndcn \(%r11\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1b 08 bndcn \(%rax\),%bnd1
-[ ]*[a-f0-9]+: f2 49 0f 1b cb bndcn %r11,%bnd1
-[ ]*[a-f0-9]+: f2 48 0f 1b c9 bndcn %rcx,%bnd1
-[ ]*[a-f0-9]+: f2 0f 1b c8 bndcn %eax,%bnd1
+[ ]*[a-f0-9]+: f2 41 0f 1b cb bndcn %r11,%bnd1
+[ ]*[a-f0-9]+: f2 0f 1b c9 bndcn %rcx,%bnd1
[ ]*[a-f0-9]+: f2 0f 1b 0c 25 99 03 00 00 bndcn 0x399,%bnd1
[ ]*[a-f0-9]+: f2 41 0f 1b 51 03 bndcn 0x3\(%r9\),%bnd2
[ ]*[a-f0-9]+: f2 0f 1b 50 03 bndcn 0x3\(%rax\),%bnd2
@@ -88,11 +85,11 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f 1a 14 1d 03 00 00 00 bndldx 0x3\(,%rbx,1\),%bnd2
[ ]*[a-f0-9]+: 42 0f 1a 14 25 03 00 00 00 bndldx 0x3\(,%r12,1\),%bnd2
[ ]*[a-f0-9]+: 0f 1a 0a bndldx \(%rdx\),%bnd1
-[ ]*[a-f0-9]+: f2 e8 34 02 00 00 bnd callq 434 <foo>
+[ ]*[a-f0-9]+: f2 e8 .. .. 00 00 bnd callq [0-9a-f]+ <foo>
[ ]*[a-f0-9]+: f2 ff 10 bnd callq \*\(%rax\)
[ ]*[a-f0-9]+: f2 41 ff 13 bnd callq \*\(%r11\)
-[ ]*[a-f0-9]+: f2 0f 84 26 02 00 00 bnd je 434 <foo>
-[ ]*[a-f0-9]+: f2 e9 20 02 00 00 bnd jmpq 434 <foo>
+[ ]*[a-f0-9]+: f2 0f 84 .. .. 00 00 bnd je [0-9a-f]+ <foo>
+[ ]*[a-f0-9]+: f2 e9 .. .. 00 00 bnd jmpq [0-9a-f]+ <foo>
[ ]*[a-f0-9]+: f2 ff 21 bnd jmpq \*\(%rcx\)
[ ]*[a-f0-9]+: f2 41 ff 24 24 bnd jmpq \*\(%r12\)
[ ]*[a-f0-9]+: f2 c3 bnd retq
@@ -127,9 +124,8 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 0f 1a d0 bndmov %bnd0,%bnd2
[ ]*[a-f0-9]+: f3 41 0f 1a 0b bndcl \(%r11\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1a 08 bndcl \(%rax\),%bnd1
-[ ]*[a-f0-9]+: f3 49 0f 1a cb bndcl %r11,%bnd1
-[ ]*[a-f0-9]+: f3 48 0f 1a c9 bndcl %rcx,%bnd1
-[ ]*[a-f0-9]+: f3 0f 1a c8 bndcl %eax,%bnd1
+[ ]*[a-f0-9]+: f3 41 0f 1a cb bndcl %r11,%bnd1
+[ ]*[a-f0-9]+: f3 0f 1a c9 bndcl %rcx,%bnd1
[ ]*[a-f0-9]+: f3 0f 1a 0c 25 99 03 00 00 bndcl 0x399,%bnd1
[ ]*[a-f0-9]+: f3 41 0f 1a 49 03 bndcl 0x3\(%r9\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1a 48 03 bndcl 0x3\(%rax\),%bnd1
@@ -139,9 +135,8 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: f3 42 0f 1a 4c 0b 03 bndcl 0x3\(%rbx,%r9,1\),%bnd1
[ ]*[a-f0-9]+: f2 41 0f 1a 0b bndcu \(%r11\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1a 08 bndcu \(%rax\),%bnd1
-[ ]*[a-f0-9]+: f2 49 0f 1a cb bndcu %r11,%bnd1
-[ ]*[a-f0-9]+: f2 48 0f 1a c9 bndcu %rcx,%bnd1
-[ ]*[a-f0-9]+: f2 0f 1a c8 bndcu %eax,%bnd1
+[ ]*[a-f0-9]+: f2 41 0f 1a cb bndcu %r11,%bnd1
+[ ]*[a-f0-9]+: f2 0f 1a c9 bndcu %rcx,%bnd1
[ ]*[a-f0-9]+: f2 0f 1a 0c 25 99 03 00 00 bndcu 0x399,%bnd1
[ ]*[a-f0-9]+: f2 41 0f 1a 49 03 bndcu 0x3\(%r9\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1a 48 03 bndcu 0x3\(%rax\),%bnd1
@@ -151,9 +146,8 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: f2 42 0f 1a 4c 0b 03 bndcu 0x3\(%rbx,%r9,1\),%bnd1
[ ]*[a-f0-9]+: f2 41 0f 1b 0b bndcn \(%r11\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1b 08 bndcn \(%rax\),%bnd1
-[ ]*[a-f0-9]+: f2 49 0f 1b cb bndcn %r11,%bnd1
-[ ]*[a-f0-9]+: f2 48 0f 1b c9 bndcn %rcx,%bnd1
-[ ]*[a-f0-9]+: f2 0f 1b c8 bndcn %eax,%bnd1
+[ ]*[a-f0-9]+: f2 41 0f 1b cb bndcn %r11,%bnd1
+[ ]*[a-f0-9]+: f2 0f 1b c9 bndcn %rcx,%bnd1
[ ]*[a-f0-9]+: f2 0f 1b 0c 25 99 03 00 00 bndcn 0x399,%bnd1
[ ]*[a-f0-9]+: f2 41 0f 1b 49 03 bndcn 0x3\(%r9\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1b 48 03 bndcn 0x3\(%rax\),%bnd1
@@ -177,15 +171,15 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f 1a 14 1d 03 00 00 00 bndldx 0x3\(,%rbx,1\),%bnd2
[ ]*[a-f0-9]+: 42 0f 1a 14 25 03 00 00 00 bndldx 0x3\(,%r12,1\),%bnd2
[ ]*[a-f0-9]+: 0f 1a 0a bndldx \(%rdx\),%bnd1
-[ ]*[a-f0-9]+: f2 e8 16 00 00 00 bnd callq 434 <foo>
+[ ]*[a-f0-9]+: f2 e8 .. 00 00 00 bnd callq [0-9a-f]+ <foo>
[ ]*[a-f0-9]+: f2 ff d0 bnd callq \*%rax
[ ]*[a-f0-9]+: f2 41 ff d3 bnd callq \*%r11
-[ ]*[a-f0-9]+: f2 74 0c bnd je 434 <foo>
-[ ]*[a-f0-9]+: f2 eb 09 bnd jmp 434 <foo>
+[ ]*[a-f0-9]+: f2 74 .. bnd je [0-9a-f]+ <foo>
+[ ]*[a-f0-9]+: f2 eb .. bnd jmp [0-9a-f]+ <foo>
[ ]*[a-f0-9]+: f2 ff e1 bnd jmpq \*%rcx
[ ]*[a-f0-9]+: f2 41 ff e4 bnd jmpq \*%r12
[ ]*[a-f0-9]+: f2 c3 bnd retq
-0+434 <foo>:
+[0-9a-f]+ <foo>:
[ ]*[a-f0-9]+: f2 c3 bnd retq
#pass
--- 2013-10-07/gas/testsuite/gas/i386/x86-64-mpx.s
+++ 2013-10-07/gas/testsuite/gas/i386/x86-64-mpx.s
@@ -41,7 +41,6 @@
bndcl (%rax), %bnd1
bndcl %r11, %bnd1
bndcl %rcx, %bnd1
- bndcl %ax, %bnd1
bndcl (0x399), %bnd1
bndcl 0x3(%r9), %bnd2
bndcl 0x3(%rax), %bnd2
@@ -55,7 +54,6 @@
bndcu (%rax), %bnd1
bndcu %r11, %bnd1
bndcu %rcx, %bnd1
- bndcu %ax, %bnd1
bndcu (0x399), %bnd1
bndcu 0x3(%r9), %bnd2
bndcu 0x3(%rax), %bnd2
@@ -69,7 +67,6 @@
bndcn (%rax), %bnd1
bndcn %r11, %bnd1
bndcn %rcx, %bnd1
- bndcn %ax, %bnd1
bndcn (0x399), %bnd1
bndcn 0x3(%r9), %bnd2
bndcn 0x3(%rax), %bnd2
@@ -147,7 +144,6 @@
bndcl bnd1, [rax]
bndcl bnd1, r11
bndcl bnd1, rcx
- bndcl bnd1, ax
bndcl bnd1, [0x399]
bndcl bnd1, [r9+0x3]
bndcl bnd1, [rax+0x3]
@@ -161,7 +157,6 @@
bndcu bnd1, [rax]
bndcu bnd1, r11
bndcu bnd1, rcx
- bndcu bnd1, ax
bndcu bnd1, [0x399]
bndcu bnd1, [r9+0x3]
bndcu bnd1, [rax+0x3]
@@ -175,7 +170,6 @@
bndcn bnd1, [rax]
bndcn bnd1, r11
bndcn bnd1, rcx
- bndcn bnd1, ax
bndcn bnd1, [0x399]
bndcn bnd1, [r9+0x3]
bndcn bnd1, [rax+0x3]
[-- Attachment #2: binutils-mainline-x86-MPX-testsuite.patch --]
[-- Type: text/plain, Size: 44588 bytes --]
This will by itself introduce testsuite failures which get addressed
by subsequent patches.
gas/testsuite/
2013-10-08 Jan Beulich <jbeulich@suse.com>
* gas/i386/mpx-inval-2.[sl]: New.
* gas/i386/i386.exp: Run new test.
* gas/i386/mpx.s: Remove invalid tests involving 16-bit register
operands to bndc[lnu].
* gas/i386/mpx.d: Adjust accordingly.
* gas/i386/x86-64-mpx.s: Remove invalid tests involving 16-bit
register operands to bndc[lnu].
* gas/i386/x86-64-mpx.d: Adjust accordingly.
* gas/i386/x86-64-mpx-inval-2.s: Add tests for invalid uses of RIP-
relative addressing, 16- and 32-bit register operands, as well as a
special case of Intel mode memory operands.
* gas/i386/x86-64-mpx-inval-2.l: Adjust accordingly and generalize.
--- 2013-10-07/gas/testsuite/gas/i386/i386.exp
+++ 2013-10-07/gas/testsuite/gas/i386/i386.exp
@@ -267,6 +267,7 @@ if [expr ([istarget "i*86-*-*"] || [ist
run_dump_test "smap"
run_dump_test "mpx"
run_list_test "mpx-inval-1" "-al"
+ run_list_test "mpx-inval-2" "-al"
run_dump_test "mpx-add-bnd-prefix"
run_dump_test "sha"
--- /dev/null
+++ 2013-10-07/gas/testsuite/gas/i386/mpx-inval-2.l
@@ -0,0 +1,145 @@
+.*: Assembler messages:
+.*:5: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:6: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:7: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:8: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:9: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:10: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:11: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:12: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:14: Error: operand type mismatch for `bndcl'
+.*:15: Error: operand type mismatch for `bndcn'
+.*:16: Error: operand type mismatch for `bndcu'
+.*:19: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:20: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:21: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:22: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:23: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:24: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:25: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:26: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:28: Error: operand type mismatch for `bndcl'
+.*:29: Error: operand type mismatch for `bndcn'
+.*:30: Error: operand type mismatch for `bndcu'
+.*:35: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:36: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:37: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:38: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:39: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:40: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:41: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:42: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:44: Error: operand type mismatch for `bndcl'
+.*:45: Error: operand type mismatch for `bndcn'
+.*:46: Error: operand type mismatch for `bndcu'
+.*:49: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:50: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:51: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:52: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:53: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:54: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:55: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:56: Error: 16-bit addressing isn't allowed in MPX instructions
+.*:58: Error: operand type mismatch for `bndcl'
+.*:59: Error: operand type mismatch for `bndcn'
+.*:60: Error: operand type mismatch for `bndcu'
+GAS LISTING .*
+#...
+[ ]*[1-9][0-9]*[ ]+mpx32:
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndcl \(%bx,%si\), %bnd0
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndcn \(%bx,%di\), %bnd0
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndcu \(%bp,%si\), %bnd0
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndldx \(%bp,%di\), %bnd0
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndmk \(%bx\), %bnd0
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndmov \(%bp\), %bnd0
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndmov %bnd0, \(%si\)
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndstx %bnd0, \(%di\)
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndcl bnd0, \[bx\]
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndcn bnd0, \[bp\]
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndcu bnd0, \[si\]
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndldx bnd0, \[di\]
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndmk bnd0, \[bx\+si\]
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndmov bnd0, \[bx\+di\]
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndmov \[bp\+si\], bnd0
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndstx \[bp\+di\], bnd0
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+mpx16:
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndcl \(%bx,%si\), %bnd0
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndcn \(%bx,%di\), %bnd0
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndcu \(%bp,%si\), %bnd0
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndldx \(%bp,%di\), %bnd0
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndmk \(%bx\), %bnd0
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndmov \(%bp\), %bnd0
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndmov %bnd0, \(%si\)
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndstx %bnd0, \(%di\)
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndcl bnd0, \[bx\]
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndcn bnd0, \[bp\]
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndcu bnd0, \[si\]
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndldx bnd0, \[di\]
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndmk bnd0, \[bx\+si\]
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndmov bnd0, \[bx\+di\]
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndmov \[bp\+si\], bnd0
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+[?0-9A-F ]*bndstx \[bp\+di\], bnd0
+\*\*\*\* Error:16-bit addressing isn't allowed in MPX instructions
+#...
--- /dev/null
+++ 2013-10-07/gas/testsuite/gas/i386/mpx-inval-2.s
@@ -0,0 +1,60 @@
+# MPX instructions
+ .text
+ .code32
+mpx32:
+ bndcl (%bx,%si), %bnd0
+ bndcn (%bx,%di), %bnd0
+ bndcu (%bp,%si), %bnd0
+ bndldx (%bp,%di), %bnd0
+ bndmk (%bx), %bnd0
+ bndmov (%bp), %bnd0
+ bndmov %bnd0, (%si)
+ bndstx %bnd0, (%di)
+
+ bndcl %di, %bnd1
+ bndcn %si, %bnd2
+ bndcu %bp, %bnd3
+
+ .intel_syntax noprefix
+ bndcl bnd0, [bx]
+ bndcn bnd0, [bp]
+ bndcu bnd0, [si]
+ bndldx bnd0, [di]
+ bndmk bnd0, [bx+si]
+ bndmov bnd0, [bx+di]
+ bndmov [bp+si], bnd0
+ bndstx [bp+di], bnd0
+
+ bndcl bnd3, ax
+ bndcn bnd2, cx
+ bndcu bnd1, dx
+
+ .att_syntax prefix
+ .code16
+mpx16:
+ bndcl (%bx,%si), %bnd0
+ bndcn (%bx,%di), %bnd0
+ bndcu (%bp,%si), %bnd0
+ bndldx (%bp,%di), %bnd0
+ bndmk (%bx), %bnd0
+ bndmov (%bp), %bnd0
+ bndmov %bnd0, (%si)
+ bndstx %bnd0, (%di)
+
+ bndcl %di, %bnd1
+ bndcn %si, %bnd2
+ bndcu %bp, %bnd3
+
+ .intel_syntax noprefix
+ bndcl bnd0, [bx]
+ bndcn bnd0, [bp]
+ bndcu bnd0, [si]
+ bndldx bnd0, [di]
+ bndmk bnd0, [bx+si]
+ bndmov bnd0, [bx+di]
+ bndmov [bp+si], bnd0
+ bndstx [bp+di], bnd0
+
+ bndcl bnd3, ax
+ bndcn bnd2, cx
+ bndcu bnd1, dx
--- 2013-10-07/gas/testsuite/gas/i386/mpx.d
+++ 2013-10-07/gas/testsuite/gas/i386/mpx.d
@@ -6,7 +6,7 @@
Disassembly of section .text:
-0+ <foo-0x2c1>:
+0+ <foo-0x[0-9a-f]+>:
[ ]*[a-f0-9]+: f3 0f 1b 08 bndmk \(%eax\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1b 0d 99 03 00 00 bndmk 0x399,%bnd1
[ ]*[a-f0-9]+: f3 0f 1b 4a 03 bndmk 0x3\(%edx\),%bnd1
@@ -29,7 +29,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 0f 1a d0 bndmov %bnd0,%bnd2
[ ]*[a-f0-9]+: f3 0f 1a 09 bndcl \(%ecx\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1a c9 bndcl %ecx,%bnd1
-[ ]*[a-f0-9]+: f3 0f 1a c8 bndcl %eax,%bnd1
[ ]*[a-f0-9]+: f3 0f 1a 0d 99 03 00 00 bndcl 0x399,%bnd1
[ ]*[a-f0-9]+: f3 0f 1a 4a 03 bndcl 0x3\(%edx\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1a 0c 08 bndcl \(%eax,%ecx,1\),%bnd1
@@ -37,7 +36,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: f3 0f 1a 4c 01 03 bndcl 0x3\(%ecx,%eax,1\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1a 09 bndcu \(%ecx\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1a c9 bndcu %ecx,%bnd1
-[ ]*[a-f0-9]+: f2 0f 1a c8 bndcu %eax,%bnd1
[ ]*[a-f0-9]+: f2 0f 1a 0d 99 03 00 00 bndcu 0x399,%bnd1
[ ]*[a-f0-9]+: f2 0f 1a 4a 03 bndcu 0x3\(%edx\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1a 0c 08 bndcu \(%eax,%ecx,1\),%bnd1
@@ -45,7 +43,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: f2 0f 1a 4c 01 03 bndcu 0x3\(%ecx,%eax,1\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1b 09 bndcn \(%ecx\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1b c9 bndcn %ecx,%bnd1
-[ ]*[a-f0-9]+: f2 0f 1b c8 bndcn %eax,%bnd1
[ ]*[a-f0-9]+: f2 0f 1b 0d 99 03 00 00 bndcn 0x399,%bnd1
[ ]*[a-f0-9]+: f2 0f 1b 4a 03 bndcn 0x3\(%edx\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1b 0c 08 bndcn \(%eax,%ecx,1\),%bnd1
@@ -65,10 +62,10 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f 1a 93 34 12 00 00 bndldx 0x1234\(%ebx\),%bnd2
[ ]*[a-f0-9]+: 0f 1a 53 03 bndldx 0x3\(%ebx\),%bnd2
[ ]*[a-f0-9]+: 0f 1a 0a bndldx \(%edx\),%bnd1
-[ ]*[a-f0-9]+: f2 e8 6f 01 00 00 bnd call 2c1 <foo>
+[ ]*[a-f0-9]+: f2 e8 .. .. 00 00 bnd call [0-9a-f]+ <foo>
[ ]*[a-f0-9]+: f2 ff 10 bnd call \*\(%eax\)
-[ ]*[a-f0-9]+: f2 0f 84 65 01 00 00 bnd je 2c1 <foo>
-[ ]*[a-f0-9]+: f2 e9 5f 01 00 00 bnd jmp 2c1 <foo>
+[ ]*[a-f0-9]+: f2 0f 84 .. .. 00 00 bnd je [0-9a-f]+ <foo>
+[ ]*[a-f0-9]+: f2 e9 .. .. 00 00 bnd jmp [0-9a-f]+ <foo>
[ ]*[a-f0-9]+: f2 ff 21 bnd jmp \*\(%ecx\)
[ ]*[a-f0-9]+: f2 c3 bnd ret
[ ]*[a-f0-9]+: f3 0f 1b 08 bndmk \(%eax\),%bnd1
@@ -93,7 +90,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 0f 1a c8 bndmov %bnd0,%bnd1
[ ]*[a-f0-9]+: f3 0f 1a 08 bndcl \(%eax\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1a c9 bndcl %ecx,%bnd1
-[ ]*[a-f0-9]+: f3 0f 1a c8 bndcl %eax,%bnd1
[ ]*[a-f0-9]+: f3 0f 1a 0d 99 03 00 00 bndcl 0x399,%bnd1
[ ]*[a-f0-9]+: f3 0f 1a 49 03 bndcl 0x3\(%ecx\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1a 0c 08 bndcl \(%eax,%ecx,1\),%bnd1
@@ -101,7 +97,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: f3 0f 1a 4c 02 03 bndcl 0x3\(%edx,%eax,1\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1a 08 bndcu \(%eax\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1a c9 bndcu %ecx,%bnd1
-[ ]*[a-f0-9]+: f2 0f 1a c8 bndcu %eax,%bnd1
[ ]*[a-f0-9]+: f2 0f 1a 0d 99 03 00 00 bndcu 0x399,%bnd1
[ ]*[a-f0-9]+: f2 0f 1a 49 03 bndcu 0x3\(%ecx\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1a 0c 08 bndcu \(%eax,%ecx,1\),%bnd1
@@ -109,7 +104,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: f2 0f 1a 4c 02 03 bndcu 0x3\(%edx,%eax,1\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1b 08 bndcn \(%eax\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1b c9 bndcn %ecx,%bnd1
-[ ]*[a-f0-9]+: f2 0f 1b c8 bndcn %eax,%bnd1
[ ]*[a-f0-9]+: f2 0f 1b 0d 99 03 00 00 bndcn 0x399,%bnd1
[ ]*[a-f0-9]+: f2 0f 1b 49 03 bndcn 0x3\(%ecx\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1b 0c 08 bndcn \(%eax,%ecx,1\),%bnd1
@@ -127,13 +121,13 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f 1a 9a 99 03 00 00 bndldx 0x399\(%edx\),%bnd3
[ ]*[a-f0-9]+: 0f 1a 14 1d 03 00 00 00 bndldx 0x3\(,%ebx,1\),%bnd2
[ ]*[a-f0-9]+: 0f 1a 0a bndldx \(%edx\),%bnd1
-[ ]*[a-f0-9]+: f2 e8 0e 00 00 00 bnd call 2c1 <foo>
+[ ]*[a-f0-9]+: f2 e8 .. 00 00 00 bnd call [0-9a-f]+ <foo>
[ ]*[a-f0-9]+: f2 ff d0 bnd call \*%eax
-[ ]*[a-f0-9]+: f2 74 08 bnd je 2c1 <foo>
-[ ]*[a-f0-9]+: f2 eb 05 bnd jmp 2c1 <foo>
+[ ]*[a-f0-9]+: f2 74 .. bnd je [0-9a-f]+ <foo>
+[ ]*[a-f0-9]+: f2 eb .. bnd jmp [0-9a-f]+ <foo>
[ ]*[a-f0-9]+: f2 ff e1 bnd jmp \*%ecx
[ ]*[a-f0-9]+: f2 c3 bnd ret
-0+2c1 <foo>:
+[0-9a-f]+ <foo>:
[ ]*[a-f0-9]+: f2 c3 bnd ret
#pass
--- 2013-10-07/gas/testsuite/gas/i386/mpx.s
+++ 2013-10-07/gas/testsuite/gas/i386/mpx.s
@@ -30,7 +30,6 @@
### bndcl
bndcl (%ecx), %bnd1
bndcl %ecx, %bnd1
- bndcl %ax, %bnd1
bndcl (0x399), %bnd1
bndcl 0x3(%edx), %bnd1
bndcl (%eax,%ecx), %bnd1
@@ -40,7 +39,6 @@
### bndcu
bndcu (%ecx), %bnd1
bndcu %ecx, %bnd1
- bndcu %ax, %bnd1
bndcu (0x399), %bnd1
bndcu 0x3(%edx), %bnd1
bndcu (%eax,%ecx), %bnd1
@@ -50,7 +48,6 @@
### bndcn
bndcn (%ecx), %bnd1
bndcn %ecx, %bnd1
- bndcn %ax, %bnd1
bndcn (0x399), %bnd1
bndcn 0x3(%edx), %bnd1
bndcn (%eax,%ecx), %bnd1
@@ -111,7 +108,6 @@
### bndcl
bndcl bnd1, [eax]
bndcl bnd1, ecx
- bndcl bnd1, ax
bndcl bnd1, [0x399]
bndcl bnd1, [ecx+0x3]
bndcl bnd1, [eax+ecx]
@@ -121,7 +117,6 @@
### bndcu
bndcu bnd1, [eax]
bndcu bnd1, ecx
- bndcu bnd1, ax
bndcu bnd1, [0x399]
bndcu bnd1, [ecx+0x3]
bndcu bnd1, [eax+ecx]
@@ -131,7 +126,6 @@
### bndcn
bndcn bnd1, [eax]
bndcn bnd1, ecx
- bndcn bnd1, ax
bndcn bnd1, [0x399]
bndcn bnd1, [ecx+0x3]
bndcn bnd1, [eax+ecx]
--- 2013-10-07/gas/testsuite/gas/i386/x86-64-mpx-inval-2.l
+++ 2013-10-07/gas/testsuite/gas/i386/x86-64-mpx-inval-2.l
@@ -1,173 +1,213 @@
.*: Assembler messages:
-.*:6: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:7: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:10: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:11: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:13: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:14: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:17: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:18: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:21: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:22: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:25: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:26: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:29: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:30: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:33: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:34: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:37: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:38: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:41: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:42: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:44: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:45: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:48: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:49: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:52: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:53: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:56: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:57: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:60: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:61: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:64: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-.*:65: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
+.*:6: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:7: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:8: Error: `\(%rip\)' cannot be used here
+.*:11: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:12: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:14: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:15: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:18: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:19: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:20: Warning: using `%rcx' instead of `%ecx' for `bndcl'
+.*:21: Error: operand type mismatch for `bndcl'
+.*:24: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:25: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:26: Warning: using `%rcx' instead of `%ecx' for `bndcu'
+.*:27: Error: operand type mismatch for `bndcu'
+.*:30: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:31: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:32: Warning: using `%rcx' instead of `%ecx' for `bndcn'
+.*:33: Error: operand type mismatch for `bndcn'
+.*:36: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:37: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:38: Warning: register scaling is being ignored here
+.*:39: Error: `base\(%rip\)' cannot be used here
+.*:42: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:43: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:44: Warning: register scaling is being ignored here
+.*:45: Error: `base\(%rip\)' cannot be used here
+.*:48: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:49: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:50: Error: `\[rip\]' cannot be used here
+.*:51: Error: `\[rax\+rsp\]' is not a valid base/index expression
+.*:54: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:55: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:57: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:58: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:61: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:62: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:63: Warning: using `rax' instead of `eax' for `bndcl'
+.*:64: Error: operand type mismatch for `bndcl'
+.*:67: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:68: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:69: Warning: using `rax' instead of `eax' for `bndcu'
+.*:70: Error: operand type mismatch for `bndcu'
+.*:73: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:74: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:75: Warning: using `rax' instead of `eax' for `bndcn'
+.*:76: Error: operand type mismatch for `bndcn'
+.*:79: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:80: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:81: Warning: register scaling is being ignored here
+.*:82: Error: `\[rip\+base\]' cannot be used here
+.*:83: Error: `\[rax\+rsp\]' is not a valid base/index expression
+.*:86: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:87: Warning: 32-bit addressing is ignored in 64-bit MPX instructions
+.*:88: Warning: register scaling is being ignored here
+.*:89: Error: `\[rip\+base\]' cannot be used here
+.*:90: Error: `\[rax\+rsp\]' is not a valid base/index expression
GAS LISTING .*
-
-
-[ ]*1[ ]+\# MPX instructions
-[ ]*2[ ]+\.allow_index_reg
-[ ]*3[ ]+\.text
-[ ]*4[ ]+
-[ ]*5[ ]+\#\#\# bndmk
-[ ]*6[ ]+\?\?\?\? 67F30F1B bndmk \(%eax\), %bnd1
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*6[ ]+08
-[ ]*7[ ]+\?\?\?\? 67F30F1B bndmk 0x3\(%ecx,%ebx,1\), %bnd1
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*7[ ]+4C1903
-[ ]*8[ ]+
-[ ]*9[ ]+\#\#\# bndmov
-[ ]*10[ ]+\?\?\?\? 6766410F bndmov \(%r8d\), %bnd1
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*10[ ]+1A08
-[ ]*11[ ]+\?\?\?\? 6766410F bndmov 0x3\(%r9d,%edx,1\), %bnd1
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*11[ ]+1A4C1103
-[ ]*12[ ]+
-[ ]*13[ ]+\?\?\?\? 67660F1B bndmov %bnd1, \(%eax\)
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*13[ ]+08
-[ ]*14[ ]+\?\?\?\? 67660F1B bndmov %bnd1, 0x3\(%ecx,%eax,1\)
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*14[ ]+4C0103
-[ ]*15[ ]+
-[ ]*16[ ]+\#\#\# bndcl
-[ ]*17[ ]+\?\?\?\? 67F30F1A bndcl \(%ecx\), %bnd1
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*17[ ]+09
-[ ]*18[ ]+\?\?\?\? 67F30F1A bndcl 0x3\(%ecx,%eax,1\), %bnd1
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*18[ ]+4C0103
-[ ]*19[ ]+
-[ ]*20[ ]+\#\#\# bndcu
-[ ]*21[ ]+\?\?\?\? 67F20F1A bndcu \(%ecx\), %bnd1
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*21[ ]+09
-[ ]*22[ ]+\?\?\?\? 67F20F1A bndcu 0x3\(%ecx,%eax,1\), %bnd1
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*22[ ]+4C0103
-[ ]*23[ ]+
-[ ]*24[ ]+\#\#\# bndcn
-[ ]*25[ ]+\?\?\?\? 67F20F1B bndcn \(%ecx\), %bnd1
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*25[ ]+09
-[ ]*26[ ]+\?\?\?\? 67F20F1B bndcn 0x3\(%ecx,%eax,1\), %bnd1
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*26[ ]+4C0103
-[ ]*27[ ]+
-[ ]*28[ ]+\#\#\# bndstx
-[ ]*29[ ]+\?\?\?\? 670F1B44 bndstx %bnd0, 0x3\(%eax,%ebx,1\)
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*29[ ]+1803
-[ ]*30[ ]+\?\?\?\? 670F1B53 bndstx %bnd2, 3\(%ebx,1\)
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-\fGAS LISTING .*
-
-
-[ ]*30[ ]+03
-[ ]*31[ ]+
-[ ]*32[ ]+\#\#\# bndldx
-[ ]*33[ ]+\?\?\?\? 670F1A44 bndldx 0x3\(%eax,%ebx,1\), %bnd0
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*33[ ]+1803
-[ ]*34[ ]+\?\?\?\? 670F1A53 bndldx 3\(%ebx,1\), %bnd2
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*34[ ]+03
-[ ]*35[ ]+
-[ ]*36[ ]+\.intel_syntax noprefix
-[ ]*37[ ]+\?\?\?\? 67F30F1B bndmk bnd1, \[eax\]
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*37[ ]+08
-[ ]*38[ ]+\?\?\?\? 67F30F1B bndmk bnd1, \[edx\+1\*eax\+0x3\]
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*38[ ]+4C0203
-[ ]*39[ ]+
-[ ]*40[ ]+\#\#\# bndmov
-[ ]*41[ ]+\?\?\?\? 67660F1A bndmov bnd1, \[eax\]
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*41[ ]+08
-[ ]*42[ ]+\?\?\?\? 67660F1A bndmov bnd1, \[edx\+1\*eax\+0x3\]
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*42[ ]+4C0203
-[ ]*43[ ]+
-[ ]*44[ ]+\?\?\?\? 67660F1B bndmov \[eax\], bnd1
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*44[ ]+08
-[ ]*45[ ]+\?\?\?\? 67660F1B bndmov \[edx\+1\*eax\+0x3\], bnd1
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*45[ ]+4C0203
-[ ]*46[ ]+
-[ ]*47[ ]+\#\#\# bndcl
-[ ]*48[ ]+\?\?\?\? 67F30F1A bndcl bnd1, \[eax\]
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*48[ ]+08
-[ ]*49[ ]+\?\?\?\? 67F30F1A bndcl bnd1, \[edx\+1\*eax\+0x3\]
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*49[ ]+4C0203
-[ ]*50[ ]+
-[ ]*51[ ]+\#\#\# bndcu
-[ ]*52[ ]+\?\?\?\? 67F20F1A bndcu bnd1, \[eax\]
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*52[ ]+08
-[ ]*53[ ]+\?\?\?\? 67F20F1A bndcu bnd1, \[edx\+1\*eax\+0x3\]
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*53[ ]+4C0203
-[ ]*54[ ]+
-[ ]*55[ ]+\#\#\# bndcn
-[ ]*56[ ]+\?\?\?\? 67F20F1B bndcn bnd1, \[eax\]
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*56[ ]+08
-[ ]*57[ ]+\?\?\?\? 67F20F1B bndcn bnd1, \[edx\+1\*eax\+0x3\]
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*57[ ]+4C0203
-[ ]*58[ ]+
-\fGAS LISTING .*
-
-
-[ ]*59[ ]+\#\#\# bndstx
-[ ]*60[ ]+\?\?\?\? 670F1B44 bndstx \[eax\+ebx\*1\+0x3\], bnd0
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*60[ ]+1803
-[ ]*61[ ]+\?\?\?\? 670F1B14 bndstx \[1\*ebx\+3\], bnd2
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*61[ ]+1D030000
-[ ]*61[ ]+00
-[ ]*62[ ]+
-[ ]*63[ ]+\#\#\# bndldx
-[ ]*64[ ]+\?\?\?\? 670F1A44 bndldx bnd0, \[eax\+ebx\*1\+0x3\]
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*64[ ]+1803
-[ ]*65[ ]+\?\?\?\? 670F1A14 bndldx bnd2, \[1\*ebx\+3\]
-\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*65[ ]+1D030000
-[ ]*65[ ]+00
+#...
+[ ]*[1-9][0-9]*[ ]+\#\#\# bndmk
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F30F1B bndmk \(%eax\), %bnd1
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F30F1B bndmk 0x3\(%ecx,%ebx,1\), %bnd1
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+bndmk \(%rip\), %bnd3
+#...
+[ ]*[1-9][0-9]*[ ]+\#\#\# bndmov
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 6766410F bndmov \(%r8d\), %bnd1
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 6766410F bndmov 0x3\(%r9d,%edx,1\), %bnd1
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67660F1B bndmov %bnd1, \(%eax\)
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67660F1B bndmov %bnd1, 0x3\(%ecx,%eax,1\)
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\#\#\# bndcl
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F30F1A bndcl \(%ecx\), %bnd1
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F30F1A bndcl 0x3\(%ecx,%eax,1\), %bnd1
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? F30F1AC9 bndcl %ecx, %bnd1
+\*\*\*\* Warning:using `%rcx' instead of `%ecx' for `bndcl'
+#...
+[ ]*[1-9][0-9]*[ ]+\#\#\# bndcu
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F20F1A bndcu \(%ecx\), %bnd1
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F20F1A bndcu 0x3\(%ecx,%eax,1\), %bnd1
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? F20F1AC9 bndcu %ecx, %bnd1
+\*\*\*\* Warning:using `%rcx' instead of `%ecx' for `bndcu'
+#...
+[ ]*[1-9][0-9]*[ ]+\#\#\# bndcn
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F20F1B bndcn \(%ecx\), %bnd1
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F20F1B bndcn 0x3\(%ecx,%eax,1\), %bnd1
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? F20F1BC9 bndcn %ecx, %bnd1
+\*\*\*\* Warning:using `%rcx' instead of `%ecx' for `bndcn'
+#...
+[ ]*[1-9][0-9]*[ ]+\#\#\# bndstx
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 670F1B44 bndstx %bnd0, 0x3\(%eax,%ebx,1\)
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 670F1B53 bndstx %bnd2, 3\(%ebx,1\)
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 410F1B0C bndstx %bnd1, \(%r15,%rax,2\)
+\*\*\*\* Warning:register scaling is being ignored here
+#...
+[ ]*[1-9][0-9]*[ ]+bndstx %bnd3, base\(%rip\)
+#...
+[ ]*[1-9][0-9]*[ ]+\#\#\# bndldx
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 670F1A44 bndldx 0x3\(%eax,%ebx,1\), %bnd0
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 670F1A53 bndldx 3\(%ebx,1\), %bnd2
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 420F1A1C bndldx \(%rax,%r15,4\), %bnd3
+\*\*\*\* Warning:register scaling is being ignored here
+#...
+[ ]*[1-9][0-9]*[ ]+bndldx base\(%rip\), %bnd1
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F30F1B bndmk bnd1, \[eax\]
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F30F1B bndmk bnd1, \[edx\+1\*eax\+0x3\]
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+bndmk bnd3, \[rip\]
+[ ]*[1-9][0-9]*[ ]+bndmk bnd2, \[rax\+rsp\]
+#...
+[ ]*[1-9][0-9]*[ ]+\#\#\# bndmov
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67660F1A bndmov bnd1, \[eax\]
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67660F1A bndmov bnd1, \[edx\+1\*eax\+0x3\]
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67660F1B bndmov \[eax\], bnd1
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67660F1B bndmov \[edx\+1\*eax\+0x3\], bnd1
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\#\#\# bndcl
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F30F1A bndcl bnd1, \[eax\]
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F30F1A bndcl bnd1, \[edx\+1\*eax\+0x3\]
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? F30F1AC8 bndcl bnd1, eax
+\*\*\*\* Warning:using `rax' instead of `eax' for `bndcl'
+#...
+[ ]*[1-9][0-9]*[ ]+\#\#\# bndcu
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F20F1A bndcu bnd1, \[eax\]
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F20F1A bndcu bnd1, \[edx\+1\*eax\+0x3\]
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? F20F1AC8 bndcu bnd1, eax
+\*\*\*\* Warning:using `rax' instead of `eax' for `bndcu'
+#...
+[ ]*[1-9][0-9]*[ ]+\#\#\# bndcn
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F20F1B bndcn bnd1, \[eax\]
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F20F1B bndcn bnd1, \[edx\+1\*eax\+0x3\]
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? F20F1BC8 bndcn bnd1, eax
+\*\*\*\* Warning:using `rax' instead of `eax' for `bndcn'
+#...
+[ ]*[1-9][0-9]*[ ]+\#\#\# bndstx
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 670F1B44 bndstx \[eax\+ebx\*1\+0x3\], bnd0
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 670F1B14 bndstx \[1\*ebx\+3\], bnd2
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 410F1B14 bndstx \[r8\+rdi\*4\], bnd2
+\*\*\*\* Warning:register scaling is being ignored here
+#...
+[ ]*[1-9][0-9]*[ ]+bndstx \[rip\+base\], bnd1
+[ ]*[1-9][0-9]*[ ]+bndstx \[rax\+rsp\], bnd3
+#...
+[ ]*[1-9][0-9]*[ ]+\#\#\# bndldx
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 670F1A44 bndldx bnd0, \[eax\+ebx\*1\+0x3\]
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 670F1A14 bndldx bnd2, \[1\*ebx\+3\]
+\*\*\*\* Warning:32-bit addressing is ignored in 64-bit MPX instructions
+#...
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 420F1A14 bndldx bnd2, \[rdi\+r8\*8\]
+\*\*\*\* Warning:register scaling is being ignored here
+#...
+[ ]*[1-9][0-9]*[ ]+bndldx bnd1, \[rip\+base\]
+[ ]*[1-9][0-9]*[ ]+bndldx bnd3, \[rax\+rsp\]
--- 2013-10-07/gas/testsuite/gas/i386/x86-64-mpx-inval-2.s
+++ 2013-10-07/gas/testsuite/gas/i386/x86-64-mpx-inval-2.s
@@ -5,6 +5,7 @@
### bndmk
bndmk (%eax), %bnd1
bndmk 0x3(%ecx,%ebx,1), %bnd1
+ bndmk (%rip), %bnd3
### bndmov
bndmov (%r8d), %bnd1
@@ -16,26 +17,38 @@
### bndcl
bndcl (%ecx), %bnd1
bndcl 0x3(%ecx,%eax,1), %bnd1
+ bndcl %ecx, %bnd1
+ bndcl %cx, %bnd1
### bndcu
bndcu (%ecx), %bnd1
bndcu 0x3(%ecx,%eax,1), %bnd1
+ bndcu %ecx, %bnd1
+ bndcu %cx, %bnd1
### bndcn
bndcn (%ecx), %bnd1
bndcn 0x3(%ecx,%eax,1), %bnd1
+ bndcn %ecx, %bnd1
+ bndcn %cx, %bnd1
### bndstx
bndstx %bnd0, 0x3(%eax,%ebx,1)
bndstx %bnd2, 3(%ebx,1)
+ bndstx %bnd1, (%r15,%rax,2)
+ bndstx %bnd3, base(%rip)
### bndldx
bndldx 0x3(%eax,%ebx,1), %bnd0
bndldx 3(%ebx,1), %bnd2
+ bndldx (%rax,%r15,4), %bnd3
+ bndldx base(%rip), %bnd1
.intel_syntax noprefix
bndmk bnd1, [eax]
bndmk bnd1, [edx+1*eax+0x3]
+ bndmk bnd3, [rip]
+ bndmk bnd2, [rax+rsp]
### bndmov
bndmov bnd1, [eax]
@@ -47,19 +60,31 @@
### bndcl
bndcl bnd1, [eax]
bndcl bnd1, [edx+1*eax+0x3]
+ bndcl bnd1, eax
+ bndcl bnd1, dx
### bndcu
bndcu bnd1, [eax]
bndcu bnd1, [edx+1*eax+0x3]
+ bndcu bnd1, eax
+ bndcu bnd1, dx
### bndcn
bndcn bnd1, [eax]
bndcn bnd1, [edx+1*eax+0x3]
+ bndcn bnd1, eax
+ bndcn bnd1, dx
### bndstx
bndstx [eax+ebx*1+0x3], bnd0
bndstx [1*ebx+3], bnd2
+ bndstx [r8+rdi*4], bnd2
+ bndstx [rip+base], bnd1
+ bndstx [rax+rsp], bnd3
### bndldx
bndldx bnd0, [eax+ebx*1+0x3]
bndldx bnd2, [1*ebx+3]
+ bndldx bnd2, [rdi+r8*8]
+ bndldx bnd1, [rip+base]
+ bndldx bnd3, [rax+rsp]
--- 2013-10-07/gas/testsuite/gas/i386/x86-64-mpx.d
+++ 2013-10-07/gas/testsuite/gas/i386/x86-64-mpx.d
@@ -6,7 +6,7 @@
Disassembly of section .text:
-0+ <foo-0x434>:
+0+ <foo-0x[0-9a-f]+>:
[ ]*[a-f0-9]+: f3 41 0f 1b 0b bndmk \(%r11\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1b 08 bndmk \(%rax\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1b 0c 25 99 03 00 00 bndmk 0x399,%bnd1
@@ -38,9 +38,8 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 0f 1a d0 bndmov %bnd0,%bnd2
[ ]*[a-f0-9]+: f3 41 0f 1a 0b bndcl \(%r11\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1a 08 bndcl \(%rax\),%bnd1
-[ ]*[a-f0-9]+: f3 49 0f 1a cb bndcl %r11,%bnd1
-[ ]*[a-f0-9]+: f3 48 0f 1a c9 bndcl %rcx,%bnd1
-[ ]*[a-f0-9]+: f3 0f 1a c8 bndcl %eax,%bnd1
+[ ]*[a-f0-9]+: f3 41 0f 1a cb bndcl %r11,%bnd1
+[ ]*[a-f0-9]+: f3 0f 1a c9 bndcl %rcx,%bnd1
[ ]*[a-f0-9]+: f3 0f 1a 0c 25 99 03 00 00 bndcl 0x399,%bnd1
[ ]*[a-f0-9]+: f3 41 0f 1a 51 03 bndcl 0x3\(%r9\),%bnd2
[ ]*[a-f0-9]+: f3 0f 1a 50 03 bndcl 0x3\(%rax\),%bnd2
@@ -50,9 +49,8 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: f3 42 0f 1a 4c 0b 03 bndcl 0x3\(%rbx,%r9,1\),%bnd1
[ ]*[a-f0-9]+: f2 41 0f 1a 0b bndcu \(%r11\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1a 08 bndcu \(%rax\),%bnd1
-[ ]*[a-f0-9]+: f2 49 0f 1a cb bndcu %r11,%bnd1
-[ ]*[a-f0-9]+: f2 48 0f 1a c9 bndcu %rcx,%bnd1
-[ ]*[a-f0-9]+: f2 0f 1a c8 bndcu %eax,%bnd1
+[ ]*[a-f0-9]+: f2 41 0f 1a cb bndcu %r11,%bnd1
+[ ]*[a-f0-9]+: f2 0f 1a c9 bndcu %rcx,%bnd1
[ ]*[a-f0-9]+: f2 0f 1a 0c 25 99 03 00 00 bndcu 0x399,%bnd1
[ ]*[a-f0-9]+: f2 41 0f 1a 51 03 bndcu 0x3\(%r9\),%bnd2
[ ]*[a-f0-9]+: f2 0f 1a 50 03 bndcu 0x3\(%rax\),%bnd2
@@ -62,9 +60,8 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: f2 42 0f 1a 4c 0b 03 bndcu 0x3\(%rbx,%r9,1\),%bnd1
[ ]*[a-f0-9]+: f2 41 0f 1b 0b bndcn \(%r11\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1b 08 bndcn \(%rax\),%bnd1
-[ ]*[a-f0-9]+: f2 49 0f 1b cb bndcn %r11,%bnd1
-[ ]*[a-f0-9]+: f2 48 0f 1b c9 bndcn %rcx,%bnd1
-[ ]*[a-f0-9]+: f2 0f 1b c8 bndcn %eax,%bnd1
+[ ]*[a-f0-9]+: f2 41 0f 1b cb bndcn %r11,%bnd1
+[ ]*[a-f0-9]+: f2 0f 1b c9 bndcn %rcx,%bnd1
[ ]*[a-f0-9]+: f2 0f 1b 0c 25 99 03 00 00 bndcn 0x399,%bnd1
[ ]*[a-f0-9]+: f2 41 0f 1b 51 03 bndcn 0x3\(%r9\),%bnd2
[ ]*[a-f0-9]+: f2 0f 1b 50 03 bndcn 0x3\(%rax\),%bnd2
@@ -88,11 +85,11 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f 1a 14 1d 03 00 00 00 bndldx 0x3\(,%rbx,1\),%bnd2
[ ]*[a-f0-9]+: 42 0f 1a 14 25 03 00 00 00 bndldx 0x3\(,%r12,1\),%bnd2
[ ]*[a-f0-9]+: 0f 1a 0a bndldx \(%rdx\),%bnd1
-[ ]*[a-f0-9]+: f2 e8 34 02 00 00 bnd callq 434 <foo>
+[ ]*[a-f0-9]+: f2 e8 .. .. 00 00 bnd callq [0-9a-f]+ <foo>
[ ]*[a-f0-9]+: f2 ff 10 bnd callq \*\(%rax\)
[ ]*[a-f0-9]+: f2 41 ff 13 bnd callq \*\(%r11\)
-[ ]*[a-f0-9]+: f2 0f 84 26 02 00 00 bnd je 434 <foo>
-[ ]*[a-f0-9]+: f2 e9 20 02 00 00 bnd jmpq 434 <foo>
+[ ]*[a-f0-9]+: f2 0f 84 .. .. 00 00 bnd je [0-9a-f]+ <foo>
+[ ]*[a-f0-9]+: f2 e9 .. .. 00 00 bnd jmpq [0-9a-f]+ <foo>
[ ]*[a-f0-9]+: f2 ff 21 bnd jmpq \*\(%rcx\)
[ ]*[a-f0-9]+: f2 41 ff 24 24 bnd jmpq \*\(%r12\)
[ ]*[a-f0-9]+: f2 c3 bnd retq
@@ -127,9 +124,8 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 0f 1a d0 bndmov %bnd0,%bnd2
[ ]*[a-f0-9]+: f3 41 0f 1a 0b bndcl \(%r11\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1a 08 bndcl \(%rax\),%bnd1
-[ ]*[a-f0-9]+: f3 49 0f 1a cb bndcl %r11,%bnd1
-[ ]*[a-f0-9]+: f3 48 0f 1a c9 bndcl %rcx,%bnd1
-[ ]*[a-f0-9]+: f3 0f 1a c8 bndcl %eax,%bnd1
+[ ]*[a-f0-9]+: f3 41 0f 1a cb bndcl %r11,%bnd1
+[ ]*[a-f0-9]+: f3 0f 1a c9 bndcl %rcx,%bnd1
[ ]*[a-f0-9]+: f3 0f 1a 0c 25 99 03 00 00 bndcl 0x399,%bnd1
[ ]*[a-f0-9]+: f3 41 0f 1a 49 03 bndcl 0x3\(%r9\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1a 48 03 bndcl 0x3\(%rax\),%bnd1
@@ -139,9 +135,8 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: f3 42 0f 1a 4c 0b 03 bndcl 0x3\(%rbx,%r9,1\),%bnd1
[ ]*[a-f0-9]+: f2 41 0f 1a 0b bndcu \(%r11\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1a 08 bndcu \(%rax\),%bnd1
-[ ]*[a-f0-9]+: f2 49 0f 1a cb bndcu %r11,%bnd1
-[ ]*[a-f0-9]+: f2 48 0f 1a c9 bndcu %rcx,%bnd1
-[ ]*[a-f0-9]+: f2 0f 1a c8 bndcu %eax,%bnd1
+[ ]*[a-f0-9]+: f2 41 0f 1a cb bndcu %r11,%bnd1
+[ ]*[a-f0-9]+: f2 0f 1a c9 bndcu %rcx,%bnd1
[ ]*[a-f0-9]+: f2 0f 1a 0c 25 99 03 00 00 bndcu 0x399,%bnd1
[ ]*[a-f0-9]+: f2 41 0f 1a 49 03 bndcu 0x3\(%r9\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1a 48 03 bndcu 0x3\(%rax\),%bnd1
@@ -151,9 +146,8 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: f2 42 0f 1a 4c 0b 03 bndcu 0x3\(%rbx,%r9,1\),%bnd1
[ ]*[a-f0-9]+: f2 41 0f 1b 0b bndcn \(%r11\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1b 08 bndcn \(%rax\),%bnd1
-[ ]*[a-f0-9]+: f2 49 0f 1b cb bndcn %r11,%bnd1
-[ ]*[a-f0-9]+: f2 48 0f 1b c9 bndcn %rcx,%bnd1
-[ ]*[a-f0-9]+: f2 0f 1b c8 bndcn %eax,%bnd1
+[ ]*[a-f0-9]+: f2 41 0f 1b cb bndcn %r11,%bnd1
+[ ]*[a-f0-9]+: f2 0f 1b c9 bndcn %rcx,%bnd1
[ ]*[a-f0-9]+: f2 0f 1b 0c 25 99 03 00 00 bndcn 0x399,%bnd1
[ ]*[a-f0-9]+: f2 41 0f 1b 49 03 bndcn 0x3\(%r9\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1b 48 03 bndcn 0x3\(%rax\),%bnd1
@@ -177,15 +171,15 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f 1a 14 1d 03 00 00 00 bndldx 0x3\(,%rbx,1\),%bnd2
[ ]*[a-f0-9]+: 42 0f 1a 14 25 03 00 00 00 bndldx 0x3\(,%r12,1\),%bnd2
[ ]*[a-f0-9]+: 0f 1a 0a bndldx \(%rdx\),%bnd1
-[ ]*[a-f0-9]+: f2 e8 16 00 00 00 bnd callq 434 <foo>
+[ ]*[a-f0-9]+: f2 e8 .. 00 00 00 bnd callq [0-9a-f]+ <foo>
[ ]*[a-f0-9]+: f2 ff d0 bnd callq \*%rax
[ ]*[a-f0-9]+: f2 41 ff d3 bnd callq \*%r11
-[ ]*[a-f0-9]+: f2 74 0c bnd je 434 <foo>
-[ ]*[a-f0-9]+: f2 eb 09 bnd jmp 434 <foo>
+[ ]*[a-f0-9]+: f2 74 .. bnd je [0-9a-f]+ <foo>
+[ ]*[a-f0-9]+: f2 eb .. bnd jmp [0-9a-f]+ <foo>
[ ]*[a-f0-9]+: f2 ff e1 bnd jmpq \*%rcx
[ ]*[a-f0-9]+: f2 41 ff e4 bnd jmpq \*%r12
[ ]*[a-f0-9]+: f2 c3 bnd retq
-0+434 <foo>:
+[0-9a-f]+ <foo>:
[ ]*[a-f0-9]+: f2 c3 bnd retq
#pass
--- 2013-10-07/gas/testsuite/gas/i386/x86-64-mpx.s
+++ 2013-10-07/gas/testsuite/gas/i386/x86-64-mpx.s
@@ -41,7 +41,6 @@
bndcl (%rax), %bnd1
bndcl %r11, %bnd1
bndcl %rcx, %bnd1
- bndcl %ax, %bnd1
bndcl (0x399), %bnd1
bndcl 0x3(%r9), %bnd2
bndcl 0x3(%rax), %bnd2
@@ -55,7 +54,6 @@
bndcu (%rax), %bnd1
bndcu %r11, %bnd1
bndcu %rcx, %bnd1
- bndcu %ax, %bnd1
bndcu (0x399), %bnd1
bndcu 0x3(%r9), %bnd2
bndcu 0x3(%rax), %bnd2
@@ -69,7 +67,6 @@
bndcn (%rax), %bnd1
bndcn %r11, %bnd1
bndcn %rcx, %bnd1
- bndcn %ax, %bnd1
bndcn (0x399), %bnd1
bndcn 0x3(%r9), %bnd2
bndcn 0x3(%rax), %bnd2
@@ -147,7 +144,6 @@
bndcl bnd1, [rax]
bndcl bnd1, r11
bndcl bnd1, rcx
- bndcl bnd1, ax
bndcl bnd1, [0x399]
bndcl bnd1, [r9+0x3]
bndcl bnd1, [rax+0x3]
@@ -161,7 +157,6 @@
bndcu bnd1, [rax]
bndcu bnd1, r11
bndcu bnd1, rcx
- bndcu bnd1, ax
bndcu bnd1, [0x399]
bndcu bnd1, [r9+0x3]
bndcu bnd1, [rax+0x3]
@@ -175,7 +170,6 @@
bndcn bnd1, [rax]
bndcn bnd1, r11
bndcn bnd1, rcx
- bndcn bnd1, ax
bndcn bnd1, [0x399]
bndcn bnd1, [r9+0x3]
bndcn bnd1, [rax+0x3]
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 2/6] x86/MPX: fix address size handling
2013-10-08 14:36 [PATCH 0/6] x86: various MPX fixes Jan Beulich
@ 2013-10-08 14:41 ` Jan Beulich
2013-10-08 15:15 ` H.J. Lu
2013-10-08 14:41 ` [PATCH 1/6] x86/MPX: testsuite adjustments Jan Beulich
` (4 subsequent siblings)
5 siblings, 1 reply; 33+ messages in thread
From: Jan Beulich @ 2013-10-08 14:41 UTC (permalink / raw)
To: H.J. Lu; +Cc: kirill.yukhin, binutils
[-- Attachment #1: Type: text/plain, Size: 1243 bytes --]
While address overrides are ignored in 64-bit mode (and hence shouldn't
result in an error), trying to use 16-bit addressing is documented to
result in #UD, and hence the assembler should reject the attempt.
gas/
2013-10-08 Jan Beulich <jbeulich@suse.com>
* tc-i386.c (md_assemble): Alter address size checking for MPX
instructions.
--- 2013-10-07/gas/config/tc-i386.c
+++ 2013-10-07/gas/config/tc-i386.c
@@ -3549,10 +3549,15 @@ md_assemble (char *line)
if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
as_bad (_("expecting valid branch instruction after `bnd'"));
- if (i.tm.cpu_flags.bitfield.cpumpx
- && flag_code == CODE_64BIT
- && i.prefix[ADDR_PREFIX])
- as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
+ if (i.tm.cpu_flags.bitfield.cpumpx)
+ {
+ if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
+ as_warn (_("32-bit addressing is ignored in 64-bit MPX instructions"));
+ else if (flag_code != CODE_16BIT
+ ? i.prefix[ADDR_PREFIX]
+ : i.mem_operands && !i.prefix[ADDR_PREFIX])
+ as_bad (_("16-bit addressing isn't allowed in MPX instructions"));
+ }
/* Insert BND prefix. */
if (add_bnd_prefix
[-- Attachment #2: binutils-mainline-x86-MPX-address-size.patch --]
[-- Type: text/plain, Size: 1237 bytes --]
While address overrides are ignored in 64-bit mode (and hence shouldn't
result in an error), trying to use 16-bit addressing is documented to
result in #UD, and hence the assembler should reject the attempt.
gas/
2013-10-08 Jan Beulich <jbeulich@suse.com>
* tc-i386.c (md_assemble): Alter address size checking for MPX
instructions.
--- 2013-10-07/gas/config/tc-i386.c
+++ 2013-10-07/gas/config/tc-i386.c
@@ -3549,10 +3549,15 @@ md_assemble (char *line)
if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
as_bad (_("expecting valid branch instruction after `bnd'"));
- if (i.tm.cpu_flags.bitfield.cpumpx
- && flag_code == CODE_64BIT
- && i.prefix[ADDR_PREFIX])
- as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
+ if (i.tm.cpu_flags.bitfield.cpumpx)
+ {
+ if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
+ as_warn (_("32-bit addressing is ignored in 64-bit MPX instructions"));
+ else if (flag_code != CODE_16BIT
+ ? i.prefix[ADDR_PREFIX]
+ : i.mem_operands && !i.prefix[ADDR_PREFIX])
+ as_bad (_("16-bit addressing isn't allowed in MPX instructions"));
+ }
/* Insert BND prefix. */
if (add_bnd_prefix
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 3/6] x86/MPX: suppress base/index swapping in Intel mode for bndmk, bndldx, and bndstx
2013-10-08 14:36 [PATCH 0/6] x86: various MPX fixes Jan Beulich
2013-10-08 14:41 ` [PATCH 2/6] x86/MPX: fix address size handling Jan Beulich
2013-10-08 14:41 ` [PATCH 1/6] x86/MPX: testsuite adjustments Jan Beulich
@ 2013-10-08 14:42 ` Jan Beulich
2013-10-08 15:16 ` H.J. Lu
2013-10-08 14:43 ` [PATCH 5/6] x86/MPX: fix operand size handling Jan Beulich
` (2 subsequent siblings)
5 siblings, 1 reply; 33+ messages in thread
From: Jan Beulich @ 2013-10-08 14:42 UTC (permalink / raw)
To: H.J. Lu; +Cc: kirill.yukhin, binutils
[-- Attachment #1: Type: text/plain, Size: 820 bytes --]
bndmk, bndldx, and bndstx assign special meaning to base and index
registers, and hence silently swapping the registers should be
suppressed.
gas/
2013-10-08 Jan Beulich <jbeulich@suse.com>
* tc-i386.c (i386_intel_simplify_register): Suppress base/index
swapping for bndmk, bndldx, and bndstx.
--- 2013-10-07/gas/config/tc-i386-intel.c
+++ 2013-10-07/gas/config/tc-i386-intel.c
@@ -291,6 +291,8 @@ i386_intel_simplify_register (expression
else if (!intel_state.index)
{
if (intel_state.in_scale
+ || current_templates->start->base_opcode == 0xf30f1b /* bndmk */
+ || (current_templates->start->base_opcode & ~1) == 0x0f1a /* bnd{ld,st}x */
|| i386_regtab[reg_num].reg_type.bitfield.baseindex)
intel_state.index = i386_regtab + reg_num;
else
[-- Attachment #2: binutils-mainline-x86-MPX-intel-no-swap.patch --]
[-- Type: text/plain, Size: 814 bytes --]
bndmk, bndldx, and bndstx assign special meaning to base and index
registers, and hence silently swapping the registers should be
suppressed.
gas/
2013-10-08 Jan Beulich <jbeulich@suse.com>
* tc-i386.c (i386_intel_simplify_register): Suppress base/index
swapping for bndmk, bndldx, and bndstx.
--- 2013-10-07/gas/config/tc-i386-intel.c
+++ 2013-10-07/gas/config/tc-i386-intel.c
@@ -291,6 +291,8 @@ i386_intel_simplify_register (expression
else if (!intel_state.index)
{
if (intel_state.in_scale
+ || current_templates->start->base_opcode == 0xf30f1b /* bndmk */
+ || (current_templates->start->base_opcode & ~1) == 0x0f1a /* bnd{ld,st}x */
|| i386_regtab[reg_num].reg_type.bitfield.baseindex)
intel_state.index = i386_regtab + reg_num;
else
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 4/6] x86/MPX: bndmk, bndldx, and bndstx only allow a memory operand
2013-10-08 14:36 [PATCH 0/6] x86: various MPX fixes Jan Beulich
` (3 preceding siblings ...)
2013-10-08 14:43 ` [PATCH 5/6] x86/MPX: fix operand size handling Jan Beulich
@ 2013-10-08 14:43 ` Jan Beulich
2013-10-08 15:28 ` H.J. Lu
2013-10-08 14:44 ` [PATCH 6/6] x86/MPX: bndmk, bndldx, and bndstx don't allow RIP-relative addressing Jan Beulich
5 siblings, 1 reply; 33+ messages in thread
From: Jan Beulich @ 2013-10-08 14:43 UTC (permalink / raw)
To: H.J. Lu; +Cc: kirill.yukhin, binutils
[-- Attachment #1: Type: text/plain, Size: 1184 bytes --]
bndmk, bndldx, and bndstx only allow memory operands, so decoding should
use OP_M() instead of OP_E().
opcodes/
2013-10-08 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (Mv_bnd): New.
(mod_table): Use it for bndmk, bndldx, and bndstx.
--- 2013-10-07/opcodes/i386-dis.c
+++ 2013-10-07/opcodes/i386-dis.c
@@ -250,6 +250,7 @@ fetch_data (struct disassemble_info *inf
#define Mo { OP_M, o_mode }
#define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
#define Mq { OP_M, q_mode }
+#define Mv_bnd { OP_M, v_bnd_mode }
#define Mx { OP_M, x_mode }
#define Mxmm { OP_M, xmm_mode }
#define Gb { OP_G, b_mode }
@@ -11126,17 +11127,17 @@ static const struct dis386 mod_table[][2
},
{
/* MOD_0F1A_PREFIX_0 */
- { "bndldx", { Gbnd, Ev_bnd } },
+ { "bndldx", { Gbnd, Mv_bnd } },
{ "nopQ", { Ev } },
},
{
/* MOD_0F1B_PREFIX_0 */
- { "bndstx", { Ev_bnd, Gbnd } },
+ { "bndstx", { Mv_bnd, Gbnd } },
{ "nopQ", { Ev } },
},
{
/* MOD_0F1B_PREFIX_1 */
- { "bndmk", { Gbnd, Ev_bnd } },
+ { "bndmk", { Gbnd, Mv_bnd } },
{ "nopQ", { Ev } },
},
{
[-- Attachment #2: binutils-mainline-x86-MPX-no-reg.patch --]
[-- Type: text/plain, Size: 1178 bytes --]
bndmk, bndldx, and bndstx only allow memory operands, so decoding should
use OP_M() instead of OP_E().
opcodes/
2013-10-08 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (Mv_bnd): New.
(mod_table): Use it for bndmk, bndldx, and bndstx.
--- 2013-10-07/opcodes/i386-dis.c
+++ 2013-10-07/opcodes/i386-dis.c
@@ -250,6 +250,7 @@ fetch_data (struct disassemble_info *inf
#define Mo { OP_M, o_mode }
#define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
#define Mq { OP_M, q_mode }
+#define Mv_bnd { OP_M, v_bnd_mode }
#define Mx { OP_M, x_mode }
#define Mxmm { OP_M, xmm_mode }
#define Gb { OP_G, b_mode }
@@ -11126,17 +11127,17 @@ static const struct dis386 mod_table[][2
},
{
/* MOD_0F1A_PREFIX_0 */
- { "bndldx", { Gbnd, Ev_bnd } },
+ { "bndldx", { Gbnd, Mv_bnd } },
{ "nopQ", { Ev } },
},
{
/* MOD_0F1B_PREFIX_0 */
- { "bndstx", { Ev_bnd, Gbnd } },
+ { "bndstx", { Mv_bnd, Gbnd } },
{ "nopQ", { Ev } },
},
{
/* MOD_0F1B_PREFIX_1 */
- { "bndmk", { Gbnd, Ev_bnd } },
+ { "bndmk", { Gbnd, Mv_bnd } },
{ "nopQ", { Ev } },
},
{
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 5/6] x86/MPX: fix operand size handling
2013-10-08 14:36 [PATCH 0/6] x86: various MPX fixes Jan Beulich
` (2 preceding siblings ...)
2013-10-08 14:42 ` [PATCH 3/6] x86/MPX: suppress base/index swapping in Intel mode for bndmk, bndldx, and bndstx Jan Beulich
@ 2013-10-08 14:43 ` Jan Beulich
2013-10-08 15:45 ` H.J. Lu
2013-10-08 14:43 ` [PATCH 4/6] x86/MPX: bndmk, bndldx, and bndstx only allow a memory operand Jan Beulich
2013-10-08 14:44 ` [PATCH 6/6] x86/MPX: bndmk, bndldx, and bndstx don't allow RIP-relative addressing Jan Beulich
5 siblings, 1 reply; 33+ messages in thread
From: Jan Beulich @ 2013-10-08 14:43 UTC (permalink / raw)
To: H.J. Lu; +Cc: kirill.yukhin, binutils
[-- Attachment #1: Type: text/plain, Size: 5069 bytes --]
All MPX instructions in 64-bit mode ignore REX.W, which means we neither
need to encode this bit nor should disassemble with 32-bit register
operands.
No MPX instructions would ever take a 16-bit register operand.
gas/
2013-10-08 Jan Beulich <jbeulich@suse.com>
* tc-i386.c (process_suffix): Warn about 32-bit register operands
to MPX instructions in 64-bit mode.
opcodes/
2013-10-08 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (intel_operand_size): Move v_bnd_mode alongside the
default case.
(OP_E_register): Move v_bnd_mode alongside m_mode.
* i386-opc.h (REGNAM_RAX): New.
* i386-opc.tbl (bndcl, bndcu, bndcn): Drop Reg16. Add NoRex64.
* i386-tbl.h: Re-generate.
--- 2013-10-07/gas/config/tc-i386.c
+++ 2013-10-07/gas/config/tc-i386.c
@@ -5073,8 +5078,24 @@ process_suffix (void)
{
/* We take i.suffix from the last register operand specified,
Destination register type is more significant than source
- register type. crc32 in SSE4.2 prefers source register
- type. */
+ register type. */
+
+ /* MPX instructions need no suffix, but may need a warning. */
+ if (i.tm.cpu_flags.bitfield.cpumpx)
+ {
+#if REGISTER_WARNINGS
+ if (flag_code == CODE_64BIT && !quiet_warnings
+ && i.tm.operand_types[0].bitfield.reg64
+ && i.types[0].bitfield.reg32)
+ as_warn (_("using `%s%s' instead of `%s%s' for `%s'"),
+ register_prefix,
+ (i.op[0].regs + REGNAM_RAX - REGNAM_EAX)->reg_name,
+ register_prefix, i.op[0].regs->reg_name, i.tm.name);
+#endif
+ return 1;
+ }
+
+ /* crc32 in SSE4.2 prefers source register type. */
if (i.tm.base_opcode == 0xf20f38f1)
{
if (i.types[0].bitfield.reg16)
--- 2013-10-07/opcodes/i386-dis.c
+++ 2013-10-07/opcodes/i386-dis.c
@@ -13800,7 +13801,6 @@ intel_operand_size (int bytemode, int si
}
/* FALLTHRU */
case v_mode:
- case v_bnd_mode:
case v_swap_mode:
case dq_mode:
USED_REX (REX_W);
@@ -14082,6 +14082,7 @@ intel_operand_size (int bytemode, int si
abort ();
oappend ("WORD PTR ");
break;
+ case v_bnd_mode:
default:
break;
}
@@ -14121,6 +14122,7 @@ OP_E_register (int bytemode, int sizefla
names = names64;
break;
case m_mode:
+ case v_bnd_mode:
names = address_mode == mode_64bit ? names64 : names32;
break;
case bnd_mode:
@@ -14135,7 +14137,6 @@ OP_E_register (int bytemode, int sizefla
bytemode = v_mode;
/* FALLTHRU */
case v_mode:
- case v_bnd_mode:
case v_swap_mode:
case dq_mode:
case dqb_mode:
--- 2013-10-07/opcodes/i386-opc.h
+++ 2013-10-07/opcodes/i386-opc.h
@@ -835,6 +835,7 @@ reg_entry;
#define REGNAM_AL 1
#define REGNAM_AX 25
#define REGNAM_EAX 41
+#define REGNAM_RAX 57
extern const reg_entry i386_regtab[];
extern const unsigned int i386_regtab_size;
--- 2013-10-07/opcodes/i386-opc.tbl
+++ 2013-10-07/opcodes/i386-opc.tbl
@@ -3064,9 +3064,9 @@ bnd, 0, 0xf2, None, 1, CpuMPX, No_bSuf|N
bndmk, 2, 0xf30f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
bndmov, 2, 0x660f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegBND, RegBND }
bndmov, 2, 0x660f1b, None, 2, CpuMPX, S|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegBND, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegBND }
-bndcl, 2, 0xf30f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64|Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
-bndcu, 2, 0xf20f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64|Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
-bndcn, 2, 0xf20f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64|Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
+bndcl, 2, 0xf30f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg32|Reg64|Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
+bndcu, 2, 0xf20f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg32|Reg64|Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
+bndcn, 2, 0xf20f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg32|Reg64|Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
bndstx, 2, 0x0f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegBND, Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
bndldx, 2, 0x0f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
[-- Attachment #2: binutils-mainline-x86-MPX-operand-size.patch --]
[-- Type: text/plain, Size: 7532 bytes --]
All MPX instructions in 64-bit mode ignore REX.W, which means we neither
need to encode this bit nor should disassemble with 32-bit register
operands.
No MPX instructions would ever take a 16-bit register operand.
gas/
2013-10-08 Jan Beulich <jbeulich@suse.com>
* tc-i386.c (process_suffix): Warn about 32-bit register operands
to MPX instructions in 64-bit mode.
opcodes/
2013-10-08 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (intel_operand_size): Move v_bnd_mode alongside the
default case.
(OP_E_register): Move v_bnd_mode alongside m_mode.
* i386-opc.h (REGNAM_RAX): New.
* i386-opc.tbl (bndcl, bndcu, bndcn): Drop Reg16. Add NoRex64.
* i386-tbl.h: Re-generate.
--- 2013-10-07/gas/config/tc-i386.c
+++ 2013-10-07/gas/config/tc-i386.c
@@ -5073,8 +5078,24 @@ process_suffix (void)
{
/* We take i.suffix from the last register operand specified,
Destination register type is more significant than source
- register type. crc32 in SSE4.2 prefers source register
- type. */
+ register type. */
+
+ /* MPX instructions need no suffix, but may need a warning. */
+ if (i.tm.cpu_flags.bitfield.cpumpx)
+ {
+#if REGISTER_WARNINGS
+ if (flag_code == CODE_64BIT && !quiet_warnings
+ && i.tm.operand_types[0].bitfield.reg64
+ && i.types[0].bitfield.reg32)
+ as_warn (_("using `%s%s' instead of `%s%s' for `%s'"),
+ register_prefix,
+ (i.op[0].regs + REGNAM_RAX - REGNAM_EAX)->reg_name,
+ register_prefix, i.op[0].regs->reg_name, i.tm.name);
+#endif
+ return 1;
+ }
+
+ /* crc32 in SSE4.2 prefers source register type. */
if (i.tm.base_opcode == 0xf20f38f1)
{
if (i.types[0].bitfield.reg16)
--- 2013-10-07/opcodes/i386-dis.c
+++ 2013-10-07/opcodes/i386-dis.c
@@ -13800,7 +13801,6 @@ intel_operand_size (int bytemode, int si
}
/* FALLTHRU */
case v_mode:
- case v_bnd_mode:
case v_swap_mode:
case dq_mode:
USED_REX (REX_W);
@@ -14082,6 +14082,7 @@ intel_operand_size (int bytemode, int si
abort ();
oappend ("WORD PTR ");
break;
+ case v_bnd_mode:
default:
break;
}
@@ -14121,6 +14122,7 @@ OP_E_register (int bytemode, int sizefla
names = names64;
break;
case m_mode:
+ case v_bnd_mode:
names = address_mode == mode_64bit ? names64 : names32;
break;
case bnd_mode:
@@ -14135,7 +14137,6 @@ OP_E_register (int bytemode, int sizefla
bytemode = v_mode;
/* FALLTHRU */
case v_mode:
- case v_bnd_mode:
case v_swap_mode:
case dq_mode:
case dqb_mode:
--- 2013-10-07/opcodes/i386-opc.h
+++ 2013-10-07/opcodes/i386-opc.h
@@ -835,6 +835,7 @@ reg_entry;
#define REGNAM_AL 1
#define REGNAM_AX 25
#define REGNAM_EAX 41
+#define REGNAM_RAX 57
extern const reg_entry i386_regtab[];
extern const unsigned int i386_regtab_size;
--- 2013-10-07/opcodes/i386-opc.tbl
+++ 2013-10-07/opcodes/i386-opc.tbl
@@ -3064,9 +3064,9 @@ bnd, 0, 0xf2, None, 1, CpuMPX, No_bSuf|N
bndmk, 2, 0xf30f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
bndmov, 2, 0x660f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegBND, RegBND }
bndmov, 2, 0x660f1b, None, 2, CpuMPX, S|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegBND, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegBND }
-bndcl, 2, 0xf30f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64|Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
-bndcu, 2, 0xf20f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64|Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
-bndcn, 2, 0xf20f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64|Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
+bndcl, 2, 0xf30f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg32|Reg64|Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
+bndcu, 2, 0xf20f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg32|Reg64|Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
+bndcn, 2, 0xf20f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg32|Reg64|Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
bndstx, 2, 0x0f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegBND, Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
bndldx, 2, 0x0f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
--- 2013-10-07/opcodes/i386-tbl.h
+++ 2013-10-07/opcodes/i386-tbl.h
@@ -53915,10 +53915,10 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
- 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0 },
- { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ { { { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -53930,10 +53930,10 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
- 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0 },
- { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ { { { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -53945,10 +53945,10 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
- 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0 },
- { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ { { { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 6/6] x86/MPX: bndmk, bndldx, and bndstx don't allow RIP-relative addressing
2013-10-08 14:36 [PATCH 0/6] x86: various MPX fixes Jan Beulich
` (4 preceding siblings ...)
2013-10-08 14:43 ` [PATCH 4/6] x86/MPX: bndmk, bndldx, and bndstx only allow a memory operand Jan Beulich
@ 2013-10-08 14:44 ` Jan Beulich
2013-10-08 16:13 ` H.J. Lu
5 siblings, 1 reply; 33+ messages in thread
From: Jan Beulich @ 2013-10-08 14:44 UTC (permalink / raw)
To: H.J. Lu; +Cc: kirill.yukhin, binutils
[-- Attachment #1: Type: text/plain, Size: 1178 bytes --]
gas/
2013-10-08 Jan Beulich <jbeulich@suse.com>
* tc-i386.c (i386_index_check): Reject RIP-relative addressing for
bndmk, bndldx, and bndstx. Warn about register scaling by other
than 1 for bndldx and bndstx.
--- 2013-10-07/gas/config/tc-i386.c
+++ 2013-10-07/gas/config/tc-i386.c
@@ -8360,6 +8375,25 @@ bad_address:
|| i.index_reg->reg_num == RegEiz))
|| !i.index_reg->reg_type.bitfield.baseindex)))
goto bad_address;
+
+ /* bndmk, bndldx, and bndstx have special restrictions. */
+ if (current_templates->start->base_opcode == 0xf30f1b
+ || (current_templates->start->base_opcode & ~1) == 0x0f1a)
+ {
+ /* They cannot use RIP-relative addressing. */
+ if (i.base_reg
+ && i.base_reg->reg_num == (addr_mode == CODE_64BIT ? RegRip
+ : RegEip))
+ {
+ as_bad (_("`%s' cannot be used here"), operand_string);
+ return 0;
+ }
+
+ /* bndldx and bndstx ignore their scale factor. */
+ if (current_templates->start->base_opcode != 0xf30f1b
+ && i.log2_scale_factor)
+ as_warn (_("register scaling is being ignored here"));
+ }
}
else
{
[-- Attachment #2: binutils-mainline-x86-MPX-RIP-rel.patch --]
[-- Type: text/plain, Size: 1172 bytes --]
gas/
2013-10-08 Jan Beulich <jbeulich@suse.com>
* tc-i386.c (i386_index_check): Reject RIP-relative addressing for
bndmk, bndldx, and bndstx. Warn about register scaling by other
than 1 for bndldx and bndstx.
--- 2013-10-07/gas/config/tc-i386.c
+++ 2013-10-07/gas/config/tc-i386.c
@@ -8360,6 +8375,25 @@ bad_address:
|| i.index_reg->reg_num == RegEiz))
|| !i.index_reg->reg_type.bitfield.baseindex)))
goto bad_address;
+
+ /* bndmk, bndldx, and bndstx have special restrictions. */
+ if (current_templates->start->base_opcode == 0xf30f1b
+ || (current_templates->start->base_opcode & ~1) == 0x0f1a)
+ {
+ /* They cannot use RIP-relative addressing. */
+ if (i.base_reg
+ && i.base_reg->reg_num == (addr_mode == CODE_64BIT ? RegRip
+ : RegEip))
+ {
+ as_bad (_("`%s' cannot be used here"), operand_string);
+ return 0;
+ }
+
+ /* bndldx and bndstx ignore their scale factor. */
+ if (current_templates->start->base_opcode != 0xf30f1b
+ && i.log2_scale_factor)
+ as_warn (_("register scaling is being ignored here"));
+ }
}
else
{
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 2/6] x86/MPX: fix address size handling
2013-10-08 14:41 ` [PATCH 2/6] x86/MPX: fix address size handling Jan Beulich
@ 2013-10-08 15:15 ` H.J. Lu
2013-10-08 15:20 ` Jan Beulich
0 siblings, 1 reply; 33+ messages in thread
From: H.J. Lu @ 2013-10-08 15:15 UTC (permalink / raw)
To: Jan Beulich; +Cc: kirill.yukhin, Binutils
On Tue, Oct 8, 2013 at 7:41 AM, Jan Beulich <JBeulich@suse.com> wrote:
> While address overrides are ignored in 64-bit mode (and hence shouldn't
> result in an error), trying to use 16-bit addressing is documented to
> result in #UD, and hence the assembler should reject the attempt.
>
> gas/
> 2013-10-08 Jan Beulich <jbeulich@suse.com>
>
> * tc-i386.c (md_assemble): Alter address size checking for MPX
> instructions.
>
> --- 2013-10-07/gas/config/tc-i386.c
> +++ 2013-10-07/gas/config/tc-i386.c
> @@ -3549,10 +3549,15 @@ md_assemble (char *line)
> if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
> as_bad (_("expecting valid branch instruction after `bnd'"));
>
> - if (i.tm.cpu_flags.bitfield.cpumpx
> - && flag_code == CODE_64BIT
> - && i.prefix[ADDR_PREFIX])
> - as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
It is done on purpose. When 32-bit address prefix in 64-bit is ignored,
MPX doesn't work correctly for x32.
> + if (i.tm.cpu_flags.bitfield.cpumpx)
> + {
> + if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
> + as_warn (_("32-bit addressing is ignored in 64-bit MPX instructions"));
> + else if (flag_code != CODE_16BIT
> + ? i.prefix[ADDR_PREFIX]
> + : i.mem_operands && !i.prefix[ADDR_PREFIX])
> + as_bad (_("16-bit addressing isn't allowed in MPX instructions"));
> + }
>
> /* Insert BND prefix. */
> if (add_bnd_prefix
>
>
>
--
H.J.
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 3/6] x86/MPX: suppress base/index swapping in Intel mode for bndmk, bndldx, and bndstx
2013-10-08 14:42 ` [PATCH 3/6] x86/MPX: suppress base/index swapping in Intel mode for bndmk, bndldx, and bndstx Jan Beulich
@ 2013-10-08 15:16 ` H.J. Lu
2013-10-08 15:23 ` Jan Beulich
0 siblings, 1 reply; 33+ messages in thread
From: H.J. Lu @ 2013-10-08 15:16 UTC (permalink / raw)
To: Jan Beulich; +Cc: kirill.yukhin, Binutils
On Tue, Oct 8, 2013 at 7:42 AM, Jan Beulich <JBeulich@suse.com> wrote:
> bndmk, bndldx, and bndstx assign special meaning to base and index
> registers, and hence silently swapping the registers should be
> suppressed.
>
> gas/
> 2013-10-08 Jan Beulich <jbeulich@suse.com>
>
> * tc-i386.c (i386_intel_simplify_register): Suppress base/index
> swapping for bndmk, bndldx, and bndstx.
>
> --- 2013-10-07/gas/config/tc-i386-intel.c
> +++ 2013-10-07/gas/config/tc-i386-intel.c
> @@ -291,6 +291,8 @@ i386_intel_simplify_register (expression
> else if (!intel_state.index)
> {
> if (intel_state.in_scale
> + || current_templates->start->base_opcode == 0xf30f1b /* bndmk */
> + || (current_templates->start->base_opcode & ~1) == 0x0f1a /* bnd{ld,st}x */
> || i386_regtab[reg_num].reg_type.bitfield.baseindex)
> intel_state.index = i386_regtab + reg_num;
> else
>
>
>
We need a testcase for this.
--
H.J.
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 2/6] x86/MPX: fix address size handling
2013-10-08 15:15 ` H.J. Lu
@ 2013-10-08 15:20 ` Jan Beulich
2013-10-08 15:32 ` H.J. Lu
0 siblings, 1 reply; 33+ messages in thread
From: Jan Beulich @ 2013-10-08 15:20 UTC (permalink / raw)
To: H.J. Lu; +Cc: kirill.yukhin, Binutils
>>> On 08.10.13 at 17:15, "H.J. Lu" <hjl.tools@gmail.com> wrote:
> On Tue, Oct 8, 2013 at 7:41 AM, Jan Beulich <JBeulich@suse.com> wrote:
>> While address overrides are ignored in 64-bit mode (and hence shouldn't
>> result in an error), trying to use 16-bit addressing is documented to
>> result in #UD, and hence the assembler should reject the attempt.
>>
>> gas/
>> 2013-10-08 Jan Beulich <jbeulich@suse.com>
>>
>> * tc-i386.c (md_assemble): Alter address size checking for MPX
>> instructions.
>>
>> --- 2013-10-07/gas/config/tc-i386.c
>> +++ 2013-10-07/gas/config/tc-i386.c
>> @@ -3549,10 +3549,15 @@ md_assemble (char *line)
>> if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
>> as_bad (_("expecting valid branch instruction after `bnd'"));
>>
>> - if (i.tm.cpu_flags.bitfield.cpumpx
>> - && flag_code == CODE_64BIT
>> - && i.prefix[ADDR_PREFIX])
>> - as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
>
> It is done on purpose. When 32-bit address prefix in 64-bit is ignored,
> MPX doesn't work correctly for x32.
I don't understand: It _is_ being ignored by the hardware as per
the documentation. So x32 need to get along with that. Maybe
an example would help, so I could understand why you think
this _needs_ to be an error...
Jan
>> + if (i.tm.cpu_flags.bitfield.cpumpx)
>> + {
>> + if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
>> + as_warn (_("32-bit addressing is ignored in 64-bit MPX
> instructions"));
>> + else if (flag_code != CODE_16BIT
>> + ? i.prefix[ADDR_PREFIX]
>> + : i.mem_operands && !i.prefix[ADDR_PREFIX])
>> + as_bad (_("16-bit addressing isn't allowed in MPX instructions"));
>> + }
>>
>> /* Insert BND prefix. */
>> if (add_bnd_prefix
>>
>>
>>
>
>
>
> --
> H.J.
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 3/6] x86/MPX: suppress base/index swapping in Intel mode for bndmk, bndldx, and bndstx
2013-10-08 15:16 ` H.J. Lu
@ 2013-10-08 15:23 ` Jan Beulich
2013-10-08 15:34 ` H.J. Lu
0 siblings, 1 reply; 33+ messages in thread
From: Jan Beulich @ 2013-10-08 15:23 UTC (permalink / raw)
To: H.J. Lu; +Cc: kirill.yukhin, Binutils
>>> On 08.10.13 at 17:16, "H.J. Lu" <hjl.tools@gmail.com> wrote:
> On Tue, Oct 8, 2013 at 7:42 AM, Jan Beulich <JBeulich@suse.com> wrote:
>> bndmk, bndldx, and bndstx assign special meaning to base and index
>> registers, and hence silently swapping the registers should be
>> suppressed.
>>
>> gas/
>> 2013-10-08 Jan Beulich <jbeulich@suse.com>
>>
>> * tc-i386.c (i386_intel_simplify_register): Suppress base/index
>> swapping for bndmk, bndldx, and bndstx.
>>
>> --- 2013-10-07/gas/config/tc-i386-intel.c
>> +++ 2013-10-07/gas/config/tc-i386-intel.c
>> @@ -291,6 +291,8 @@ i386_intel_simplify_register (expression
>> else if (!intel_state.index)
>> {
>> if (intel_state.in_scale
>> + || current_templates->start->base_opcode == 0xf30f1b /* bndmk */
>> + || (current_templates->start->base_opcode & ~1) == 0x0f1a /* bnd{ld,st}x */
>> || i386_regtab[reg_num].reg_type.bitfield.baseindex)
>> intel_state.index = i386_regtab + reg_num;
>> else
>>
>>
>>
>
> We need a testcase for this.
Which is included in patch 1!
Jan
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 4/6] x86/MPX: bndmk, bndldx, and bndstx only allow a memory operand
2013-10-08 14:43 ` [PATCH 4/6] x86/MPX: bndmk, bndldx, and bndstx only allow a memory operand Jan Beulich
@ 2013-10-08 15:28 ` H.J. Lu
2013-10-09 7:24 ` Jan Beulich
0 siblings, 1 reply; 33+ messages in thread
From: H.J. Lu @ 2013-10-08 15:28 UTC (permalink / raw)
To: Jan Beulich; +Cc: kirill.yukhin, Binutils
On Tue, Oct 8, 2013 at 7:43 AM, Jan Beulich <JBeulich@suse.com> wrote:
> bndmk, bndldx, and bndstx only allow memory operands, so decoding should
> use OP_M() instead of OP_E().
The change isn't wrong. But register operand will never be used since
MOD != 3. Also, in this case, only register operand is possible for nop
since MOD == 0x3. If we want to make the change, we should also
replace Ev with Gv.
> opcodes/
> 2013-10-08 Jan Beulich <jbeulich@suse.com>
>
> * i386-dis.c (Mv_bnd): New.
> (mod_table): Use it for bndmk, bndldx, and bndstx.
>
> --- 2013-10-07/opcodes/i386-dis.c
> +++ 2013-10-07/opcodes/i386-dis.c
> @@ -250,6 +250,7 @@ fetch_data (struct disassemble_info *inf
> #define Mo { OP_M, o_mode }
> #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
> #define Mq { OP_M, q_mode }
> +#define Mv_bnd { OP_M, v_bnd_mode }
> #define Mx { OP_M, x_mode }
> #define Mxmm { OP_M, xmm_mode }
> #define Gb { OP_G, b_mode }
> @@ -11126,17 +11127,17 @@ static const struct dis386 mod_table[][2
> },
> {
> /* MOD_0F1A_PREFIX_0 */
> - { "bndldx", { Gbnd, Ev_bnd } },
> + { "bndldx", { Gbnd, Mv_bnd } },
> { "nopQ", { Ev } },
> },
> {
> /* MOD_0F1B_PREFIX_0 */
> - { "bndstx", { Ev_bnd, Gbnd } },
> + { "bndstx", { Mv_bnd, Gbnd } },
> { "nopQ", { Ev } },
> },
> {
> /* MOD_0F1B_PREFIX_1 */
> - { "bndmk", { Gbnd, Ev_bnd } },
> + { "bndmk", { Gbnd, Mv_bnd } },
> { "nopQ", { Ev } },
> },
> {
>
--
H.J.
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 2/6] x86/MPX: fix address size handling
2013-10-08 15:20 ` Jan Beulich
@ 2013-10-08 15:32 ` H.J. Lu
2013-10-09 7:30 ` Jan Beulich
0 siblings, 1 reply; 33+ messages in thread
From: H.J. Lu @ 2013-10-08 15:32 UTC (permalink / raw)
To: Jan Beulich; +Cc: kirill.yukhin, Binutils
On Tue, Oct 8, 2013 at 8:20 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>> On 08.10.13 at 17:15, "H.J. Lu" <hjl.tools@gmail.com> wrote:
>> On Tue, Oct 8, 2013 at 7:41 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>> While address overrides are ignored in 64-bit mode (and hence shouldn't
>>> result in an error), trying to use 16-bit addressing is documented to
>>> result in #UD, and hence the assembler should reject the attempt.
>>>
>>> gas/
>>> 2013-10-08 Jan Beulich <jbeulich@suse.com>
>>>
>>> * tc-i386.c (md_assemble): Alter address size checking for MPX
>>> instructions.
>>>
>>> --- 2013-10-07/gas/config/tc-i386.c
>>> +++ 2013-10-07/gas/config/tc-i386.c
>>> @@ -3549,10 +3549,15 @@ md_assemble (char *line)
>>> if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
>>> as_bad (_("expecting valid branch instruction after `bnd'"));
>>>
>>> - if (i.tm.cpu_flags.bitfield.cpumpx
>>> - && flag_code == CODE_64BIT
>>> - && i.prefix[ADDR_PREFIX])
>>> - as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
>>
>> It is done on purpose. When 32-bit address prefix in 64-bit is ignored,
>> MPX doesn't work correctly for x32.
>
> I don't understand: It _is_ being ignored by the hardware as per
> the documentation. So x32 need to get along with that. Maybe
> an example would help, so I could understand why you think
> this _needs_ to be an error...
>
X32 won't work with MPX since hardware assumes pointer
size is always 64 bit in 64-bit mode with or without address
size prefix. MPX depends on correct pointer size to work.
I don't want people to use MPX in x32 by accident.
--
H.J.
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 3/6] x86/MPX: suppress base/index swapping in Intel mode for bndmk, bndldx, and bndstx
2013-10-08 15:23 ` Jan Beulich
@ 2013-10-08 15:34 ` H.J. Lu
2013-10-08 16:00 ` Jan Beulich
0 siblings, 1 reply; 33+ messages in thread
From: H.J. Lu @ 2013-10-08 15:34 UTC (permalink / raw)
To: Jan Beulich; +Cc: kirill.yukhin, Binutils
On Tue, Oct 8, 2013 at 8:22 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>> On 08.10.13 at 17:16, "H.J. Lu" <hjl.tools@gmail.com> wrote:
>> On Tue, Oct 8, 2013 at 7:42 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>> bndmk, bndldx, and bndstx assign special meaning to base and index
>>> registers, and hence silently swapping the registers should be
>>> suppressed.
>>>
>>> gas/
>>> 2013-10-08 Jan Beulich <jbeulich@suse.com>
>>>
>>> * tc-i386.c (i386_intel_simplify_register): Suppress base/index
>>> swapping for bndmk, bndldx, and bndstx.
>>>
>>> --- 2013-10-07/gas/config/tc-i386-intel.c
>>> +++ 2013-10-07/gas/config/tc-i386-intel.c
>>> @@ -291,6 +291,8 @@ i386_intel_simplify_register (expression
>>> else if (!intel_state.index)
>>> {
>>> if (intel_state.in_scale
>>> + || current_templates->start->base_opcode == 0xf30f1b /* bndmk */
>>> + || (current_templates->start->base_opcode & ~1) == 0x0f1a /* bnd{ld,st}x */
>>> || i386_regtab[reg_num].reg_type.bitfield.baseindex)
>>> intel_state.index = i386_regtab + reg_num;
>>> else
>>>
>>>
>>>
>>
>> We need a testcase for this.
>
> Which is included in patch 1!
Does that mean I got "make check" failure with patch 1 applied?
A patch shouldn't introduce a "make check" failure and a testcase
should be together with the change.
--
H.J.
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 5/6] x86/MPX: fix operand size handling
2013-10-08 14:43 ` [PATCH 5/6] x86/MPX: fix operand size handling Jan Beulich
@ 2013-10-08 15:45 ` H.J. Lu
2013-10-09 7:36 ` Jan Beulich
0 siblings, 1 reply; 33+ messages in thread
From: H.J. Lu @ 2013-10-08 15:45 UTC (permalink / raw)
To: Jan Beulich; +Cc: kirill.yukhin, Binutils
On Tue, Oct 8, 2013 at 7:43 AM, Jan Beulich <JBeulich@suse.com> wrote:
> All MPX instructions in 64-bit mode ignore REX.W, which means we neither
> need to encode this bit nor should disassemble with 32-bit register
> operands.
>
> No MPX instructions would ever take a 16-bit register operand.
>
> gas/
> 2013-10-08 Jan Beulich <jbeulich@suse.com>
>
> * tc-i386.c (process_suffix): Warn about 32-bit register operands
> to MPX instructions in 64-bit mode.
I think it should be an error.
> opcodes/
> 2013-10-08 Jan Beulich <jbeulich@suse.com>
>
> * i386-dis.c (intel_operand_size): Move v_bnd_mode alongside the
> default case.
> (OP_E_register): Move v_bnd_mode alongside m_mode.
> * i386-opc.h (REGNAM_RAX): New.
> * i386-opc.tbl (bndcl, bndcu, bndcn): Drop Reg16. Add NoRex64.
> * i386-tbl.h: Re-generate.
>
Should we also remove Disp16?
--
H.J.
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 3/6] x86/MPX: suppress base/index swapping in Intel mode for bndmk, bndldx, and bndstx
2013-10-08 15:34 ` H.J. Lu
@ 2013-10-08 16:00 ` Jan Beulich
2013-10-08 16:19 ` H.J. Lu
0 siblings, 1 reply; 33+ messages in thread
From: Jan Beulich @ 2013-10-08 16:00 UTC (permalink / raw)
To: H.J. Lu; +Cc: kirill.yukhin, Binutils
>>> On 08.10.13 at 17:33, "H.J. Lu" <hjl.tools@gmail.com> wrote:
> On Tue, Oct 8, 2013 at 8:22 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>>> On 08.10.13 at 17:16, "H.J. Lu" <hjl.tools@gmail.com> wrote:
>>> On Tue, Oct 8, 2013 at 7:42 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>> bndmk, bndldx, and bndstx assign special meaning to base and index
>>>> registers, and hence silently swapping the registers should be
>>>> suppressed.
>>>>
>>>> gas/
>>>> 2013-10-08 Jan Beulich <jbeulich@suse.com>
>>>>
>>>> * tc-i386.c (i386_intel_simplify_register): Suppress base/index
>>>> swapping for bndmk, bndldx, and bndstx.
>>>>
>>>> --- 2013-10-07/gas/config/tc-i386-intel.c
>>>> +++ 2013-10-07/gas/config/tc-i386-intel.c
>>>> @@ -291,6 +291,8 @@ i386_intel_simplify_register (expression
>>>> else if (!intel_state.index)
>>>> {
>>>> if (intel_state.in_scale
>>>> + || current_templates->start->base_opcode == 0xf30f1b /* bndmk */
>>>> + || (current_templates->start->base_opcode & ~1) == 0x0f1a /*
> bnd{ld,st}x */
>>>> || i386_regtab[reg_num].reg_type.bitfield.baseindex)
>>>> intel_state.index = i386_regtab + reg_num;
>>>> else
>>>>
>>>>
>>>>
>>>
>>> We need a testcase for this.
>>
>> Which is included in patch 1!
>
> Does that mean I got "make check" failure with patch 1 applied?
> A patch shouldn't introduce a "make check" failure and a testcase
> should be together with the change.
Both 0/6 and 1/6 mentioned this quite clearly. And no, with how
badly the MPX tests were written (referring to other badly written
ones would at best be a lame excuse), I don't think it's appropriate
for you to ask that I now go back and disentangle all the various
changes to those test cases. You shouldn't have approved/
committed such non-extensible test cases in the first place.
Jan
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 6/6] x86/MPX: bndmk, bndldx, and bndstx don't allow RIP-relative addressing
2013-10-08 14:44 ` [PATCH 6/6] x86/MPX: bndmk, bndldx, and bndstx don't allow RIP-relative addressing Jan Beulich
@ 2013-10-08 16:13 ` H.J. Lu
2013-10-09 7:40 ` Jan Beulich
0 siblings, 1 reply; 33+ messages in thread
From: H.J. Lu @ 2013-10-08 16:13 UTC (permalink / raw)
To: Jan Beulich; +Cc: kirill.yukhin, Binutils
On Tue, Oct 8, 2013 at 7:44 AM, Jan Beulich <JBeulich@suse.com> wrote:
> gas/
> 2013-10-08 Jan Beulich <jbeulich@suse.com>
>
> * tc-i386.c (i386_index_check): Reject RIP-relative addressing for
> bndmk, bndldx, and bndstx. Warn about register scaling by other
> than 1 for bndldx and bndstx.
>
> --- 2013-10-07/gas/config/tc-i386.c
> +++ 2013-10-07/gas/config/tc-i386.c
> @@ -8360,6 +8375,25 @@ bad_address:
> || i.index_reg->reg_num == RegEiz))
> || !i.index_reg->reg_type.bitfield.baseindex)))
> goto bad_address;
> +
> + /* bndmk, bndldx, and bndstx have special restrictions. */
> + if (current_templates->start->base_opcode == 0xf30f1b
> + || (current_templates->start->base_opcode & ~1) == 0x0f1a)
> + {
> + /* They cannot use RIP-relative addressing. */
> + if (i.base_reg
> + && i.base_reg->reg_num == (addr_mode == CODE_64BIT ? RegRip
> + : RegEip))
> + {
> + as_bad (_("`%s' cannot be used here"), operand_string);
> + return 0;
> + }
RegEip should be disallowed much earlier since address size
prefix doesn't work for MPX.
> + /* bndldx and bndstx ignore their scale factor. */
> + if (current_templates->start->base_opcode != 0xf30f1b
> + && i.log2_scale_factor)
> + as_warn (_("register scaling is being ignored here"));
Scaling factor is still encoded. I am not sure if it belongs to assembler.
> + }
> }
> else
> {
>
>
>
--
H.J.
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 3/6] x86/MPX: suppress base/index swapping in Intel mode for bndmk, bndldx, and bndstx
2013-10-08 16:00 ` Jan Beulich
@ 2013-10-08 16:19 ` H.J. Lu
2013-10-09 7:15 ` acceptance rules (was: Re: [PATCH 3/6] x86/MPX: suppress base/index swapping ...) Jan Beulich
0 siblings, 1 reply; 33+ messages in thread
From: H.J. Lu @ 2013-10-08 16:19 UTC (permalink / raw)
To: Jan Beulich; +Cc: kirill.yukhin, Binutils
On Tue, Oct 8, 2013 at 9:00 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>> On 08.10.13 at 17:33, "H.J. Lu" <hjl.tools@gmail.com> wrote:
>> On Tue, Oct 8, 2013 at 8:22 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>>>> On 08.10.13 at 17:16, "H.J. Lu" <hjl.tools@gmail.com> wrote:
>>>> On Tue, Oct 8, 2013 at 7:42 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>>> bndmk, bndldx, and bndstx assign special meaning to base and index
>>>>> registers, and hence silently swapping the registers should be
>>>>> suppressed.
>>>>>
>>>>> gas/
>>>>> 2013-10-08 Jan Beulich <jbeulich@suse.com>
>>>>>
>>>>> * tc-i386.c (i386_intel_simplify_register): Suppress base/index
>>>>> swapping for bndmk, bndldx, and bndstx.
>>>>>
>>>>> --- 2013-10-07/gas/config/tc-i386-intel.c
>>>>> +++ 2013-10-07/gas/config/tc-i386-intel.c
>>>>> @@ -291,6 +291,8 @@ i386_intel_simplify_register (expression
>>>>> else if (!intel_state.index)
>>>>> {
>>>>> if (intel_state.in_scale
>>>>> + || current_templates->start->base_opcode == 0xf30f1b /* bndmk */
>>>>> + || (current_templates->start->base_opcode & ~1) == 0x0f1a /*
>> bnd{ld,st}x */
>>>>> || i386_regtab[reg_num].reg_type.bitfield.baseindex)
>>>>> intel_state.index = i386_regtab + reg_num;
>>>>> else
>>>>>
>>>>>
>>>>>
>>>>
>>>> We need a testcase for this.
>>>
>>> Which is included in patch 1!
>>
>> Does that mean I got "make check" failure with patch 1 applied?
>> A patch shouldn't introduce a "make check" failure and a testcase
>> should be together with the change.
>
> Both 0/6 and 1/6 mentioned this quite clearly. And no, with how
> badly the MPX tests were written (referring to other badly written
> ones would at best be a lame excuse), I don't think it's appropriate
> for you to ask that I now go back and disentangle all the various
> changes to those test cases. You shouldn't have approved/
> committed such non-extensible test cases in the first place.
>
I prefer a testcase together with the corresponding change,
instead of a jumbo testcase patch. I also don't agree every
MPX change you proposed. If it makes it easier to write
testcases, you can use a separate testcase file for each
change.
Thanks.
--
H.J.
^ permalink raw reply [flat|nested] 33+ messages in thread
* acceptance rules (was: Re: [PATCH 3/6] x86/MPX: suppress base/index swapping ...)
2013-10-08 16:19 ` H.J. Lu
@ 2013-10-09 7:15 ` Jan Beulich
2013-10-09 16:45 ` H.J. Lu
0 siblings, 1 reply; 33+ messages in thread
From: Jan Beulich @ 2013-10-09 7:15 UTC (permalink / raw)
To: Alan Modra, H.J. Lu, Ian Taylor, Nick Clifton, Richard Henderson
Cc: kirill.yukhin, Binutils
>>> On 08.10.13 at 18:19, "H.J. Lu" <hjl.tools@gmail.com> wrote:
> I prefer a testcase together with the corresponding change,
> instead of a jumbo testcase patch. I also don't agree every
> MPX change you proposed. If it makes it easier to write
> testcases, you can use a separate testcase file for each
> change.
Okay, so then I'll submit a monolithic patch combined with the
testcase changes (once we sorted out eventual adjustments).
Separate testcase files is not a desirable approach imo - what
belongs together should stay together. As additional context:
Getting the existing test case straightened took me significantly
more time than fixing the actual bugs here, and I simply don't
see myself wasting more time on this unless there's a _good_
reason.
And just to repeat - I'm very opposed to the idea of rejecting
bug fixes just because of controversy about test cases. This
isn't happening the first time (and is also not isolated to you as
the x86 maintainer). I very much think that bug fixes ought to
be acceptable in any case, and test cases ought to be optional.
I can see this being more strict for enhancements, and even a
requirement for new feature additions.
Yet in no case should - imo - badly written test cases be
accepted just because this is better than no test case at all.
But of course I realize that there's no guideline (or at least I'm
unaware of there being any) on how a good test case would
look like (my main requirements would be that they (a) don't
test things to be valid that aren't and (b) use patterns instead
of exact matches where precise values don't matter so that
they can be extended without having to entirely replace them).
I specifically added some of the general maintainers that I
recall being relatively active in that role (others - please
forgive me not recalling) to the recipient list, as I think this is a
more general problem, and I'm seeking clarification as things
going the way they do currently may make me stay away from
contributing back bug fixes if there's a risk of them not being
accepted just because of differing opinions on test case
requirements (I already refrained from re-submitting an ARM
bug fix about half a year ago for that very reason). There are
better ways I can spend my time, and I could probably live with
the extra (but also unnecessary from an abstract perspective)
work needed to keep such fixes up to date.
Jan
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 4/6] x86/MPX: bndmk, bndldx, and bndstx only allow a memory operand
2013-10-08 15:28 ` H.J. Lu
@ 2013-10-09 7:24 ` Jan Beulich
2013-10-09 15:17 ` H.J. Lu
0 siblings, 1 reply; 33+ messages in thread
From: Jan Beulich @ 2013-10-09 7:24 UTC (permalink / raw)
To: H.J. Lu; +Cc: kirill.yukhin, Binutils
>>> On 08.10.13 at 17:28, "H.J. Lu" <hjl.tools@gmail.com> wrote:
> On Tue, Oct 8, 2013 at 7:43 AM, Jan Beulich <JBeulich@suse.com> wrote:
>> bndmk, bndldx, and bndstx only allow memory operands, so decoding should
>> use OP_M() instead of OP_E().
>
> The change isn't wrong. But register operand will never be used since
> MOD != 3. Also, in this case, only register operand is possible for nop
> since MOD == 0x3. If we want to make the change, we should also
> replace Ev with Gv.
Looks like I didn't look at mod_table[]'s usage closely enough - I
guess for consistency reasons I'll withdraw the patch rather than
extending it (even though performance would perhaps be slightly
improved by using the more specific operand handling routines
here, but that would be the case for various other code paths /
table entries too I believe).
Jan
>> opcodes/
>> 2013-10-08 Jan Beulich <jbeulich@suse.com>
>>
>> * i386-dis.c (Mv_bnd): New.
>> (mod_table): Use it for bndmk, bndldx, and bndstx.
>>
>> --- 2013-10-07/opcodes/i386-dis.c
>> +++ 2013-10-07/opcodes/i386-dis.c
>> @@ -250,6 +250,7 @@ fetch_data (struct disassemble_info *inf
>> #define Mo { OP_M, o_mode }
>> #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for
> LDS, LES etc */
>> #define Mq { OP_M, q_mode }
>> +#define Mv_bnd { OP_M, v_bnd_mode }
>> #define Mx { OP_M, x_mode }
>> #define Mxmm { OP_M, xmm_mode }
>> #define Gb { OP_G, b_mode }
>> @@ -11126,17 +11127,17 @@ static const struct dis386 mod_table[][2
>> },
>> {
>> /* MOD_0F1A_PREFIX_0 */
>> - { "bndldx", { Gbnd, Ev_bnd } },
>> + { "bndldx", { Gbnd, Mv_bnd } },
>> { "nopQ", { Ev } },
>> },
>> {
>> /* MOD_0F1B_PREFIX_0 */
>> - { "bndstx", { Ev_bnd, Gbnd } },
>> + { "bndstx", { Mv_bnd, Gbnd } },
>> { "nopQ", { Ev } },
>> },
>> {
>> /* MOD_0F1B_PREFIX_1 */
>> - { "bndmk", { Gbnd, Ev_bnd } },
>> + { "bndmk", { Gbnd, Mv_bnd } },
>> { "nopQ", { Ev } },
>> },
>> {
>>
>
>
>
> --
> H.J.
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 2/6] x86/MPX: fix address size handling
2013-10-08 15:32 ` H.J. Lu
@ 2013-10-09 7:30 ` Jan Beulich
2013-10-09 15:45 ` H.J. Lu
0 siblings, 1 reply; 33+ messages in thread
From: Jan Beulich @ 2013-10-09 7:30 UTC (permalink / raw)
To: H.J. Lu; +Cc: kirill.yukhin, Binutils
>>> On 08.10.13 at 17:32, "H.J. Lu" <hjl.tools@gmail.com> wrote:
> On Tue, Oct 8, 2013 at 8:20 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>>> On 08.10.13 at 17:15, "H.J. Lu" <hjl.tools@gmail.com> wrote:
>>> On Tue, Oct 8, 2013 at 7:41 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>> While address overrides are ignored in 64-bit mode (and hence shouldn't
>>>> result in an error), trying to use 16-bit addressing is documented to
>>>> result in #UD, and hence the assembler should reject the attempt.
>>>>
>>>> gas/
>>>> 2013-10-08 Jan Beulich <jbeulich@suse.com>
>>>>
>>>> * tc-i386.c (md_assemble): Alter address size checking for MPX
>>>> instructions.
>>>>
>>>> --- 2013-10-07/gas/config/tc-i386.c
>>>> +++ 2013-10-07/gas/config/tc-i386.c
>>>> @@ -3549,10 +3549,15 @@ md_assemble (char *line)
>>>> if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
>>>> as_bad (_("expecting valid branch instruction after `bnd'"));
>>>>
>>>> - if (i.tm.cpu_flags.bitfield.cpumpx
>>>> - && flag_code == CODE_64BIT
>>>> - && i.prefix[ADDR_PREFIX])
>>>> - as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
>>>
>>> It is done on purpose. When 32-bit address prefix in 64-bit is ignored,
>>> MPX doesn't work correctly for x32.
>>
>> I don't understand: It _is_ being ignored by the hardware as per
>> the documentation. So x32 need to get along with that. Maybe
>> an example would help, so I could understand why you think
>> this _needs_ to be an error...
>>
>
> X32 won't work with MPX since hardware assumes pointer
> size is always 64 bit in 64-bit mode with or without address
> size prefix. MPX depends on correct pointer size to work.
> I don't want people to use MPX in x32 by accident.
This seems even more odd - why would x32 be excluded from
using MPX? Again - an example might help, as my understanding
so far was that the implicit zero extension of results of 32-bit
operations should guarantee the half width pointers to be quite
fine to use as full width values (i.e. in other memory operands
I don't see why you would want to use 32-bit addressing either,
except when the wraparound case matters, as might e.g. be
the case with EIP-relative addressing).
And in any case - the assembler shouldn't enforce policy, it
should only enforce architectural restrictions.
Bottom line - I continue to be convinced that the diagnostic
we talk about here ought to be a warning, not an error (at
least by default).
Jan
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 5/6] x86/MPX: fix operand size handling
2013-10-08 15:45 ` H.J. Lu
@ 2013-10-09 7:36 ` Jan Beulich
2013-10-09 15:51 ` H.J. Lu
0 siblings, 1 reply; 33+ messages in thread
From: Jan Beulich @ 2013-10-09 7:36 UTC (permalink / raw)
To: H.J. Lu; +Cc: kirill.yukhin, Binutils
>>> On 08.10.13 at 17:45, "H.J. Lu" <hjl.tools@gmail.com> wrote:
> On Tue, Oct 8, 2013 at 7:43 AM, Jan Beulich <JBeulich@suse.com> wrote:
>> All MPX instructions in 64-bit mode ignore REX.W, which means we neither
>> need to encode this bit nor should disassemble with 32-bit register
>> operands.
>>
>> No MPX instructions would ever take a 16-bit register operand.
>>
>> gas/
>> 2013-10-08 Jan Beulich <jbeulich@suse.com>
>>
>> * tc-i386.c (process_suffix): Warn about 32-bit register operands
>> to MPX instructions in 64-bit mode.
>
> I think it should be an error.
I can certainly change that - a warning just seemed a better match
to hardware ignoring operand size here.
>> opcodes/
>> 2013-10-08 Jan Beulich <jbeulich@suse.com>
>>
>> * i386-dis.c (intel_operand_size): Move v_bnd_mode alongside the
>> default case.
>> (OP_E_register): Move v_bnd_mode alongside m_mode.
>> * i386-opc.h (REGNAM_RAX): New.
>> * i386-opc.tbl (bndcl, bndcu, bndcn): Drop Reg16. Add NoRex64.
>> * i386-tbl.h: Re-generate.
>>
>
> Should we also remove Disp16?
Yes, we certainly could, but then also from the other MPX
instructions. Logically this would belong into the address size fix
patch though.
Jan
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 6/6] x86/MPX: bndmk, bndldx, and bndstx don't allow RIP-relative addressing
2013-10-08 16:13 ` H.J. Lu
@ 2013-10-09 7:40 ` Jan Beulich
0 siblings, 0 replies; 33+ messages in thread
From: Jan Beulich @ 2013-10-09 7:40 UTC (permalink / raw)
To: H.J. Lu; +Cc: kirill.yukhin, Binutils
>>> On 08.10.13 at 18:13, "H.J. Lu" <hjl.tools@gmail.com> wrote:
> On Tue, Oct 8, 2013 at 7:44 AM, Jan Beulich <JBeulich@suse.com> wrote:
>> gas/
>> 2013-10-08 Jan Beulich <jbeulich@suse.com>
>>
>> * tc-i386.c (i386_index_check): Reject RIP-relative addressing for
>> bndmk, bndldx, and bndstx. Warn about register scaling by other
>> than 1 for bndldx and bndstx.
>>
>> --- 2013-10-07/gas/config/tc-i386.c
>> +++ 2013-10-07/gas/config/tc-i386.c
>> @@ -8360,6 +8375,25 @@ bad_address:
>> || i.index_reg->reg_num == RegEiz))
>> || !i.index_reg->reg_type.bitfield.baseindex)))
>> goto bad_address;
>> +
>> + /* bndmk, bndldx, and bndstx have special restrictions. */
>> + if (current_templates->start->base_opcode == 0xf30f1b
>> + || (current_templates->start->base_opcode & ~1) == 0x0f1a)
>> + {
>> + /* They cannot use RIP-relative addressing. */
>> + if (i.base_reg
>> + && i.base_reg->reg_num == (addr_mode == CODE_64BIT ? RegRip
>> + : RegEip))
>> + {
>> + as_bad (_("`%s' cannot be used here"), operand_string);
>> + return 0;
>> + }
>
> RegEip should be disallowed much earlier since address size
> prefix doesn't work for MPX.
Only if that diagnostic gets converted back to an error, which I
don't agree to so far.
>> + /* bndldx and bndstx ignore their scale factor. */
>> + if (current_templates->start->base_opcode != 0xf30f1b
>> + && i.log2_scale_factor)
>> + as_warn (_("register scaling is being ignored here"));
>
> Scaling factor is still encoded. I am not sure if it belongs to assembler.
That's why it's a warning - it's providing a hint to the programmer
that what (s)he wrote makes no sense, but is being accepted. I
wouldn't, however, mind hiding this one when quiet_warnings is set.
Jan
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 4/6] x86/MPX: bndmk, bndldx, and bndstx only allow a memory operand
2013-10-09 7:24 ` Jan Beulich
@ 2013-10-09 15:17 ` H.J. Lu
0 siblings, 0 replies; 33+ messages in thread
From: H.J. Lu @ 2013-10-09 15:17 UTC (permalink / raw)
To: Jan Beulich; +Cc: kirill.yukhin, Binutils
On Wed, Oct 9, 2013 at 12:24 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>> On 08.10.13 at 17:28, "H.J. Lu" <hjl.tools@gmail.com> wrote:
>> On Tue, Oct 8, 2013 at 7:43 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>> bndmk, bndldx, and bndstx only allow memory operands, so decoding should
>>> use OP_M() instead of OP_E().
>>
>> The change isn't wrong. But register operand will never be used since
>> MOD != 3. Also, in this case, only register operand is possible for nop
>> since MOD == 0x3. If we want to make the change, we should also
>> replace Ev with Gv.
>
> Looks like I didn't look at mod_table[]'s usage closely enough - I
> guess for consistency reasons I'll withdraw the patch rather than
> extending it (even though performance would perhaps be slightly
> improved by using the more specific operand handling routines
> here, but that would be the case for various other code paths /
> table entries too I believe).
>
We have
static void
OP_M (int bytemode, int sizeflag)
{
if (modrm.mod == 3)
/* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
BadOp ();
else
OP_E (bytemode, sizeflag);
}
OP_M will be slower than OP_E. With mod_table, we can get rid
rid of OP_M. A patch is welcome.
--
H.J.
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 2/6] x86/MPX: fix address size handling
2013-10-09 7:30 ` Jan Beulich
@ 2013-10-09 15:45 ` H.J. Lu
2013-10-10 12:27 ` Jan Beulich
0 siblings, 1 reply; 33+ messages in thread
From: H.J. Lu @ 2013-10-09 15:45 UTC (permalink / raw)
To: Jan Beulich; +Cc: kirill.yukhin, Binutils
On Wed, Oct 9, 2013 at 12:30 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>> On 08.10.13 at 17:32, "H.J. Lu" <hjl.tools@gmail.com> wrote:
>> On Tue, Oct 8, 2013 at 8:20 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>>>> On 08.10.13 at 17:15, "H.J. Lu" <hjl.tools@gmail.com> wrote:
>>>> On Tue, Oct 8, 2013 at 7:41 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>>> While address overrides are ignored in 64-bit mode (and hence shouldn't
>>>>> result in an error), trying to use 16-bit addressing is documented to
>>>>> result in #UD, and hence the assembler should reject the attempt.
>>>>>
>>>>> gas/
>>>>> 2013-10-08 Jan Beulich <jbeulich@suse.com>
>>>>>
>>>>> * tc-i386.c (md_assemble): Alter address size checking for MPX
>>>>> instructions.
>>>>>
>>>>> --- 2013-10-07/gas/config/tc-i386.c
>>>>> +++ 2013-10-07/gas/config/tc-i386.c
>>>>> @@ -3549,10 +3549,15 @@ md_assemble (char *line)
>>>>> if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
>>>>> as_bad (_("expecting valid branch instruction after `bnd'"));
>>>>>
>>>>> - if (i.tm.cpu_flags.bitfield.cpumpx
>>>>> - && flag_code == CODE_64BIT
>>>>> - && i.prefix[ADDR_PREFIX])
>>>>> - as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
>>>>
>>>> It is done on purpose. When 32-bit address prefix in 64-bit is ignored,
>>>> MPX doesn't work correctly for x32.
>>>
>>> I don't understand: It _is_ being ignored by the hardware as per
>>> the documentation. So x32 need to get along with that. Maybe
>>> an example would help, so I could understand why you think
>>> this _needs_ to be an error...
>>>
>>
>> X32 won't work with MPX since hardware assumes pointer
>> size is always 64 bit in 64-bit mode with or without address
>> size prefix. MPX depends on correct pointer size to work.
>> I don't want people to use MPX in x32 by accident.
>
> This seems even more odd - why would x32 be excluded from
> using MPX? Again - an example might help, as my understanding
> so far was that the implicit zero extension of results of 32-bit
> operations should guarantee the half width pointers to be quite
> fine to use as full width values (i.e. in other memory operands
> I don't see why you would want to use 32-bit addressing either,
> except when the wraparound case matters, as might e.g. be
> the case with EIP-relative addressing).
In 64-bit mode, bndldx and bndstx ignore the lower 3 bits of
the address of a pointer, which is OK when pointers are
64-bit aligned. X32 runs in 64-bit mode. But pointers are
32-bit aligned. That means 2 pointers may point to the same
bound table entry. That is why MPX won't work for x32 and
assembler shouldn't allow it.
--
H.J.
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 5/6] x86/MPX: fix operand size handling
2013-10-09 7:36 ` Jan Beulich
@ 2013-10-09 15:51 ` H.J. Lu
2013-10-10 13:14 ` Jan Beulich
0 siblings, 1 reply; 33+ messages in thread
From: H.J. Lu @ 2013-10-09 15:51 UTC (permalink / raw)
To: Jan Beulich; +Cc: kirill.yukhin, Binutils
On Wed, Oct 9, 2013 at 12:36 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>> On 08.10.13 at 17:45, "H.J. Lu" <hjl.tools@gmail.com> wrote:
>> On Tue, Oct 8, 2013 at 7:43 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>> All MPX instructions in 64-bit mode ignore REX.W, which means we neither
>>> need to encode this bit nor should disassemble with 32-bit register
>>> operands.
>>>
>>> No MPX instructions would ever take a 16-bit register operand.
>>>
>>> gas/
>>> 2013-10-08 Jan Beulich <jbeulich@suse.com>
>>>
>>> * tc-i386.c (process_suffix): Warn about 32-bit register operands
>>> to MPX instructions in 64-bit mode.
>>
>> I think it should be an error.
>
> I can certainly change that - a warning just seemed a better match
> to hardware ignoring operand size here.
We can use separate entries with Reg32 for CpuNo64 and Reg64 for Cpu64,
similar to mov with debug registers. Let's do that instead.
>>> opcodes/
>>> 2013-10-08 Jan Beulich <jbeulich@suse.com>
>>>
>>> * i386-dis.c (intel_operand_size): Move v_bnd_mode alongside the
>>> default case.
>>> (OP_E_register): Move v_bnd_mode alongside m_mode.
>>> * i386-opc.h (REGNAM_RAX): New.
>>> * i386-opc.tbl (bndcl, bndcu, bndcn): Drop Reg16. Add NoRex64.
>>> * i386-tbl.h: Re-generate.
>>>
>>
>> Should we also remove Disp16?
>
> Yes, we certainly could, but then also from the other MPX
> instructions. Logically this would belong into the address size fix
> patch though.
>
> Jan
>
--
H.J.
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: acceptance rules (was: Re: [PATCH 3/6] x86/MPX: suppress base/index swapping ...)
2013-10-09 7:15 ` acceptance rules (was: Re: [PATCH 3/6] x86/MPX: suppress base/index swapping ...) Jan Beulich
@ 2013-10-09 16:45 ` H.J. Lu
0 siblings, 0 replies; 33+ messages in thread
From: H.J. Lu @ 2013-10-09 16:45 UTC (permalink / raw)
To: Jan Beulich
Cc: Alan Modra, Ian Taylor, Nick Clifton, Richard Henderson,
kirill.yukhin, Binutils
On Wed, Oct 9, 2013 at 12:15 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>> On 08.10.13 at 18:19, "H.J. Lu" <hjl.tools@gmail.com> wrote:
>> I prefer a testcase together with the corresponding change,
>> instead of a jumbo testcase patch. I also don't agree every
>> MPX change you proposed. If it makes it easier to write
>> testcases, you can use a separate testcase file for each
>> change.
>
> Okay, so then I'll submit a monolithic patch combined with the
> testcase changes (once we sorted out eventual adjustments).
> Separate testcase files is not a desirable approach imo - what
> belongs together should stay together. As additional context:
> Getting the existing test case straightened took me significantly
> more time than fixing the actual bugs here, and I simply don't
You can open a bug report to report the issue
against the existing testcase.
> see myself wasting more time on this unless there's a _good_
> reason.
>
> And just to repeat - I'm very opposed to the idea of rejecting
> bug fixes just because of controversy about test cases. This
> isn't happening the first time (and is also not isolated to you as
> the x86 maintainer). I very much think that bug fixes ought to
> be acceptable in any case, and test cases ought to be optional.
> I can see this being more strict for enhancements, and even a
> requirement for new feature additions.
If a patch changes the assembler behavior, it should
be verified via a testcase to make sure that it does
what it is intended and stays that way.
> Yet in no case should - imo - badly written test cases be
> accepted just because this is better than no test case at all.
> But of course I realize that there's no guideline (or at least I'm
> unaware of there being any) on how a good test case would
> look like (my main requirements would be that they (a) don't
> test things to be valid that aren't and (b) use patterns instead
> of exact matches where precise values don't matter so that
> they can be extended without having to entirely replace them).
If a testcase, which is supposed to pass, contains invalid
instructions, we should just fix it. If you notice any issue
within binutils, including testcases, just open a bug report
against it. At least, there is a trail.
Thanks for your contribution.
--
H.J.
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 2/6] x86/MPX: fix address size handling
2013-10-09 15:45 ` H.J. Lu
@ 2013-10-10 12:27 ` Jan Beulich
2013-10-10 15:18 ` H.J. Lu
0 siblings, 1 reply; 33+ messages in thread
From: Jan Beulich @ 2013-10-10 12:27 UTC (permalink / raw)
To: H.J. Lu; +Cc: kirill.yukhin, Binutils
>>> On 09.10.13 at 17:45, "H.J. Lu" <hjl.tools@gmail.com> wrote:
> On Wed, Oct 9, 2013 at 12:30 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>>> On 08.10.13 at 17:32, "H.J. Lu" <hjl.tools@gmail.com> wrote:
>>> On Tue, Oct 8, 2013 at 8:20 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>>>>> On 08.10.13 at 17:15, "H.J. Lu" <hjl.tools@gmail.com> wrote:
>>>>> On Tue, Oct 8, 2013 at 7:41 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>>>> While address overrides are ignored in 64-bit mode (and hence shouldn't
>>>>>> result in an error), trying to use 16-bit addressing is documented to
>>>>>> result in #UD, and hence the assembler should reject the attempt.
>>>>>>
>>>>>> gas/
>>>>>> 2013-10-08 Jan Beulich <jbeulich@suse.com>
>>>>>>
>>>>>> * tc-i386.c (md_assemble): Alter address size checking for MPX
>>>>>> instructions.
>>>>>>
>>>>>> --- 2013-10-07/gas/config/tc-i386.c
>>>>>> +++ 2013-10-07/gas/config/tc-i386.c
>>>>>> @@ -3549,10 +3549,15 @@ md_assemble (char *line)
>>>>>> if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
>>>>>> as_bad (_("expecting valid branch instruction after `bnd'"));
>>>>>>
>>>>>> - if (i.tm.cpu_flags.bitfield.cpumpx
>>>>>> - && flag_code == CODE_64BIT
>>>>>> - && i.prefix[ADDR_PREFIX])
>>>>>> - as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
>>>>>
>>>>> It is done on purpose. When 32-bit address prefix in 64-bit is ignored,
>>>>> MPX doesn't work correctly for x32.
>>>>
>>>> I don't understand: It _is_ being ignored by the hardware as per
>>>> the documentation. So x32 need to get along with that. Maybe
>>>> an example would help, so I could understand why you think
>>>> this _needs_ to be an error...
>>>>
>>>
>>> X32 won't work with MPX since hardware assumes pointer
>>> size is always 64 bit in 64-bit mode with or without address
>>> size prefix. MPX depends on correct pointer size to work.
>>> I don't want people to use MPX in x32 by accident.
>>
>> This seems even more odd - why would x32 be excluded from
>> using MPX? Again - an example might help, as my understanding
>> so far was that the implicit zero extension of results of 32-bit
>> operations should guarantee the half width pointers to be quite
>> fine to use as full width values (i.e. in other memory operands
>> I don't see why you would want to use 32-bit addressing either,
>> except when the wraparound case matters, as might e.g. be
>> the case with EIP-relative addressing).
>
> In 64-bit mode, bndldx and bndstx ignore the lower 3 bits of
> the address of a pointer, which is OK when pointers are
> 64-bit aligned. X32 runs in 64-bit mode. But pointers are
> 32-bit aligned. That means 2 pointers may point to the same
> bound table entry. That is why MPX won't work for x32 and
> assembler shouldn't allow it.
Here you're making assumptions that you can't control. For
example, there's nothing preventing anyone to create a
compiler/library pair that guarantees objects to be at least 8
bytes apart. And that's leaving aside that even in full 64-bit
mode there can be multiple objects within an 8-byte range.
As said before - the assembler should not enforce any kind of
policy.
Jan
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 5/6] x86/MPX: fix operand size handling
2013-10-09 15:51 ` H.J. Lu
@ 2013-10-10 13:14 ` Jan Beulich
2013-10-10 15:14 ` H.J. Lu
0 siblings, 1 reply; 33+ messages in thread
From: Jan Beulich @ 2013-10-10 13:14 UTC (permalink / raw)
To: H.J. Lu; +Cc: kirill.yukhin, Binutils
[-- Attachment #1: Type: text/plain, Size: 6230 bytes --]
>>> On 09.10.13 at 17:51, "H.J. Lu" <hjl.tools@gmail.com> wrote:
> On Wed, Oct 9, 2013 at 12:36 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>>> On 08.10.13 at 17:45, "H.J. Lu" <hjl.tools@gmail.com> wrote:
>>> On Tue, Oct 8, 2013 at 7:43 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>> All MPX instructions in 64-bit mode ignore REX.W, which means we neither
>>>> need to encode this bit nor should disassemble with 32-bit register
>>>> operands.
>>>>
>>>> No MPX instructions would ever take a 16-bit register operand.
>>>>
>>>> gas/
>>>> 2013-10-08 Jan Beulich <jbeulich@suse.com>
>>>>
>>>> * tc-i386.c (process_suffix): Warn about 32-bit register operands
>>>> to MPX instructions in 64-bit mode.
>>>
>>> I think it should be an error.
>>
>> I can certainly change that - a warning just seemed a better match
>> to hardware ignoring operand size here.
>
> We can use separate entries with Reg32 for CpuNo64 and Reg64 for Cpu64,
> similar to mov with debug registers. Let's do that instead.
Here's the updated patch.
Jan
General purpose register operands of MPX instructions can only ever be
native size ones.
opcodes/
2013-10-08 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (intel_operand_size): Move v_bnd_mode alongside the
default case.
(OP_E_register): Move v_bnd_mode alongside m_mode.
* i386-opc.tbl (bndcl, bndcu, bndcn): Split 32- and 64-bit variants.
Drop Reg16 and Disp16. Add NoRex64.
(bndmk, bndmov, bndldx, bndstx): Drop Disp16.
* i386-tbl.h: Re-generate.
--- 2013-10-07/opcodes/i386-dis.c
+++ 2013-10-07/opcodes/i386-dis.c
@@ -13800,7 +13801,6 @@ intel_operand_size (int bytemode, int si
}
/* FALLTHRU */
case v_mode:
- case v_bnd_mode:
case v_swap_mode:
case dq_mode:
USED_REX (REX_W);
@@ -14082,6 +14082,7 @@ intel_operand_size (int bytemode, int si
abort ();
oappend ("WORD PTR ");
break;
+ case v_bnd_mode:
default:
break;
}
@@ -14121,6 +14122,7 @@ OP_E_register (int bytemode, int sizefla
names = names64;
break;
case m_mode:
+ case v_bnd_mode:
names = address_mode == mode_64bit ? names64 : names32;
break;
case bnd_mode:
@@ -14135,7 +14137,6 @@ OP_E_register (int bytemode, int sizefla
bytemode = v_mode;
/* FALLTHRU */
case v_mode:
- case v_bnd_mode:
case v_swap_mode:
case dq_mode:
case dqb_mode:
--- 2013-10-07/opcodes/i386-opc.tbl
+++ 2013-10-07/opcodes/i386-opc.tbl
@@ -3061,14 +3061,17 @@ stac, 0, 0xf01, 0xcb, 2, CpuSMAP, No_bSu
bnd, 0, 0xf2, None, 1, CpuMPX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 }
// MPX instructions.
-bndmk, 2, 0xf30f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
-bndmov, 2, 0x660f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegBND, RegBND }
-bndmov, 2, 0x660f1b, None, 2, CpuMPX, S|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegBND, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegBND }
-bndcl, 2, 0xf30f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64|Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
-bndcu, 2, 0xf20f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64|Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
-bndcn, 2, 0xf20f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64|Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
-bndstx, 2, 0x0f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegBND, Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
-bndldx, 2, 0x0f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
+bndmk, 2, 0xf30f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Anysize|BaseIndex|Disp8|Disp32|Disp32S, RegBND }
+bndmov, 2, 0x660f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S|RegBND, RegBND }
+bndmov, 2, 0x660f1b, None, 2, CpuMPX, S|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegBND, Xmmword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S|RegBND }
+bndcl, 2, 0xf30f1a, None, 2, CpuMPX|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Anysize|BaseIndex|Disp8|Disp32, RegBND }
+bndcl, 2, 0xf30f1a, None, 2, CpuMPX|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg64|Anysize|BaseIndex|Disp8|Disp32|Disp32S, RegBND }
+bndcu, 2, 0xf20f1a, None, 2, CpuMPX|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Anysize|BaseIndex|Disp8|Disp32, RegBND }
+bndcu, 2, 0xf20f1a, None, 2, CpuMPX|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg64|Anysize|BaseIndex|Disp8|Disp32|Disp32S, RegBND }
+bndcn, 2, 0xf20f1b, None, 2, CpuMPX|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Anysize|BaseIndex|Disp8|Disp32, RegBND }
+bndcn, 2, 0xf20f1b, None, 2, CpuMPX|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg64|Anysize|BaseIndex|Disp8|Disp32|Disp32S, RegBND }
+bndstx, 2, 0x0f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegBND, Anysize|BaseIndex|Disp8|Disp32|Disp32S }
+bndldx, 2, 0x0f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Anysize|BaseIndex|Disp8|Disp32|Disp32S, RegBND }
// SHA instructions.
sha1rnds4, 3, 0xf3acc, None, 3, CpuSHA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
[-- Attachment #2: binutils-mainline-x86-MPX-operand-size.patch --]
[-- Type: text/plain, Size: 13548 bytes --]
General purpose register operands of MPX instructions can only ever be
native size ones.
opcodes/
2013-10-08 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (intel_operand_size): Move v_bnd_mode alongside the
default case.
(OP_E_register): Move v_bnd_mode alongside m_mode.
* i386-opc.tbl (bndcl, bndcu, bndcn): Split 32- and 64-bit variants.
Drop Reg16 and Disp16. Add NoRex64.
(bndmk, bndmov, bndldx, bndstx): Drop Disp16.
* i386-tbl.h: Re-generate.
--- 2013-10-07/opcodes/i386-dis.c
+++ 2013-10-07/opcodes/i386-dis.c
@@ -13800,7 +13801,6 @@ intel_operand_size (int bytemode, int si
}
/* FALLTHRU */
case v_mode:
- case v_bnd_mode:
case v_swap_mode:
case dq_mode:
USED_REX (REX_W);
@@ -14082,6 +14082,7 @@ intel_operand_size (int bytemode, int si
abort ();
oappend ("WORD PTR ");
break;
+ case v_bnd_mode:
default:
break;
}
@@ -14121,6 +14122,7 @@ OP_E_register (int bytemode, int sizefla
names = names64;
break;
case m_mode:
+ case v_bnd_mode:
names = address_mode == mode_64bit ? names64 : names32;
break;
case bnd_mode:
@@ -14135,7 +14137,6 @@ OP_E_register (int bytemode, int sizefla
bytemode = v_mode;
/* FALLTHRU */
case v_mode:
- case v_bnd_mode:
case v_swap_mode:
case dq_mode:
case dqb_mode:
--- 2013-10-07/opcodes/i386-opc.tbl
+++ 2013-10-07/opcodes/i386-opc.tbl
@@ -3061,14 +3061,17 @@ stac, 0, 0xf01, 0xcb, 2, CpuSMAP, No_bSu
bnd, 0, 0xf2, None, 1, CpuMPX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 }
// MPX instructions.
-bndmk, 2, 0xf30f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
-bndmov, 2, 0x660f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegBND, RegBND }
-bndmov, 2, 0x660f1b, None, 2, CpuMPX, S|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegBND, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegBND }
-bndcl, 2, 0xf30f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64|Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
-bndcu, 2, 0xf20f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64|Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
-bndcn, 2, 0xf20f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64|Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
-bndstx, 2, 0x0f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegBND, Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
-bndldx, 2, 0x0f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
+bndmk, 2, 0xf30f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Anysize|BaseIndex|Disp8|Disp32|Disp32S, RegBND }
+bndmov, 2, 0x660f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S|RegBND, RegBND }
+bndmov, 2, 0x660f1b, None, 2, CpuMPX, S|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegBND, Xmmword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S|RegBND }
+bndcl, 2, 0xf30f1a, None, 2, CpuMPX|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Anysize|BaseIndex|Disp8|Disp32, RegBND }
+bndcl, 2, 0xf30f1a, None, 2, CpuMPX|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg64|Anysize|BaseIndex|Disp8|Disp32|Disp32S, RegBND }
+bndcu, 2, 0xf20f1a, None, 2, CpuMPX|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Anysize|BaseIndex|Disp8|Disp32, RegBND }
+bndcu, 2, 0xf20f1a, None, 2, CpuMPX|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg64|Anysize|BaseIndex|Disp8|Disp32|Disp32S, RegBND }
+bndcn, 2, 0xf20f1b, None, 2, CpuMPX|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Anysize|BaseIndex|Disp8|Disp32, RegBND }
+bndcn, 2, 0xf20f1b, None, 2, CpuMPX|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg64|Anysize|BaseIndex|Disp8|Disp32|Disp32S, RegBND }
+bndstx, 2, 0x0f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegBND, Anysize|BaseIndex|Disp8|Disp32|Disp32S }
+bndldx, 2, 0x0f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Anysize|BaseIndex|Disp8|Disp32|Disp32S, RegBND }
// SHA instructions.
sha1rnds4, 3, 0xf3acc, None, 3, CpuSHA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
--- 2013-10-07/opcodes/i386-tbl.h
+++ 2013-10-07/opcodes/i386-tbl.h
@@ -53874,7 +53874,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0 },
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -53889,7 +53889,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0 },
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -53907,19 +53907,34 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 } } } },
{ "bndcl", 2, 0xf30f1a, None, 2,
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+ 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0 },
- { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ { { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } } } },
+ { "bndcl", 2, 0xf30f1a, None, 2,
+ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } },
+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
+ 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0 },
+ { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -53928,13 +53943,28 @@ const insn_template i386_optab[] =
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+ 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0 },
- { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ { { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } } } },
+ { "bndcu", 2, 0xf20f1a, None, 2,
+ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } },
+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
+ 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0 },
+ { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -53943,13 +53973,28 @@ const insn_template i386_optab[] =
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+ 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0 },
- { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ { { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } } } },
+ { "bndcn", 2, 0xf20f1b, None, 2,
+ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } },
+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
+ 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0 },
+ { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -53967,7 +54012,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } } } },
{ "bndldx", 2, 0x0f1a, None, 2,
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -53979,7 +54024,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0 },
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 5/6] x86/MPX: fix operand size handling
2013-10-10 13:14 ` Jan Beulich
@ 2013-10-10 15:14 ` H.J. Lu
2013-10-12 15:58 ` H.J. Lu
0 siblings, 1 reply; 33+ messages in thread
From: H.J. Lu @ 2013-10-10 15:14 UTC (permalink / raw)
To: Jan Beulich; +Cc: kirill.yukhin, Binutils
On Thu, Oct 10, 2013 at 6:14 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>> On 09.10.13 at 17:51, "H.J. Lu" <hjl.tools@gmail.com> wrote:
>> On Wed, Oct 9, 2013 at 12:36 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>>>> On 08.10.13 at 17:45, "H.J. Lu" <hjl.tools@gmail.com> wrote:
>>>> On Tue, Oct 8, 2013 at 7:43 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>>> All MPX instructions in 64-bit mode ignore REX.W, which means we neither
>>>>> need to encode this bit nor should disassemble with 32-bit register
>>>>> operands.
>>>>>
>>>>> No MPX instructions would ever take a 16-bit register operand.
>>>>>
>>>>> gas/
>>>>> 2013-10-08 Jan Beulich <jbeulich@suse.com>
>>>>>
>>>>> * tc-i386.c (process_suffix): Warn about 32-bit register operands
>>>>> to MPX instructions in 64-bit mode.
>>>>
>>>> I think it should be an error.
>>>
>>> I can certainly change that - a warning just seemed a better match
>>> to hardware ignoring operand size here.
>>
>> We can use separate entries with Reg32 for CpuNo64 and Reg64 for Cpu64,
>> similar to mov with debug registers. Let's do that instead.
>
> Here's the updated patch.
>
> Jan
>
> General purpose register operands of MPX instructions can only ever be
> native size ones.
>
> opcodes/
> 2013-10-08 Jan Beulich <jbeulich@suse.com>
>
> * i386-dis.c (intel_operand_size): Move v_bnd_mode alongside the
> default case.
> (OP_E_register): Move v_bnd_mode alongside m_mode.
> * i386-opc.tbl (bndcl, bndcu, bndcn): Split 32- and 64-bit variants.
> Drop Reg16 and Disp16. Add NoRex64.
> (bndmk, bndmov, bndldx, bndstx): Drop Disp16.
> * i386-tbl.h: Re-generate.
>
It is OK.
Thanks.
H.J.
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 2/6] x86/MPX: fix address size handling
2013-10-10 12:27 ` Jan Beulich
@ 2013-10-10 15:18 ` H.J. Lu
0 siblings, 0 replies; 33+ messages in thread
From: H.J. Lu @ 2013-10-10 15:18 UTC (permalink / raw)
To: Jan Beulich; +Cc: kirill.yukhin, Binutils
On Thu, Oct 10, 2013 at 5:27 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>> On 09.10.13 at 17:45, "H.J. Lu" <hjl.tools@gmail.com> wrote:
>> On Wed, Oct 9, 2013 at 12:30 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>>>> On 08.10.13 at 17:32, "H.J. Lu" <hjl.tools@gmail.com> wrote:
>>>> On Tue, Oct 8, 2013 at 8:20 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>>>>>> On 08.10.13 at 17:15, "H.J. Lu" <hjl.tools@gmail.com> wrote:
>>>>>> On Tue, Oct 8, 2013 at 7:41 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>>>>> While address overrides are ignored in 64-bit mode (and hence shouldn't
>>>>>>> result in an error), trying to use 16-bit addressing is documented to
>>>>>>> result in #UD, and hence the assembler should reject the attempt.
>>>>>>>
>>>>>>> gas/
>>>>>>> 2013-10-08 Jan Beulich <jbeulich@suse.com>
>>>>>>>
>>>>>>> * tc-i386.c (md_assemble): Alter address size checking for MPX
>>>>>>> instructions.
>>>>>>>
>>>>>>> --- 2013-10-07/gas/config/tc-i386.c
>>>>>>> +++ 2013-10-07/gas/config/tc-i386.c
>>>>>>> @@ -3549,10 +3549,15 @@ md_assemble (char *line)
>>>>>>> if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
>>>>>>> as_bad (_("expecting valid branch instruction after `bnd'"));
>>>>>>>
>>>>>>> - if (i.tm.cpu_flags.bitfield.cpumpx
>>>>>>> - && flag_code == CODE_64BIT
>>>>>>> - && i.prefix[ADDR_PREFIX])
>>>>>>> - as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
>>>>>>
>>>>>> It is done on purpose. When 32-bit address prefix in 64-bit is ignored,
>>>>>> MPX doesn't work correctly for x32.
>>>>>
>>>>> I don't understand: It _is_ being ignored by the hardware as per
>>>>> the documentation. So x32 need to get along with that. Maybe
>>>>> an example would help, so I could understand why you think
>>>>> this _needs_ to be an error...
>>>>>
>>>>
>>>> X32 won't work with MPX since hardware assumes pointer
>>>> size is always 64 bit in 64-bit mode with or without address
>>>> size prefix. MPX depends on correct pointer size to work.
>>>> I don't want people to use MPX in x32 by accident.
>>>
>>> This seems even more odd - why would x32 be excluded from
>>> using MPX? Again - an example might help, as my understanding
>>> so far was that the implicit zero extension of results of 32-bit
>>> operations should guarantee the half width pointers to be quite
>>> fine to use as full width values (i.e. in other memory operands
>>> I don't see why you would want to use 32-bit addressing either,
>>> except when the wraparound case matters, as might e.g. be
>>> the case with EIP-relative addressing).
>>
>> In 64-bit mode, bndldx and bndstx ignore the lower 3 bits of
>> the address of a pointer, which is OK when pointers are
>> 64-bit aligned. X32 runs in 64-bit mode. But pointers are
>> 32-bit aligned. That means 2 pointers may point to the same
>> bound table entry. That is why MPX won't work for x32 and
>> assembler shouldn't allow it.
>
> Here you're making assumptions that you can't control. For
> example, there's nothing preventing anyone to create a
> compiler/library pair that guarantees objects to be at least 8
> bytes apart. And that's leaving aside that even in full 64-bit
> mode there can be multiple objects within an 8-byte range.
>
It won't work with
struct foo
{
void *x;
void *y;
void *z;
void *p;
};
nor
int *foo[20];
2 pointers will share the same bound table entry.
--
H.J.
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 5/6] x86/MPX: fix operand size handling
2013-10-10 15:14 ` H.J. Lu
@ 2013-10-12 15:58 ` H.J. Lu
2013-10-12 17:12 ` H.J. Lu
0 siblings, 1 reply; 33+ messages in thread
From: H.J. Lu @ 2013-10-12 15:58 UTC (permalink / raw)
To: Jan Beulich; +Cc: kirill.yukhin, Binutils
On Thu, Oct 10, 2013 at 8:14 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
> On Thu, Oct 10, 2013 at 6:14 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>>> On 09.10.13 at 17:51, "H.J. Lu" <hjl.tools@gmail.com> wrote:
>>> On Wed, Oct 9, 2013 at 12:36 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>>>>> On 08.10.13 at 17:45, "H.J. Lu" <hjl.tools@gmail.com> wrote:
>>>>> On Tue, Oct 8, 2013 at 7:43 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>>>> All MPX instructions in 64-bit mode ignore REX.W, which means we neither
>>>>>> need to encode this bit nor should disassemble with 32-bit register
>>>>>> operands.
>>>>>>
>>>>>> No MPX instructions would ever take a 16-bit register operand.
>>>>>>
>>>>>> gas/
>>>>>> 2013-10-08 Jan Beulich <jbeulich@suse.com>
>>>>>>
>>>>>> * tc-i386.c (process_suffix): Warn about 32-bit register operands
>>>>>> to MPX instructions in 64-bit mode.
>>>>>
>>>>> I think it should be an error.
>>>>
>>>> I can certainly change that - a warning just seemed a better match
>>>> to hardware ignoring operand size here.
>>>
>>> We can use separate entries with Reg32 for CpuNo64 and Reg64 for Cpu64,
>>> similar to mov with debug registers. Let's do that instead.
>>
>> Here's the updated patch.
>>
>> Jan
>>
>> General purpose register operands of MPX instructions can only ever be
>> native size ones.
>>
>> opcodes/
>> 2013-10-08 Jan Beulich <jbeulich@suse.com>
>>
>> * i386-dis.c (intel_operand_size): Move v_bnd_mode alongside the
>> default case.
>> (OP_E_register): Move v_bnd_mode alongside m_mode.
>> * i386-opc.tbl (bndcl, bndcu, bndcn): Split 32- and 64-bit variants.
>> Drop Reg16 and Disp16. Add NoRex64.
>> (bndmk, bndmov, bndldx, bndstx): Drop Disp16.
>> * i386-tbl.h: Re-generate.
>>
>
> It is OK.
>
I checked it in with testcase updates.
Thanks.
--
H.J.
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 5/6] x86/MPX: fix operand size handling
2013-10-12 15:58 ` H.J. Lu
@ 2013-10-12 17:12 ` H.J. Lu
0 siblings, 0 replies; 33+ messages in thread
From: H.J. Lu @ 2013-10-12 17:12 UTC (permalink / raw)
To: Jan Beulich; +Cc: kirill.yukhin, Binutils
On Sat, Oct 12, 2013 at 8:58 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
> On Thu, Oct 10, 2013 at 8:14 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
>> On Thu, Oct 10, 2013 at 6:14 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>>>> On 09.10.13 at 17:51, "H.J. Lu" <hjl.tools@gmail.com> wrote:
>>>> On Wed, Oct 9, 2013 at 12:36 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>>>>>> On 08.10.13 at 17:45, "H.J. Lu" <hjl.tools@gmail.com> wrote:
>>>>>> On Tue, Oct 8, 2013 at 7:43 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>>>>> All MPX instructions in 64-bit mode ignore REX.W, which means we neither
>>>>>>> need to encode this bit nor should disassemble with 32-bit register
>>>>>>> operands.
>>>>>>>
>>>>>>> No MPX instructions would ever take a 16-bit register operand.
>>>>>>>
>>>>>>> gas/
>>>>>>> 2013-10-08 Jan Beulich <jbeulich@suse.com>
>>>>>>>
>>>>>>> * tc-i386.c (process_suffix): Warn about 32-bit register operands
>>>>>>> to MPX instructions in 64-bit mode.
>>>>>>
>>>>>> I think it should be an error.
>>>>>
>>>>> I can certainly change that - a warning just seemed a better match
>>>>> to hardware ignoring operand size here.
>>>>
>>>> We can use separate entries with Reg32 for CpuNo64 and Reg64 for Cpu64,
>>>> similar to mov with debug registers. Let's do that instead.
>>>
>>> Here's the updated patch.
>>>
>>> Jan
>>>
>>> General purpose register operands of MPX instructions can only ever be
>>> native size ones.
>>>
>>> opcodes/
>>> 2013-10-08 Jan Beulich <jbeulich@suse.com>
>>>
>>> * i386-dis.c (intel_operand_size): Move v_bnd_mode alongside the
>>> default case.
>>> (OP_E_register): Move v_bnd_mode alongside m_mode.
>>> * i386-opc.tbl (bndcl, bndcu, bndcn): Split 32- and 64-bit variants.
>>> Drop Reg16 and Disp16. Add NoRex64.
>>> (bndmk, bndmov, bndldx, bndstx): Drop Disp16.
>>> * i386-tbl.h: Re-generate.
>>>
>>
>> It is OK.
>>
>
> I checked it in with testcase updates.
>
> Thanks.
>
I also checked it into 2.24 branch.
--
H.J.
^ permalink raw reply [flat|nested] 33+ messages in thread
end of thread, other threads:[~2013-10-12 17:12 UTC | newest]
Thread overview: 33+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2013-10-08 14:36 [PATCH 0/6] x86: various MPX fixes Jan Beulich
2013-10-08 14:41 ` [PATCH 2/6] x86/MPX: fix address size handling Jan Beulich
2013-10-08 15:15 ` H.J. Lu
2013-10-08 15:20 ` Jan Beulich
2013-10-08 15:32 ` H.J. Lu
2013-10-09 7:30 ` Jan Beulich
2013-10-09 15:45 ` H.J. Lu
2013-10-10 12:27 ` Jan Beulich
2013-10-10 15:18 ` H.J. Lu
2013-10-08 14:41 ` [PATCH 1/6] x86/MPX: testsuite adjustments Jan Beulich
2013-10-08 14:42 ` [PATCH 3/6] x86/MPX: suppress base/index swapping in Intel mode for bndmk, bndldx, and bndstx Jan Beulich
2013-10-08 15:16 ` H.J. Lu
2013-10-08 15:23 ` Jan Beulich
2013-10-08 15:34 ` H.J. Lu
2013-10-08 16:00 ` Jan Beulich
2013-10-08 16:19 ` H.J. Lu
2013-10-09 7:15 ` acceptance rules (was: Re: [PATCH 3/6] x86/MPX: suppress base/index swapping ...) Jan Beulich
2013-10-09 16:45 ` H.J. Lu
2013-10-08 14:43 ` [PATCH 5/6] x86/MPX: fix operand size handling Jan Beulich
2013-10-08 15:45 ` H.J. Lu
2013-10-09 7:36 ` Jan Beulich
2013-10-09 15:51 ` H.J. Lu
2013-10-10 13:14 ` Jan Beulich
2013-10-10 15:14 ` H.J. Lu
2013-10-12 15:58 ` H.J. Lu
2013-10-12 17:12 ` H.J. Lu
2013-10-08 14:43 ` [PATCH 4/6] x86/MPX: bndmk, bndldx, and bndstx only allow a memory operand Jan Beulich
2013-10-08 15:28 ` H.J. Lu
2013-10-09 7:24 ` Jan Beulich
2013-10-09 15:17 ` H.J. Lu
2013-10-08 14:44 ` [PATCH 6/6] x86/MPX: bndmk, bndldx, and bndstx don't allow RIP-relative addressing Jan Beulich
2013-10-08 16:13 ` H.J. Lu
2013-10-09 7:40 ` Jan Beulich
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