From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oa1-x29.google.com (mail-oa1-x29.google.com [IPv6:2001:4860:4864:20::29]) by sourceware.org (Postfix) with ESMTPS id C50C03858423 for ; Wed, 30 Nov 2022 00:01:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org C50C03858423 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-oa1-x29.google.com with SMTP id 586e51a60fabf-1432a5f6468so19113373fac.12 for ; Tue, 29 Nov 2022 16:01:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=jlWvXmiLHeTvmV5WG10KTub0F6ymZhKxwNtPJ3xxR3w=; b=IpiWboBQEeYJz1hdmrqaxZyeovAd09XWJy39bIXZUaSz+L0l/12QOLus7OYiUxy23L Ol6phvjqo/+3SvRqBoA/NNit/SBTT9eBhJPb3Wn3w1EGYGQC/gSCbR5A1x/dRNbgVhIy u7uG/0WDlXKQjN1F8yqz+40fX8EjOqzNW41olKrq5CO8yjvH8WjM56EI9qvB3gw1D+Vr PxtJNw3HV8QgN4e7rHQyBUhcZtYaArNVjIwb7fdI9ad6MXmU/JARt/F59y2VceAt8/tz 5wscS4rz0tELAuaQelG+unB9Jv0cOPQ/mdYx0pNw69FzwKvKaImBWRujcW8QfvFjCHqk 4A3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=jlWvXmiLHeTvmV5WG10KTub0F6ymZhKxwNtPJ3xxR3w=; b=Qj1SFBiHwjVeL09buwUdIJLemw1qjhjF8ScLiODY9C/pXpDtMiRLvlGyth2ZGJJBt0 n0WsV5WfbgVm2TbZe2mCs8IAaeR5SWmHrRyju+THBNATw38RykFQfW7yoZ+Pz53bFt8/ ME7N1kRrblcolOcqf3yXvw9106S/RKLOFD73MZf7ft8RfpTtk3VFIXmFxzf4VjPnL8zM hfXPwknfj5Iia48NzOVALBGf4QodY81Z0xYskP6GuvR1kXNcIX9L3zktoKMIQA3Uizv/ /6t1voC6qZegjLsx03uP1QxyfVRXF0Qyi+eRqZlIZbSUj2UkJSu8Zu7pj+RGaK21A6Ss MqGA== X-Gm-Message-State: ANoB5pm17y2mkweWcb/O7hCh5CfZuVWVyeFnPS8Qbt2Y3sGw5n+6J9As 5cJBWEpBQ+BndA82wGwS9PvoTtzNEpTka/spWTO+OZYT X-Google-Smtp-Source: AA0mqf74Pn2A6NoZFzBEuusMh497aj3MYIs694aO1zQzX8iLJJSIpiNLKNkFIyCwVLX+kaYHREMCBUutCRDdtAXbiVk= X-Received: by 2002:a05:6871:4501:b0:13c:5da4:7229 with SMTP id nj1-20020a056871450100b0013c5da47229mr26808356oab.266.1669766490157; Tue, 29 Nov 2022 16:01:30 -0800 (PST) MIME-Version: 1.0 References: <5dd8b2df-62f2-a551-4b35-f3df66d57e04@suse.com> In-Reply-To: <5dd8b2df-62f2-a551-4b35-f3df66d57e04@suse.com> From: "H.J. Lu" Date: Tue, 29 Nov 2022 16:00:54 -0800 Message-ID: Subject: Re: [PATCH 3/3] x86: clean up after removal of support for gcc <= 2.8.1 To: Jan Beulich Cc: Binutils Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-3016.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,KAM_NUMSUBJECT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Thu, Nov 24, 2022 at 12:58 AM Jan Beulich wrote: > > At the very least a comment in process_operands() is stale. Beyond that > there are effectively two options: > 1) It is possible that FADDP and FMULP were mistakenly not marked as > being in need of dealing with the compiler anomaly, and hence the > respective templates weren't removed at the time when they should > have been. > 2) It is also possible that there are indeed uses known beyond compiler > generated output for these two commutative opcodes, and hence the > templates need to stay. > To be on the safe side assume 2: Update the comment and fold the > templates into their "normal" ones (utilizing D), adjusting consuming > code accordingly. > > For FMULP also add a comment paralleling a similar one FADDP has. > > --- a/gas/config/tc-i386.c > +++ b/gas/config/tc-i386.c > @@ -6806,7 +6806,8 @@ match_template (char mnem_suffix) > found_reverse_match = 0; > else if (operand_types[0].bitfield.tbyte) > { > - found_reverse_match = Opcode_FloatD; > + if (t->opcode_modifier.operandconstraint != UGH) > + found_reverse_match = Opcode_FloatD; > /* FSUB{,R} and FDIV{,R} may need a 2nd bit flipped. */ > if ((t->base_opcode & 0x20) > && (intel_syntax || intel_mnemonic)) > @@ -7997,29 +7998,31 @@ process_operands (void) > { > /* The register or float register operand is in operand > 0 or 1. */ > - unsigned int op = i.tm.operand_types[0].bitfield.class != Reg; > + const reg_entry *r = i.op[0].regs; > > + if (i.imm_operands > + || (r->reg_type.bitfield.instance == Accum && i.op[1].regs)) > + r = i.op[1].regs; > /* Register goes in low 3 bits of opcode. */ > - i.tm.base_opcode |= i.op[op].regs->reg_num; > - if ((i.op[op].regs->reg_flags & RegRex) != 0) > + i.tm.base_opcode |= r->reg_num; > + if ((r->reg_flags & RegRex) != 0) > i.rex |= REX_B; > if (!quiet_warnings && i.tm.opcode_modifier.operandconstraint == UGH) > { > - /* Warn about some common errors, but press on regardless. > - The first case can be generated by gcc (<= 2.8.1). */ > - if (i.operands == 2) > - { > - /* Reversed arguments on faddp, fsubp, etc. */ > - as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name, > - register_prefix, i.op[!intel_syntax].regs->reg_name, > - register_prefix, i.op[intel_syntax].regs->reg_name); > - } > - else > + /* Warn about some common errors, but press on regardless. */ > + if (i.operands != 2) > { > /* Extraneous `l' suffix on fp insn. */ > as_warn (_("translating to `%s %s%s'"), i.tm.name, > register_prefix, i.op[0].regs->reg_name); > } > + else if (i.op[0].regs->reg_type.bitfield.instance != Accum) > + { > + /* Reversed arguments on faddp or fmulp. */ > + as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name, > + register_prefix, i.op[!intel_syntax].regs->reg_name, > + register_prefix, i.op[intel_syntax].regs->reg_name); > + } > } > } > > --- a/opcodes/i386-opc.tbl > +++ b/opcodes/i386-opc.tbl > @@ -686,11 +686,10 @@ fadd, 0xdec1, None, CpuFP, NoSuf|Ugh|ATT > fadd, 0xd8, 0, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex } > fiadd, 0xde, 0, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex } > > -faddp, 0xdec0, None, CpuFP, NoSuf, { FloatAcc, FloatReg } > +faddp, 0xdec0, None, CpuFP, D|NoSuf|Ugh, { FloatAcc, FloatReg } > faddp, 0xdec0, None, CpuFP, NoSuf, { FloatReg } > // alias for faddp %st, %st(1) > faddp, 0xdec1, None, CpuFP, NoSuf, {} > -faddp, 0xdec0, None, CpuFP, NoSuf|Ugh, { FloatReg, FloatAcc } > > // subtract > fsub, 0xd8e0, None, CpuFP, NoSuf, { FloatReg } > @@ -732,10 +731,10 @@ fmul, 0xdec9, None, CpuFP, NoSuf|Ugh|ATT > fmul, 0xd8, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex } > fimul, 0xde, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex } > > -fmulp, 0xdec8, None, CpuFP, NoSuf, { FloatAcc, FloatReg } > +fmulp, 0xdec8, None, CpuFP, D|NoSuf|Ugh, { FloatAcc, FloatReg } > fmulp, 0xdec8, None, CpuFP, NoSuf, { FloatReg } > +// alias for fmulp %st, %st(1) > fmulp, 0xdec9, None, CpuFP, NoSuf, {} > -fmulp, 0xdec8, None, CpuFP, NoSuf|Ugh, { FloatReg, FloatAcc } > > // divide > fdiv, 0xd8f0, None, CpuFP, NoSuf, { FloatReg } > OK. Thanks. -- H.J.