From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 23685 invoked by alias); 8 Oct 2013 15:45:28 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 23666 invoked by uid 89); 8 Oct 2013 15:45:27 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-1.3 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-ob0-f180.google.com Received: from mail-ob0-f180.google.com (HELO mail-ob0-f180.google.com) (209.85.214.180) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Tue, 08 Oct 2013 15:45:25 +0000 Received: by mail-ob0-f180.google.com with SMTP id wn1so601794obc.25 for ; Tue, 08 Oct 2013 08:45:24 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.182.237.75 with SMTP id va11mr1706454obc.5.1381247123988; Tue, 08 Oct 2013 08:45:23 -0700 (PDT) Received: by 10.76.110.15 with HTTP; Tue, 8 Oct 2013 08:45:23 -0700 (PDT) In-Reply-To: <5254364802000078000F9A5D@nat28.tlf.novell.com> References: <5254349502000078000F9A3D@nat28.tlf.novell.com> <5254364802000078000F9A5D@nat28.tlf.novell.com> Date: Tue, 08 Oct 2013 15:45:00 -0000 Message-ID: Subject: Re: [PATCH 5/6] x86/MPX: fix operand size handling From: "H.J. Lu" To: Jan Beulich Cc: kirill.yukhin@intel.com, Binutils Content-Type: text/plain; charset=ISO-8859-1 X-IsSubscribed: yes X-SW-Source: 2013-10/txt/msg00084.txt.bz2 On Tue, Oct 8, 2013 at 7:43 AM, Jan Beulich wrote: > All MPX instructions in 64-bit mode ignore REX.W, which means we neither > need to encode this bit nor should disassemble with 32-bit register > operands. > > No MPX instructions would ever take a 16-bit register operand. > > gas/ > 2013-10-08 Jan Beulich > > * tc-i386.c (process_suffix): Warn about 32-bit register operands > to MPX instructions in 64-bit mode. I think it should be an error. > opcodes/ > 2013-10-08 Jan Beulich > > * i386-dis.c (intel_operand_size): Move v_bnd_mode alongside the > default case. > (OP_E_register): Move v_bnd_mode alongside m_mode. > * i386-opc.h (REGNAM_RAX): New. > * i386-opc.tbl (bndcl, bndcu, bndcn): Drop Reg16. Add NoRex64. > * i386-tbl.h: Re-generate. > Should we also remove Disp16? -- H.J.