From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qt1-x831.google.com (mail-qt1-x831.google.com [IPv6:2607:f8b0:4864:20::831]) by sourceware.org (Postfix) with ESMTPS id 046D738582B8 for ; Tue, 11 Oct 2022 17:51:08 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 046D738582B8 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-qt1-x831.google.com with SMTP id g11so4097953qts.1 for ; Tue, 11 Oct 2022 10:51:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=0DInBjVfKsp/rAvYti5RlE9TGsMwt9W09yzNspNDrZQ=; b=f9ThnlDhLDcGsc9VhNmCYc+9uWCtu/MSOTR8BmQBiys0B5xj4esMlJ9pKwvOkDwlWf RpwaTknYkRmT7n2ho1nQfSXnVKxU2IBVrT18TN2YTbpLQ9cVNh0/F1jrfvP+rxHrGXpA 3lssFuqrEPj340YwgmLpA6lYTyAQMnh7u2IGvdQGxw9HuN5L9dA5X+3QHEAWPmxui3jK +ERHzgcNCqybcJdwEMk9nsF1du1MRP0C/eqMBionVmolcrRpi/ssUTVPRtZ3jakm4IWt NKw4CJqt4EQzpC61SHx4DftZO3NW+4+7jxNc8Xgfpc8s0w4voAyq65Q4va16OG3G6uyg sJQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=0DInBjVfKsp/rAvYti5RlE9TGsMwt9W09yzNspNDrZQ=; b=FyrkXqtjhWT7/rma+UaayBPsRWIpGBiNv/kMM+sP24n1Q5H75VAkBVCaJa5k2dG0QZ FMtomvGDaVjcOpd5jJazq2mw4kZwWG8SGUMZo5yHNt2lMbwCFkQhxddbQZHe4mo2S9oO j74A5oPQTXQFZxEI1xSUdGpzpeHFuF1qeCJguDhcCx6+YA6WrhdnXsUYAE+s/d5phnzB FjYhnusyl1TGEh1vtOoLcUZiCWxYL/uYDCnfCIbjmQnJWojwAlVo0HZgqzYs4hOOFRfJ LCJtma3EV+HcS647ijdrteiR4ei6/L+GbJHMEPI0kFSNo5erbc9cxwLamdfsQCu8hkCJ Sj+g== X-Gm-Message-State: ACrzQf0fClFb7GP8vNdtR4jn+W53u+uN4PsNF5FpuUmBZdXDd9WdzHYD b/yPLX0wRfSvWrHD2GxVsRcCeBSw70hDc9l56zk= X-Google-Smtp-Source: AMsMyM7QxKEoo83wIHLOmm+wtgWukgl/EN2bNm9JiMLyumamC5iJO8gAYOpzOZSPgZIjS/J9yDaATMBs1EFBPZFoVaY= X-Received: by 2002:ac8:5c02:0:b0:39a:bf28:81d7 with SMTP id i2-20020ac85c02000000b0039abf2881d7mr7832971qti.437.1665510666826; Tue, 11 Oct 2022 10:51:06 -0700 (PDT) MIME-Version: 1.0 References: <1266f001-4511-2662-dba9-14b4d0317c57@suse.com> In-Reply-To: <1266f001-4511-2662-dba9-14b4d0317c57@suse.com> From: "H.J. Lu" Date: Tue, 11 Oct 2022 10:50:30 -0700 Message-ID: Subject: Re: [PATCH] x86: drop "regmask" static variable To: Jan Beulich Cc: Binutils Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-3018.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Wed, Oct 5, 2022 at 12:40 AM Jan Beulich wrote: > > Replace its two uses by more direct checks, paralleling what's already > there for SIMD registers. > > --- a/gas/config/tc-i386.c > +++ b/gas/config/tc-i386.c > @@ -1907,7 +1907,6 @@ operand_type_xor (i386_operand_type x, i > static const i386_operand_type anydisp = OPERAND_TYPE_ANYDISP; > static const i386_operand_type anyimm = OPERAND_TYPE_ANYIMM; > static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM; > -static const i386_operand_type regmask = OPERAND_TYPE_REGMASK; > static const i386_operand_type imm8 = OPERAND_TYPE_IMM8; > static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S; > static const i386_operand_type imm16 = OPERAND_TYPE_IMM16; > @@ -8190,7 +8189,7 @@ if(flag_debug) fprintf(stderr, "%s: imm= > || ((op.bitfield.class != Reg > || (!op.bitfield.dword && !op.bitfield.qword)) > && op.bitfield.class != RegSIMD > - && !operand_type_equal (&op, ®mask))) > + && op.bitfield.class != RegMask)) > abort (); > i.vex.register_specifier = i.op[vvvv].regs; > dest++; > @@ -8601,7 +8600,7 @@ if(flag_debug) fprintf(stderr, "%s: imm= > if ((type->bitfield.class != Reg > || (!type->bitfield.dword && !type->bitfield.qword)) > && type->bitfield.class != RegSIMD > - && !operand_type_equal (type, ®mask)) > + && type->bitfield.class != RegMask) > abort (); > > i.vex.register_specifier = i.op[vex_reg].regs; OK. Thanks. -- H.J.