From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 107481 invoked by alias); 12 May 2015 12:37:20 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 107150 invoked by uid 89); 12 May 2015 12:37:19 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.5 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-ob0-f182.google.com Received: from mail-ob0-f182.google.com (HELO mail-ob0-f182.google.com) (209.85.214.182) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Tue, 12 May 2015 12:37:16 +0000 Received: by obfe9 with SMTP id e9so4150889obf.1 for ; Tue, 12 May 2015 05:37:14 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.182.56.196 with SMTP id c4mr12063490obq.26.1431434234732; Tue, 12 May 2015 05:37:14 -0700 (PDT) Received: by 10.76.54.14 with HTTP; Tue, 12 May 2015 05:37:14 -0700 (PDT) In-Reply-To: <55520C440200007800079718@mail.emea.novell.com> References: <20150511212331.GA1838@intel.com> <5551F4E70200007800079575@mail.emea.novell.com> <55520C440200007800079718@mail.emea.novell.com> Date: Tue, 12 May 2015 12:37:00 -0000 Message-ID: Subject: Re: [committed, PATCH] Remove Disp16|Disp32 from 64-bit direct branches From: "H.J. Lu" To: Jan Beulich Cc: Binutils Content-Type: text/plain; charset=UTF-8 X-IsSubscribed: yes X-SW-Source: 2015-05/txt/msg00081.txt.bz2 On Tue, May 12, 2015 at 5:20 AM, Jan Beulich wrote: >>>> On 12.05.15 at 13:54, wrote: >> On Tue, May 12, 2015 at 3:41 AM, Jan Beulich wrote: >>>>>> On 11.05.15 at 23:23, wrote: >>>> Disp16 and Disp32 aren't supported by direct branches in 64-bit mode. >>>> This patch removes them from 64-bit direct branches. >>> >>> See the recent discussion regarding callw - these can certainly have >>> 16-bit displacements on AMD CPUs. And while disassembly may just >>> get "disturbed" by getting this wrong, assembly will produce bad >>> code if you don't account for both cases (or refuse to assemble >>> such mnemonics if they would require size overrides to be added). >>> >>> Apart from that I wonder why you do this for CALL and JMP, but not >>> for Jcc, JCXZ, JRCXZ, LOOP, and LOOPcc. >>> >>> But first of all - please don't bias x86 binutils towards only supporting >>> Intel hardware. >> >> Can you generate call/jmp with 16-bit displacement in 64-bit mode? > > Didn't check whether there is a mechanism currently; of course I > would expect "data16 jmp