From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 96278 invoked by alias); 17 Feb 2020 01:20:18 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 96270 invoked by uid 89); 17 Feb 2020 01:20:18 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-14.7 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,KAM_NUMSUBJECT,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: mail-ot1-f65.google.com Received: from mail-ot1-f65.google.com (HELO mail-ot1-f65.google.com) (209.85.210.65) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 17 Feb 2020 01:20:16 +0000 Received: by mail-ot1-f65.google.com with SMTP id l2so8343012otp.4 for ; Sun, 16 Feb 2020 17:20:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=gw346wSQrHqp/PA53vbKF8KvXU8L3cSrkVtjjTRsEHM=; b=WIvfZ350lE9Qes10flWkBUZ2Hd/yQxR4NkndK/Ag3+gy291Ctj39H7USWa43yzRxiQ 5e7gJ75/17/TqOZCgUArzJ32yZUOtwhDzrarP4PGDB5QFeGwm3kpv7B9QZETLvaOy2Wf K28ct0YWi4ghZzN0Y3RuYt39cVd9u5AYdL0Bq97QJxEbSCXbwHxJMIUfggKwmmK4su7C tfHJojUEAGL5hupl/KtWv002K7ToVlp46jDasPiTrqYMvdIwAa8qsUltLvETe3bQqiYg 2A6mNH1k4WYt/+dbb3Wis2dF7G+NBls7p1fVc+HW2YzHsn6PooilQT4OaAUeEj9qE7k7 cm5A== MIME-Version: 1.0 References: <3bc597bb-10f9-80f9-8e00-f28aeb2eea77@suse.com> <20200217010628.GA5570@bubble.grove.modra.org> In-Reply-To: <20200217010628.GA5570@bubble.grove.modra.org> From: "H.J. Lu" Date: Mon, 17 Feb 2020 01:20:00 -0000 Message-ID: Subject: Re: [committed, PATCH] x86: Don't disable SSE4a when disabling SSE4 To: Alan Modra Cc: Jan Beulich , "binutils@sourceware.org" Content-Type: text/plain; charset="UTF-8" X-IsSubscribed: yes X-SW-Source: 2020-02/txt/msg00386.txt.bz2 On Sun, Feb 16, 2020 at 5:06 PM Alan Modra wrote: > > On Sun, Feb 16, 2020 at 08:47:56AM -0800, H.J. Lu wrote: > > commit 7deea9aad8 changed nosse4 to include CpuSSE4a. But AMD SSE4a is > > a superset of SSE3 and Intel SSE4 is a superset of SSSE3. Disable Intel > > SSE4 shouldn't disable AMD SSE4a. This patch restores nosse4. It also > > adds .sse4a and nosse4a. > > diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c > index 79f4cc9d25..45106bcf6d 100644 > --- a/opcodes/i386-gen.c > +++ b/opcodes/i386-gen.c > @@ -326,6 +326,8 @@ static initializer cpu_flag_init[] = > { "CPU_ANY_SSE2_FLAGS", > "CPU_ANY_SSE3_FLAGS|CpuSSE2" }, > { "CPU_ANY_SSE3_FLAGS", > + { "CPU_ANY_SSE4A_FLAGS", > + "CPU_ANY_SSE3_FLAGS|CpuSSE4a" }, > "CPU_ANY_SSSE3_FLAGS|CpuSSE3|CpuSSE4a" }, > { "CPU_ANY_SSSE3_FLAGS", > "CPU_ANY_SSE4_1_FLAGS|CpuSSSE3" }, > @@ -333,8 +335,6 @@ static initializer cpu_flag_init[] = > "CPU_ANY_SSE4_2_FLAGS|CpuSSE4_1" }, > { "CPU_ANY_SSE4_2_FLAGS", > "CpuSSE4_2" }, > - { "CPU_ANY_SSE4_FLAGS", > - "CPU_ANY_SSE4_1_FLAGS|CpuSSE4a" }, > { "CPU_ANY_AVX_FLAGS", > "CPU_ANY_AVX2_FLAGS|CpuF16C|CpuFMA|CpuFMA4|CpuXOP|CpuAVX" }, > { "CPU_ANY_AVX2_FLAGS", > > Merge error? Is there anything wrong? -- H.J.