From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ej1-x62c.google.com (mail-ej1-x62c.google.com [IPv6:2a00:1450:4864:20::62c]) by sourceware.org (Postfix) with ESMTPS id 94A453852C4A for ; Thu, 17 Nov 2022 19:52:03 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 94A453852C4A Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ej1-x62c.google.com with SMTP id ud5so7808599ejc.4 for ; Thu, 17 Nov 2022 11:52:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=zwgrZau3ZyGzc4zxVRiV/J/zmbtuW9SQPjjaJedHAnw=; b=SVd3qMxVvi2n4HjbCQWbE9hM3OKbvFwArQPjeJmy+S5rl7I+Ewg26/KWXaqaShA5WI zfBx+UYpgQ4i1tDzYh6n7TPjDeRxJ5MU7X+Z1r583ElccVCN5Wr+JU2+XigxXmQgtx2i Uv7Mw+Elfig500ctcCDrHBRmv72hEglqeH697lqfJA3qns+PrLGohhsaILE56ORN4mtF PePwPgFROJscncz5L8giCrlL0FH4Pe5nGkIhgD2TbOORmtjsqJi9OTdqM1Z49Rd/I5aO fYL1tlfzWRQ63RjjUqOjF1wjPwvM7uA2qvRTSCUNAc0/w2fgZfhH78X0QncSrwDzspvZ QHEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zwgrZau3ZyGzc4zxVRiV/J/zmbtuW9SQPjjaJedHAnw=; b=RGP7xl2KVP9KAMendH9d/PAcRjVI1Z5V0FBPMWLdJ0KIQJ+c1lvfDMW8XcO+vicfLd j6v8ina54A741Ow8tzuHpDwN1joo8DVInLHkdtvgVINGKBdEvFg2wnWAJUDqMo9Auz7G DHimrRKeT/qOZ64S7eKp7UZPjm54td/Eyzf3ghbr+Kqkuo1q3tr1XRlos4ioJi5JSbNy jYSwBD0xzQxKboXyWHz3+DPnUU0/I/Zi/rLCLIWYz1rkANXY2gT1PnaT7VIgudFImsOa Pd1lB5vwiYlzHAQclq3UENUMIM0yhIsfDPYwj6QHPfPKBcMGn13WLjjXUELlPcUm0z+V hwrA== X-Gm-Message-State: ANoB5pnapzoC92I2EtrjsoMMLSsyqWbONgKwjYcbt/qygZUxR15sWXHC OQFedEILBZOOm0DjV+us9pXuH1QY9TgyW/6EcoXiOpFR X-Google-Smtp-Source: AA0mqf5IIOLGKk4/515BLy3cwNe++W/QNoVchyQthHw3saQe091DGFj4lIm3xq80V4whZ+ToN/tLV7oZ47jIJwnDvRU= X-Received: by 2002:a17:906:2c51:b0:7b2:8c66:9bda with SMTP id f17-20020a1709062c5100b007b28c669bdamr3211646ejh.732.1668714722312; Thu, 17 Nov 2022 11:52:02 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: "H.J. Lu" Date: Thu, 17 Nov 2022 11:51:22 -0800 Message-ID: Subject: Re: [PATCH] binutils: partially revert 17c6c3b99156fe82c1e637e1a5fd9f163ac788c8 To: =?UTF-8?B?5b6Q5oyB5oGSIFh1IENoaWhlbmc=?= Cc: "binutils@sourceware.org" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-3015.9 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,KAM_LOTSOFHASH,KAM_NUMSUBJECT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Thu, Nov 17, 2022 at 11:29 AM =E5=BE=90=E6=8C=81=E6=81=92 Xu Chiheng wrote: > > In developing some kernel like program. It start as 32 bit mode, then swi= tch to 64 bit mode. All code are written in C++(only with inline assembly, = with no assembly file). > Please compile C++ code to assembly code and add .code32 to assembly codes to tell assembler to generate 32-bit instructions. > ________________________________ > From: H.J. Lu > Sent: Friday, November 18, 2022 03:11 > To: =E5=BE=90=E6=8C=81=E6=81=92 Xu Chiheng > Cc: binutils@sourceware.org > Subject: Re: [PATCH] binutils: partially revert 17c6c3b99156fe82c1e637e1a= 5fd9f163ac788c8 > > On Thu, Nov 17, 2022 at 11:01 AM =E5=BE=90=E6=8C=81=E6=81=92 Xu Chiheng <= chiheng.xu@gmail.com> wrote: > > > > binutils-2.36 and earlier works > > binutils-2.37 and later does not work. > > It worked by accident before. May I ask why you want to do it this way? > > > ________________________________ > > From: H.J. Lu > > Sent: Friday, November 18, 2022 02:50 > > To: =E5=BE=90=E6=8C=81=E6=81=92 Xu Chiheng > > Cc: binutils@sourceware.org > > Subject: Re: [PATCH] binutils: partially revert 17c6c3b99156fe82c1e637e= 1a5fd9f163ac788c8 > > > > On Thu, Nov 17, 2022 at 10:28 AM =E5=BE=90=E6=8C=81=E6=81=92 Xu Chiheng= wrote: > > > > > > No. not using NASM. > > > > > > using x86_64-elf-g++ -m32 to generate 32 bit code(elf32). > > > using x86_64-elf-objcopy to convert it to elf64. > > > then link the 32 bit code(elf64) with 64 bit code. > > > > > > > This is an unsupported operation. > > > > H.J. > > > > > > > > > ________________________________ > > > From: H.J. Lu > > > Sent: Friday, November 18, 2022 02:06 > > > To: =E5=BE=90=E6=8C=81=E6=81=92 Xu Chiheng > > > Cc: binutils@sourceware.org > > > Subject: Re: [PATCH] binutils: partially revert 17c6c3b99156fe82c1e63= 7e1a5fd9f163ac788c8 > > > > > > On Thu, Nov 17, 2022 at 9:44 AM =E5=BE=90=E6=8C=81=E6=81=92 Xu Chihen= g via Binutils > > > wrote: > > > > > > > > Phenomenal: In 32 bit and 64 bit mixed code, ld can't do relocati= on > > > > for 32 bit code. > > > > It is caused by commit 17c6c3b99156fe82c1e637e1a5fd9f163ac788c8. > > > > > > > > > > > > > > > > > > > > /* src_mask selects the part of the instruction (or data) to be u= sed > > > > in the relocation sum. If the target relocations don't have a= n > > > > addend in the reloc, eg. ELF USE_REL, src_mask will normally e= qual > > > > dst_mask to extract the addend from the section contents. If > > > > relocations do have an addend in the reloc, eg. ELF USE_RELA, = this > > > > field should normally be zero. Non-zero values for ELF USE_RE= LA > > > > targets should be viewed with suspicion as normally the value = in > > > > the dst_mask part of the section contents should be ignored. = */ > > > > bfd_vma src_mask; > > > > > > > > > > > > > > > > Author: Jan Beulich 2021-05-07 18:05:12 > > > > Committer: Jan Beulich 2021-05-07 18:05:12 > > > > Parent: 98da05bf2698b55b73453480a3fbb92f163d2c7b (x86: don't mix di= sp > > > > and imm processing) > > > > Child: 4cf88725da1cb503be04d3237354105ec170bc86 ([gdb/symtab] Fix > > > > infinite recursion in dwarf2_cu::get_builder()) > > > > Branches: master, test0558-01 and many more (41) > > > > Follows: gdb-10-branchpoint > > > > Precedes: binutils-2_37, gdb-11-branchpoint > > > > > > > > x86-64/ELF: clear src_mask for all reloc types > > > > > > > > x86-64 uses rela relocations. The comment next to the field's d= eclaration > > > > says "Non-zero values for ELF USE_RELA targets should be viewed= with > > > > suspicion ..." And indeed the fields being non-zero causes sect= ion > > > > contents to be accumulated into the final relocated values in a= ddition to > > > > the relocations' addends, which is contrary to the ELF spec. > > > > > > Are you using NASM? > > > > > > -- > > > H.J. > > > > > > > > -- > > H.J. > > > > -- > H.J. --=20 H.J.