From: "H.J. Lu" <hjl.tools@gmail.com>
To: Jan Beulich <jbeulich@suse.com>
Cc: "binutils@sourceware.org" <binutils@sourceware.org>
Subject: Re: [PATCH 1/9] x86: refine TPAUSE and UMWAIT
Date: Thu, 05 Mar 2020 14:05:00 -0000 [thread overview]
Message-ID: <CAMe9rOpdvye4eYAEPGTfpvMAHrN=pi4xtWo1VT29EPEcRocyYA@mail.gmail.com> (raw)
In-Reply-To: <6c6fdbc1-2de1-ec66-9c99-88f9cafde57c@suse.com>
On Thu, Mar 5, 2020 at 12:08 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 04.03.2020 12:44, H.J. Lu wrote:
> > On Wed, Mar 4, 2020 at 3:40 AM Jan Beulich <jbeulich@suse.com> wrote:
> >> On 04.03.2020 12:36, H.J. Lu wrote:
> >>> On Wed, Mar 4, 2020 at 1:37 AM Jan Beulich <jbeulich@suse.com> wrote:
> >>>> Allowing 64-bit registers is misleading here: Elsewhere these get allowed
> >>>> when there's no difference between either variant, because of 32-bit
> >>>> destination registers having their upper halves zeroed in 64-bit mode.
> >>>> Here, however, they're source registers, and hence specifying 64-bit
> >>>> registers would lead to the ambiguity of whether the upper 32 bits
> >>>> actually matter.
> >>>>
> >>>> Additionally, for proper code generation in 16-bit mode, IgnoreSize is
> >>>> needed on both.
> >>>
> >>> Are there testcases to show IgnoreSize is needed on them?
> >>
> >> The situation with 16-bit test cases is rather poor anyway. I didn't
> >> consider it reasonable to add such very special ones when far more
> >> general ones don't exist. But if your question is to mean you demand
> >
> > Let's start from somewhere.
> >
> >> such to be added, then I'll (somewhat hesitantly) add/extend some.
> >> Please clarify.
> >
> > Please add testcases.
>
> Actually they were there, in patch 2. I've moved them to this patch
> and have just sent v1.1 for just this one patch.
Do we need to adjust disassembler for 16-bit mode?
--
H.J.
next prev parent reply other threads:[~2020-03-05 14:05 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-04 9:32 [PATCH 0/9] x86: (mainly) misc IgnoreSize related adjustments Jan Beulich
2020-03-04 9:41 ` [PATCH 1/9] x86: refine TPAUSE and UMWAIT Jan Beulich
2020-03-04 11:37 ` H.J. Lu
2020-03-04 11:40 ` Jan Beulich
2020-03-04 11:44 ` H.J. Lu
2020-03-05 8:08 ` Jan Beulich
2020-03-05 14:05 ` H.J. Lu [this message]
2020-03-05 14:08 ` Jan Beulich
2020-03-05 14:38 ` H.J. Lu
2020-03-05 14:51 ` Jan Beulich
2020-03-05 14:54 ` H.J. Lu
2020-03-05 15:16 ` Jan Beulich
2020-03-05 15:22 ` Jan Beulich
2020-03-05 15:37 ` H.J. Lu
2020-03-05 15:42 ` Jan Beulich
2020-03-05 16:00 ` H.J. Lu
2020-03-04 9:42 ` [PATCH 2/9] x86: add missing IgnoreSize Jan Beulich
2020-03-04 11:40 ` H.J. Lu
2020-03-04 9:43 ` [PATCH 3/9] x86: correct MPX insn w/o base or index encoding in 16-bit mode Jan Beulich
2020-03-04 11:46 ` H.J. Lu
2020-03-04 11:50 ` Jan Beulich
2020-03-04 11:55 ` H.J. Lu
2020-03-04 12:58 ` Jan Beulich
2020-03-04 13:26 ` H.J. Lu
2020-03-04 9:44 ` [PATCH 4/9] x86: drop Rex64 attribute Jan Beulich
2020-03-04 11:47 ` H.J. Lu
2020-03-04 9:45 ` [PATCH 6/9] x86: don't accept FI{LD,STP,STTP}LL in Intel syntax mode Jan Beulich
2020-03-04 11:55 ` H.J. Lu
2020-03-04 9:46 ` [PATCH 7/9] x86: fold (supposed to be) identical code Jan Beulich
2020-03-04 11:56 ` H.J. Lu
2020-03-04 9:47 ` [PATCH 9/9] x86: reduce amount of various VCVT* templates Jan Beulich
2020-03-04 12:00 ` H.J. Lu
2020-03-04 10:15 ` [PATCH 8/9] x86: drop/replace IgnoreSize Jan Beulich
2020-03-04 11:59 ` H.J. Lu
2020-03-04 10:19 ` [PATCH 5/9] x86: replace NoRex64 on VEX-encoded insns Jan Beulich
2020-03-04 11:51 ` H.J. Lu
2020-03-05 8:07 ` [PATCH v1.1 1/9] x86: refine TPAUSE and UMWAIT Jan Beulich
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