From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf1-x435.google.com (mail-pf1-x435.google.com [IPv6:2607:f8b0:4864:20::435]) by sourceware.org (Postfix) with ESMTPS id B83293858D28 for ; Mon, 18 Jul 2022 14:45:24 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org B83293858D28 Received: by mail-pf1-x435.google.com with SMTP id b9so10802201pfp.10 for ; Mon, 18 Jul 2022 07:45:24 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=XRk8/tovOkNxSp1Hw7uj0+LWPFTkOzdD6/9PxiwxMyE=; b=LlrAyIAPMtxiHCJ61RsrPhqYh+oIHvxQ2Ydk6at0q7qJTVUFkoiryOzs0jCwFHsHnA 3L1CHinrsPtFpPOkcgUDL7Zlp1q9CjncVoSPPZOuZIHhDnlyCnliye6w/jEBZFRmntxJ AWY1feuX7MhYl1iNEYw42wUd7e6mwZRnCYExIsmOzkQup1E5Qyye7hyzeZtRiKJ/w+1m OFTxMZTNBl4yCLISm0MogVBRxwLJouYFgcnomUgUcv3teW30Yt9s/WfHH0i6qFK5hsOL 129uXKYPORPfYwDEg2l+WcxoQXYIiie/CX36UV0KLyx+gl5Tm1CKXLDfmFmT/Tf1X71y Fviw== X-Gm-Message-State: AJIora9tZ5lzrwxy7Lsj0Wzk3CPo8rLGUZyv4Zc2wLDKXFEjCoyIGzF3 LiErWVYAvNS6ETbTGE/sE6yJvMeSmUK+LYD3eaVZka8z X-Google-Smtp-Source: AGRyM1uKXEeorbuvkH6MvphJdygS5w1AKdYcBJ44RGCkAvp15oD1ITzhbC+ohydG0g45+75pqidfHdesq6ZLLx4nNBU= X-Received: by 2002:a05:6a00:14c5:b0:52b:8877:8263 with SMTP id w5-20020a056a0014c500b0052b88778263mr99499pfu.1.1658155522573; Mon, 18 Jul 2022 07:45:22 -0700 (PDT) MIME-Version: 1.0 References: <0833827c-9e81-56c9-6633-8cf1912b328e@suse.com> In-Reply-To: From: "H.J. Lu" Date: Mon, 18 Jul 2022 07:44:46 -0700 Message-ID: Subject: Re: [PATCH] x86: correct VMOVSH attributes To: Jan Beulich Cc: Binutils , Lili Cui Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-3018.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 18 Jul 2022 14:45:26 -0000 On Mon, Jul 18, 2022 at 2:23 AM Jan Beulich wrote: > > On 15.07.2022 19:49, H.J. Lu wrote: > > On Fri, Jul 15, 2022 at 3:01 AM Jan Beulich wrote: > >> > >> Both forms were missing VexW0 (thus allowing Evex.W=3D1 to be encoded = by > >> suitable means, which would cause #UD). The memory operand form furthe= r > >> was using the wrong Masking value, thus allowing zeroing-masking to be > >> encoded for the store form (which would again cause #UD). > >> > >> --- a/gas/testsuite/gas/i386/evex-wig.s > >> +++ b/gas/testsuite/gas/i386/evex-wig.s > >> @@ -62,6 +62,18 @@ _start: > >> {evex} vpinsrw $0, %eax, %xmm0, %xmm0 > >> {evex} vpinsrw $0, 2(%eax), %xmm0, %xmm0 > >> > >> + vmovss %xmm0, %xmm0, %xmm0{%k7} > >> + vmovss (%eax), %xmm0{%k7} > >> + vmovss %xmm0, (%eax){%k7} > >> + > >> + vmovsd %xmm0, %xmm0, %xmm0{%k7} > >> + vmovsd (%eax), %xmm0{%k7} > >> + vmovsd %xmm0, (%eax){%k7} > >> + > >> + vmovsh %xmm0, %xmm0, %xmm0{%k7} > >> + vmovsh (%eax), %xmm0{%k7} > >> + vmovsh %xmm0, (%eax){%k7} > >> + > >> vpmovsxbd %xmm5, %zmm6{%k7} # AVX512 > >> vpmovsxbd %xmm5, %zmm6{%k7}{z} # AVX512 > >> vpmovsxbd (%ecx), %zmm6{%k7} # AVX512 > >> --- a/gas/testsuite/gas/i386/evex-wig1-intel.d > >> +++ b/gas/testsuite/gas/i386/evex-wig1-intel.d > >> @@ -45,6 +45,15 @@ Disassembly of section .text: > >> [ ]*[a-f0-9]+: 62 f3 fd 08 22 40 01 00 vpinsrd xmm0,x= mm0,DWORD PTR \[eax\+0x4\],0x0 > >> [ ]*[a-f0-9]+: 62 f1 fd 08 c4 c0 00 vpinsrw xmm0,xmm0,eax,= 0x0 > >> [ ]*[a-f0-9]+: 62 f1 fd 08 c4 40 01 00 vpinsrw xmm0,x= mm0,WORD PTR \[eax\+0x2\],0x0 > >> +[ ]*[a-f0-9]+: 62 f1 7e 0f 10 c0 vmovss xmm0\{k7\},xmm0= ,xmm0 > >> +[ ]*[a-f0-9]+: 62 f1 7e 0f 10 00 vmovss xmm0\{k7\},DWOR= D PTR \[eax\] > >> +[ ]*[a-f0-9]+: 62 f1 7e 0f 11 00 vmovss DWORD PTR \[eax= \]\{k7\},xmm0 > >> +[ ]*[a-f0-9]+: 62 f1 ff 0f 10 c0 vmovsd xmm0\{k7\},xmm0= ,xmm0 > >> +[ ]*[a-f0-9]+: 62 f1 ff 0f 10 00 vmovsd xmm0\{k7\},QWOR= D PTR \[eax\] > >> +[ ]*[a-f0-9]+: 62 f1 ff 0f 11 00 vmovsd QWORD PTR \[eax= \]\{k7\},xmm0 > >> +[ ]*[a-f0-9]+: 62 f5 7e 0f 10 c0 vmovsh xmm0\{k7\},xmm0= ,xmm0 > >> +[ ]*[a-f0-9]+: 62 f5 7e 0f 10 00 vmovsh xmm0\{k7\},WORD= PTR \[eax\] > >> +[ ]*[a-f0-9]+: 62 f5 7e 0f 11 00 vmovsh WORD PTR \[eax\= ]\{k7\},xmm0 > >> [ ]*[a-f0-9]+: 62 f2 fd 4f 21 f5 vpmovsxbd zmm6\{k7\},x= mm5 > >> [ ]*[a-f0-9]+: 62 f2 fd cf 21 f5 vpmovsxbd zmm6\{k7\}\{= z\},xmm5 > >> [ ]*[a-f0-9]+: 62 f2 fd 4f 21 31 vpmovsxbd zmm6\{k7\},X= MMWORD PTR \[ecx\] > >> --- a/gas/testsuite/gas/i386/evex-wig1.d > >> +++ b/gas/testsuite/gas/i386/evex-wig1.d > >> @@ -45,6 +45,15 @@ Disassembly of section .text: > >> [ ]*[a-f0-9]+: 62 f3 fd 08 22 40 01 00 vpinsrd \$0x0,= 0x4\(%eax\),%xmm0,%xmm0 > >> [ ]*[a-f0-9]+: 62 f1 fd 08 c4 c0 00 vpinsrw \$0x0,%eax,%xm= m0,%xmm0 > >> [ ]*[a-f0-9]+: 62 f1 fd 08 c4 40 01 00 vpinsrw \$0x0,= 0x2\(%eax\),%xmm0,%xmm0 > >> +[ ]*[a-f0-9]+: 62 f1 7e 0f 10 c0 vmovss %xmm0,%xmm0,%xm= m0\{%k7\} > >> +[ ]*[a-f0-9]+: 62 f1 7e 0f 10 00 vmovss \(%eax\),%xmm0\= {%k7\} > >> +[ ]*[a-f0-9]+: 62 f1 7e 0f 11 00 vmovss %xmm0,\(%eax\)\= {%k7\} > >> +[ ]*[a-f0-9]+: 62 f1 ff 0f 10 c0 vmovsd %xmm0,%xmm0,%xm= m0\{%k7\} > >> +[ ]*[a-f0-9]+: 62 f1 ff 0f 10 00 vmovsd \(%eax\),%xmm0\= {%k7\} > >> +[ ]*[a-f0-9]+: 62 f1 ff 0f 11 00 vmovsd %xmm0,\(%eax\)\= {%k7\} > >> +[ ]*[a-f0-9]+: 62 f5 7e 0f 10 c0 vmovsh %xmm0,%xmm0,%xm= m0\{%k7\} > >> +[ ]*[a-f0-9]+: 62 f5 7e 0f 10 00 vmovsh \(%eax\),%xmm0\= {%k7\} > >> +[ ]*[a-f0-9]+: 62 f5 7e 0f 11 00 vmovsh %xmm0,\(%eax\)\= {%k7\} > >> [ ]*[a-f0-9]+: 62 f2 fd 4f 21 f5 vpmovsxbd %xmm5,%zmm6\= {%k7\} > >> [ ]*[a-f0-9]+: 62 f2 fd cf 21 f5 vpmovsxbd %xmm5,%zmm6\= {%k7\}\{z\} > >> [ ]*[a-f0-9]+: 62 f2 fd 4f 21 31 vpmovsxbd \(%ecx\),%zm= m6\{%k7\} > >> --- a/opcodes/i386-opc.tbl > >> +++ b/opcodes/i386-opc.tbl > >> @@ -3684,8 +3684,8 @@ vmaxsh, 0xf35f, None, CpuAVX512_FP16, Mo > >> vminph, 0x5d, None, CpuAVX512_FP16, Modrm|VexVVVV|Masking=3D3|EVexMap= 5|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf= |No_qSuf|No_ldSuf|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, R= egXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > >> vminsh, 0xf35d, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3D3|EVexM= ap5|VexVVVV|VexW0|Disp8MemShift=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf= |No_ldSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM } > >> > >> -vmovsh, 0xf310, None, CpuAVX512_FP16, D|Modrm|EVexLIG|Masking=3D3|EVe= xMap5|Disp8MemShift=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {= Word|Unspecified|BaseIndex, RegXMM } > >> -vmovsh, 0xf310, None, CpuAVX512_FP16, D|Modrm|EVexLIG|Masking=3D3|EVe= xMap5|VexVVVV|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, R= egXMM, RegXMM } > >> +vmovsh, 0xf310, None, CpuAVX512_FP16, D|Modrm|EVexLIG|MaskingMorZ|EVe= xMap5|VexW0|Disp8MemShift=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ld= Suf, { Word|Unspecified|BaseIndex, RegXMM } > >> +vmovsh, 0xf310, None, CpuAVX512_FP16, D|Modrm|EVexLIG|Masking=3D3|EVe= xMap5|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg= XMM, RegXMM, RegXMM } > >> > >> vmovw, 0x666e, None, CpuAVX512_FP16, D|Modrm|EVex128|VexWIG|EVexMap5|= Disp8MemShift=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|= Unspecified|BaseIndex, RegXMM } > >> vmovw, 0x667e, None, CpuAVX512_FP16, D|RegMem|EVex128|VexWIG|EVexMap5= |No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Reg32 } > > > > OK. > > Thanks. I wonder whether we don't also want this on the 2.39 branch. > > Jan Please backport to 2.39. Thanks. --=20 H.J.