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From: "H.J. Lu" <hjl.tools@gmail.com>
To: Jan Beulich <jbeulich@suse.com>
Cc: Binutils <binutils@sourceware.org>
Subject: Re: [PATCH 1/7] x86/Intel: restrict suffix derivation
Date: Mon, 22 Aug 2022 07:38:48 -0700	[thread overview]
Message-ID: <CAMe9rOpo=9qc-TrwT4MNoBAQG42mtVcetxDvy-0ADkxdPjFPYg@mail.gmail.com> (raw)
In-Reply-To: <0c692b29-efcf-f94f-51fe-958e3cec862b@suse.com>

On Mon, Aug 22, 2022 at 2:34 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 19.08.2022 19:00, H.J. Lu wrote:
> > On Fri, Aug 19, 2022 at 7:49 AM Jan Beulich <jbeulich@suse.com> wrote:
> >>
> >> On 19.08.2022 16:23, H.J. Lu wrote:
> >>> On Fri, Aug 19, 2022 at 1:20 AM Jan Beulich <jbeulich@suse.com> wrote:
> >>>>
> >>>> On 18.08.2022 16:46, H.J. Lu wrote:
> >>>>> On Wed, Aug 17, 2022 at 11:08 PM Jan Beulich <jbeulich@suse.com> wrote:
> >>>>>>
> >>>>>> On 17.08.2022 21:19, H.J. Lu wrote:
> >>>>>>> On Tue, Aug 16, 2022 at 12:30 AM Jan Beulich <jbeulich@suse.com> wrote:
> >>>>>>>>
> >>>>>>>> While in some cases deriving an AT&T-style suffix from an Intel syntax
> >>>>>>>> memory operand size specifier is necessary, in many cases this is not
> >>>>>>>> only pointless, but has led to the introduction of various workarounds:
> >>>>>>>> Excessive use of IgnoreSize and NoRex64 as well as the ToDword and
> >>>>>>>> ToQword attributes. Suppress suffix derivation when we can clearly tell
> >>>>>>>> that the memory operand's size isn't going to be needed to infer the
> >>>>>>>> possible need for the low byte/word opcode bit or an operand size prefix
> >>>>>>>> (0x66 or REX.W).
> >>>>>>>>
> >>>>>>>> As a result ToDword and ToQword can be dropped entirely, plus a fair
> >>>>>>>> number of IgnoreSize and NoRex64 can also be got rid of. Note that
> >>>>>>>> IgnoreSize needs to remain on legacy encoded SIMD insns with GPR
> >>>>>>>> operand, to avoid emitting an operand size prefix in 16-bit mode. (Since
> >>>>>>>> 16-bit code using SIMD insns isn't well tested, clone an existing
> >>>>>>>> testcase just enough to cover a few insns which are potentially
> >>>>>>>> problematic but are being touched here.)
> >>>>>>>>
> >>>>>>>> As a side effect of folding the VCVT{,T}S{S,D,H}2SI templates,
> >>>>>>>> VCVT{,T}SH2SI will now allow L and Q suffixes, consistent with
> >>>>>>>> VCVT{,T}S{S,D}2SI. All of these remain inconsistent with their 2USI
> >>>>>>>> counterparts (which I think should also be corrected, but perhaps better
> >>>>>>>> in a separate change).
> >>>>>>>
> >>>>>>> I don't think allowing more unnecessary L and Q suffixes for AVX
> >>>>>>> instructions is desirable.   I prefer not to allow unnecessary L and
> >>>>>>> Q suffixes in folded entries.   We can add special entries to allow
> >>>>>>> the existing instructions with suffixes.
> >>>>>>
> >>>>>> I think we've been there before, and I continue to think that we should
> >>>>>> be consistent throughout the entire ISA in allowing suffixes when GPRs
> >>>>>> or their equivalent memory operands are involved. That's in the spirit
> >>>>>> of the original AT&T syntax intentions, after all. I have to admit that
> >>>>>> I find it particularly worrying that you suggest to introduce new
> >>>>>> templates, when the overall / long term goal is to reduce the set, to
> >>>>>> keep it manageable in spite of all the new additions that yer yet to
> >>>>>> come.
> >>>>>>
> >>>>>> As pointed out elsewhere, any inconsistencies here make it harder for
> >>>>>> people to write e.g. heavily macro-ized code. Similarly it can result
> >>>>>> in surprises when cloning existing code to deal with new extensions.
> >>>>>>
> >>>>>
> >>>>> Will it work without unnecessary suffixes?
> >>>>
> >>>> I'm afraid I can only guess at what "it" means in your reply. Of course
> >>>> things will work for people who have never used what you call
> >>>> "unnecessary" prefixes. But there are other people who believe that the
> >>>> spirit of AT&T syntax is to put suffixes everywhere where multiple
> >>>> operand sizes are possible, and where the suffix allows to distinguish
> >>>
> >>> In glibc, integer instructions without suffixes are used to support different
> >>> vector sizes.
> >
> > https://sourceware.org/git/?p=glibc.git;a=blob;f=sysdeps/x86_64/multiarch/strlen-evex-base.S
>
> I'm afraid I don't see how this is related to the topic. Yes, that's one
> way to do such programming. But it doesn't mean others shouldn't be
> allowed to do things differently, to their liking. Plus - integer
> instructions aren't relevant here at all; we permit suffixes for all of
> them anyway. Vector / scalar instructions are what matters, and I see
> they actually abstract kmov{q,d} via a KMOV pre-processor macro, for
> example. (Not relevant here: I actually view it as a shortcoming of
> the assembler that they need to do that, rather than us allowing use of
> "kmov" without the Intel-mandated suffix. Obviously this would extend
> to other insns as well.)
>
> >> 1) Could you please point me at an example?
> >>
> >> 2) How is this related? We wouldn't require suffixes all of the sudden,
> >> we'd only permit their use.
> >
> > We shouldn't add suffixes when they aren't needed.   Suffixes aren't
> > required.
>
> You're re-stating what I've said. What you look to not be willing to
> accept is that we ought to _allow_ use of suffixes in _all_ places
> where they might matter, _irrespective_ of them being required.
>

That is correct.

-- 
H.J.

  reply	other threads:[~2022-08-22 14:39 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-16  7:27 [PATCH 0/7] x86: suffix handling changes Jan Beulich
2022-08-16  7:30 ` [PATCH 1/7] x86/Intel: restrict suffix derivation Jan Beulich
2022-08-17 19:19   ` H.J. Lu
2022-08-18  6:07     ` Jan Beulich
2022-08-18 14:46       ` H.J. Lu
2022-08-19  8:19         ` Jan Beulich
2022-08-19 14:23           ` H.J. Lu
2022-08-19 14:49             ` Jan Beulich
2022-08-19 17:00               ` H.J. Lu
2022-08-22  9:34                 ` Jan Beulich
2022-08-22 14:38                   ` H.J. Lu [this message]
2022-08-16  7:30 ` [PATCH 2/7] x86: insert "no error" enumerator in i386_error enumeration Jan Beulich
2022-08-17 19:19   ` H.J. Lu
2022-08-16  7:31 ` [PATCH 3/7] x86: move / quiesce pre-386 non-16-bit warning Jan Beulich
2022-08-17 19:21   ` H.J. Lu
2022-08-18  7:21     ` Jan Beulich
2022-08-18 15:30       ` H.J. Lu
2022-08-19  6:13         ` Jan Beulich
2022-08-19 14:18           ` H.J. Lu
2022-08-16  7:32 ` [PATCH 4/7] x86: improve match_template()'s diagnostics Jan Beulich
2022-08-17 20:24   ` H.J. Lu
2022-08-18  6:14     ` Jan Beulich
2022-08-18 14:51       ` H.J. Lu
2022-08-16  7:32 ` [PATCH 5/7] x86: re-work insn/suffix recognition Jan Beulich
2022-08-17 20:29   ` H.J. Lu
2022-08-18  6:24     ` Jan Beulich
2022-08-18 15:14       ` H.J. Lu
2022-08-19  8:28         ` Jan Beulich
2022-08-23  2:00           ` H.J. Lu
2022-08-26  9:26             ` Jan Beulich
2022-08-26 18:46               ` H.J. Lu
2022-09-06  6:40                 ` Jan Beulich
2022-09-06 21:53                   ` H.J. Lu
2022-09-07  7:17                     ` Jan Beulich
2022-09-26 23:52                       ` H.J. Lu
2022-09-28 12:49                         ` Jan Beulich
2022-09-28 19:33                           ` H.J. Lu
2022-09-29  8:08                             ` Jan Beulich
2022-09-29 16:00                               ` H.J. Lu
2022-09-29 16:06                                 ` Jan Beulich
2022-09-29 16:20                                   ` H.J. Lu
2022-08-16  7:33 ` [PATCH 6/7] x86-64: further re-work insn/suffix recognition to also cover MOVSL Jan Beulich
2022-08-16  7:34 ` [PATCH 7/7] ix86: don't recognize/derive Q suffix in the common case Jan Beulich
2022-08-17 20:36   ` H.J. Lu
2022-08-18  6:29     ` Jan Beulich

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