Date: Fri, 15 May 2015 09:47:39 -0700
Subject: [PATCH] Support AMD64/Intel ISAs in assembler/disassembler

AMD64 spec and Intel64 spec differ in direct unconditional branches in
64-bit mode.  AMD64 supports direct unconditional branches with 16-bit
offset via the data size prefix, which truncates RIP to 16 bits, while
the data size prefix is ignored by Intel64.

This patch adds -mamd64/-mintel64 option to x86-64 assembler and
-Mamd64/-Mintel64 option to x86-64 disassembler.  The most permissive
ISA, which is AMD64, is the default.

GDB can add an option, similar to

(gdb) help set disassembly-flavor
Set the disassembly flavor.
The valid values are "att" and "intel", and the default value is "att".

to select which ISA to disassemble.

binutils/

	PR binutis/18386
	* doc/binutils.texi: Document -Mamd64 and -Mintel64.

gas/

	PR binutis/18386
	* config/tc-i386.c (OPTION_MAMD64): New.
	(OPTION_MINTEL64): Likewise.
	(md_longopts): Add -mamd64 and -mintel64.
	(md_parse_option): Handle OPTION_MAMD64 and OPTION_MINTEL64.
	(md_show_usage): Add -mamd64 and -mintel64.
	* doc/c-i386.texi: Document -mamd64 and -mintel64.

gas/testsuite/

	PR binutis/18386
	* gas/i386/i386.exp: Run x86-64-branch-2 and x86-64-branch-3.
	* gas/i386/x86-64-branch.d: Also pass -Mintel64 to objdump.
	* gas/i386/ilp32/x86-64-branch.d: Likewise.
	* gas/i386/x86-64-branch-2.d: New file.
	* gas/i386/x86-64-branch-2.s: Likewise.
	* gas/i386/x86-64-branch-3.l: Likewise.
	* gas/i386/x86-64-branch-3.s: Likewise.

ld/testsuite/

	PR binutis/18386
	* ld-x86-64/tlsgdesc.dd: Also pass -Mintel64 to objdump.
	* ld-x86-64/tlspic.dd: Likewise.
	* ld-x86-64/x86-64.exp (x86_64tests): Also pass -Mintel64 to
	objdump for tlspic.dd and tlsgdesc.dd.

opcodes/

	PR binutis/18386
	* i386-dis.c: Add comments for '@'.
	(x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
	(enum x86_64_isa): New.
	(isa64): Likewise.
	(print_i386_disassembler_options): Add amd64 and intel64.
	(print_insn): Handle amd64 and intel64.
	(putop): Handle '@'.
	(OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
	* i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
	* i386-opc.h (AMD64): New.
	(CpuIntel64): Likewise.
	(i386_cpu_flags): Add cpuamd64 and cpuintel64.
	* i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
	Mark direct call/jmp without Disp16|Disp32 as Intel64.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
---
 binutils/ChangeLog                           |     5 +
 binutils/doc/binutils.texi                   |     4 +
 gas/ChangeLog                                |    10 +
 gas/config/tc-i386.c                         |    22 +
 gas/doc/c-i386.texi                          |     7 +
 gas/testsuite/ChangeLog                      |    11 +
 gas/testsuite/gas/i386/i386.exp              |     2 +
 gas/testsuite/gas/i386/ilp32/x86-64-branch.d |     2 +-
 gas/testsuite/gas/i386/x86-64-branch-2.d     |    15 +
 gas/testsuite/gas/i386/x86-64-branch-2.s     |     7 +
 gas/testsuite/gas/i386/x86-64-branch-3.l     |    17 +
 gas/testsuite/gas/i386/x86-64-branch-3.s     |     7 +
 gas/testsuite/gas/i386/x86-64-branch.d       |     2 +-
 ld/testsuite/ChangeLog                       |     8 +
 ld/testsuite/ld-x86-64/tlsgdesc.dd           |     2 +-
 ld/testsuite/ld-x86-64/tlspic.dd             |     2 +-
 ld/testsuite/ld-x86-64/x86-64.exp            |     4 +-
 opcodes/ChangeLog                            |    20 +
 opcodes/i386-dis.c                           |    45 +-
 opcodes/i386-gen.c                           |     2 +
 opcodes/i386-init.h                          |   212 +-
 opcodes/i386-opc.h                           |     6 +
 opcodes/i386-opc.tbl                         |     6 +-
 opcodes/i386-tbl.h                           | 10392 +++++++++++++------------
 24 files changed, 5508 insertions(+), 5302 deletions(-)
 create mode 100644 gas/testsuite/gas/i386/x86-64-branch-2.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-branch-2.s
 create mode 100644 gas/testsuite/gas/i386/x86-64-branch-3.l
 create mode 100644 gas/testsuite/gas/i386/x86-64-branch-3.s

diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index ee2ddf0..2328f6e 100644
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -1,3 +1,8 @@
+2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR binutis/18386
+	* doc/binutils.texi: Document -Mamd64 and -Mintel64.
+
 2015-05-15  Nick Clifton  <nickc@redhat.com>
 
 	* readelf.c (options): Add "decompress".
diff --git a/binutils/doc/binutils.texi b/binutils/doc/binutils.texi
index 619c28e..75852e6 100644
--- a/binutils/doc/binutils.texi
+++ b/binutils/doc/binutils.texi
@@ -2175,6 +2175,10 @@ Select disassembly for the given architecture.
 @itemx att
 Select between intel syntax mode and AT&T syntax mode.
 
+@item amd64
+@itemx intel64
+Select between AMD64 ISA and Intel64 ISA.
+
 @item intel-mnemonic
 @itemx att-mnemonic
 Select between intel mnemonic mode and AT&T mnemonic mode.
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 9bc4a15..6cd3639 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,15 @@
 2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>
 
+	PR binutis/18386
+	* config/tc-i386.c (OPTION_MAMD64): New.
+	(OPTION_MINTEL64): Likewise.
+	(md_longopts): Add -mamd64 and -mintel64.
+	(md_parse_option): Handle OPTION_MAMD64 and OPTION_MINTEL64.
+	(md_show_usage): Add -mamd64 and -mintel64.
+	* doc/c-i386.texi: Document -mamd64 and -mintel64.
+
+2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>
+
 	* config/tc-i386.c (shared): New.
 	(OPTION_MSHARED): Likewise.
 	(elf_symbol_resolved_in_segment_p): Add relocation argument.
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 254548f..34b5c28 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -9550,6 +9550,8 @@ const char *md_shortopts = "qn";
 #define OPTION_OMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
+#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
+#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
 
 struct option md_longopts[] =
 {
@@ -9582,6 +9584,8 @@ struct option md_longopts[] =
 #endif
   {"momit-lock-prefix", required_argument, NULL, OPTION_OMIT_LOCK_PREFIX},
   {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
+  {"mamd64", no_argument, NULL, OPTION_MAMD64},
+  {"mintel64", no_argument, NULL, OPTION_MINTEL64},
   {NULL, no_argument, NULL, 0}
 };
 size_t md_longopts_size = sizeof (md_longopts);
@@ -9898,6 +9902,20 @@ md_parse_option (int c, char *arg)
         as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
       break;
 
+    case OPTION_MAMD64:
+      cpu_arch_flags.bitfield.cpuamd64 = 1;
+      cpu_arch_flags.bitfield.cpuintel64 = 0;
+      cpu_arch_isa_flags.bitfield.cpuamd64 = 1;
+      cpu_arch_isa_flags.bitfield.cpuintel64 = 0;
+      break;
+
+    case OPTION_MINTEL64:
+      cpu_arch_flags.bitfield.cpuamd64 = 0;
+      cpu_arch_flags.bitfield.cpuintel64 = 1;
+      cpu_arch_isa_flags.bitfield.cpuamd64 = 0;
+      cpu_arch_isa_flags.bitfield.cpuintel64 = 1;
+      break;
+
     default:
       return 0;
     }
@@ -10063,6 +10081,10 @@ md_show_usage (FILE *stream)
   fprintf (stream, _("\
   -momit-lock-prefix=[no|yes]\n\
                           strip all lock prefixes\n"));
+  fprintf (stream, _("\
+  -mamd64                 accept only AMD64 ISA\n"));
+  fprintf (stream, _("\
+  -mintel64               accept only Intel64 ISA\n"));
 }
 
 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index ea08c63..6118987 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -339,6 +339,13 @@ of EVEX instruction with 00, which is the default.
 and @option{-mevexrcig=@var{rz}} will encode SAE-only EVEX instructions
 with 01, 10 and 11 RC bits, respectively.
 
+@cindex @samp{-mamd64} option, x86-64
+@cindex @samp{-mintel64} option, x86-64
+@item -mamd64
+@itemx -mintel64
+This option specifies that the assembler should accept only AMD64 or
+Intel64 ISA in 64-bit mode.  The default is to accept both.
+
 @end table
 @c man end
 
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 95b7583..7f4b81b 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,5 +1,16 @@
 2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>
 
+	PR binutis/18386
+	* gas/i386/i386.exp: Run x86-64-branch-2 and x86-64-branch-3.
+	* gas/i386/x86-64-branch.d: Also pass -Mintel64 to objdump.
+	* gas/i386/ilp32/x86-64-branch.d: Likewise.
+	* gas/i386/x86-64-branch-2.d: New file.
+	* gas/i386/x86-64-branch-2.s: Likewise.
+	* gas/i386/x86-64-branch-3.l: Likewise.
+	* gas/i386/x86-64-branch-3.s: Likewise.
+
+2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>
+
 	* gas/i386/i386.exp: Don't run pcrel for ELF targets.  Run
 	pcrel-elf, relax-4 and x86-64-relax-3 for ELF targets.
 	* gas/i386/pcrel-elf.d: New file.
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index ff648b0..9ff38d3 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -770,6 +770,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
 	run_dump_test "x86-64-relax-3"
 
 	run_dump_test "x86-64-jump"
+	run_dump_test "x86-64-branch-2"
+	run_list_test "x86-64-branch-3" "-al -mintel64"
     }
 
     set ASFLAGS "$old_ASFLAGS"
diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-branch.d b/gas/testsuite/gas/i386/ilp32/x86-64-branch.d
index 9fcb8ca..8200282 100644
--- a/gas/testsuite/gas/i386/ilp32/x86-64-branch.d
+++ b/gas/testsuite/gas/i386/ilp32/x86-64-branch.d
@@ -1,6 +1,6 @@
 #source: ../x86-64-branch.s
 #as: -J
-#objdump: -drw
+#objdump: -drw -Mintel64
 #name: x86-64 (ILP32) branch
 
 .*: +file format .*
diff --git a/gas/testsuite/gas/i386/x86-64-branch-2.d b/gas/testsuite/gas/i386/x86-64-branch-2.d
new file mode 100644
index 0000000..5078daa
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-branch-2.d
@@ -0,0 +1,15 @@
+#as: -J
+#objdump: -dwr
+#name: x86-64 branch 2
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <bar-0x4>:
+[ 	]*[a-f0-9]+:	66 e9 00 00          	jmpw   4 <bar>	2: R_X86_64_PC16	foo-0x2
+
+0+4 <bar>:
+[ 	]*[a-f0-9]+:	89 c3                	mov    %eax,%ebx
+[ 	]*[a-f0-9]+:	66 e8 00 00          	callw  a <bar\+0x6>	8: R_X86_64_PC16	foo-0x2
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-branch-2.s b/gas/testsuite/gas/i386/x86-64-branch-2.s
new file mode 100644
index 0000000..16c85a3
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-branch-2.s
@@ -0,0 +1,7 @@
+	.text
+	data16 jmp foo
+
+bar:
+	mov %eax, %ebx
+
+	data16 call foo
diff --git a/gas/testsuite/gas/i386/x86-64-branch-3.l b/gas/testsuite/gas/i386/x86-64-branch-3.l
new file mode 100644
index 0000000..de3c2dd
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-branch-3.l
@@ -0,0 +1,17 @@
+.*: Assembler messages:
+.*:2: Warning: indirect jmp without `\*'
+.*:7: Warning: indirect call without `\*'
+GAS LISTING .*
+
+
+[ 	]*1[ 	]+\.text
+[ 	]*2[ 	]+0000 66FF2C25 		data16 jmp foo
+\*\*\*\*  Warning: indirect jmp without `\*'
+[ 	]*2[ 	]+00000000 
+[ 	]*3[ 	]+
+[ 	]*4[ 	]+bar:
+[ 	]*5[ 	]+0008 89C3     		mov %eax, %ebx
+[ 	]*6[ 	]+
+[ 	]*7[ 	]+000a 66FF1C25 		data16 call foo
+\*\*\*\*  Warning: indirect call without `\*'
+[ 	]*7[ 	]+00000000 
diff --git a/gas/testsuite/gas/i386/x86-64-branch-3.s b/gas/testsuite/gas/i386/x86-64-branch-3.s
new file mode 100644
index 0000000..16c85a3
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-branch-3.s
@@ -0,0 +1,7 @@
+	.text
+	data16 jmp foo
+
+bar:
+	mov %eax, %ebx
+
+	data16 call foo
diff --git a/gas/testsuite/gas/i386/x86-64-branch.d b/gas/testsuite/gas/i386/x86-64-branch.d
index 49e17a4..612acc0 100644
--- a/gas/testsuite/gas/i386/x86-64-branch.d
+++ b/gas/testsuite/gas/i386/x86-64-branch.d
@@ -1,5 +1,5 @@
 #as: -J
-#objdump: -dw
+#objdump: -dw -Mintel64
 #name: x86-64 branch
 
 .*: +file format .*
diff --git a/ld/testsuite/ChangeLog b/ld/testsuite/ChangeLog
index a7b006c..43c7c24 100644
--- a/ld/testsuite/ChangeLog
+++ b/ld/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR binutis/18386
+	* ld-x86-64/tlsgdesc.dd: Also pass -Mintel64 to objdump.
+	* ld-x86-64/tlspic.dd: Likewise.
+	* ld-x86-64/x86-64.exp (x86_64tests): Also pass -Mintel64 to
+	objdump for tlspic.dd and tlsgdesc.dd.
+
 2015-05-12  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* ld-i386/i386.exp: Run pltgot-1 for Linux targets.
diff --git a/ld/testsuite/ld-x86-64/tlsgdesc.dd b/ld/testsuite/ld-x86-64/tlsgdesc.dd
index 88eb953..a983a75 100644
--- a/ld/testsuite/ld-x86-64/tlsgdesc.dd
+++ b/ld/testsuite/ld-x86-64/tlsgdesc.dd
@@ -1,7 +1,7 @@
 #source: tlsgdesc.s
 #as: --64
 #ld: -shared -melf_x86_64 --no-ld-generated-unwind-info
-#objdump: -drj.text
+#objdump: -drj.text -Mintel64
 #target: x86_64-*-*
 
 .*: +file format elf64-x86-64.*
diff --git a/ld/testsuite/ld-x86-64/tlspic.dd b/ld/testsuite/ld-x86-64/tlspic.dd
index aab8181..bf3ba69 100644
--- a/ld/testsuite/ld-x86-64/tlspic.dd
+++ b/ld/testsuite/ld-x86-64/tlspic.dd
@@ -2,7 +2,7 @@
 #source: tlspic2.s
 #as: --64
 #ld: -shared -melf_x86_64 --no-ld-generated-unwind-info
-#objdump: -drj.text
+#objdump: -drj.text -Mintel64
 #target: x86_64-*-*
 
 .*: +file format elf64-x86-64.*
diff --git a/ld/testsuite/ld-x86-64/x86-64.exp b/ld/testsuite/ld-x86-64/x86-64.exp
index 58e598e..a312271 100644
--- a/ld/testsuite/ld-x86-64/x86-64.exp
+++ b/ld/testsuite/ld-x86-64/x86-64.exp
@@ -52,7 +52,7 @@ set x86_64tests {
     {"TLS -fpic -shared transitions"
      "-shared -melf_x86_64 --no-ld-generated-unwind-info" ""
      "--64" {tlspic1.s tlspic2.s}
-     {{readelf -WSsrl tlspic.rd} {objdump -drj.text tlspic.dd}
+     {{readelf -WSsrl tlspic.rd} {objdump -drj.text\ -Mintel64 tlspic.dd}
       {objdump -sj.got tlspic.sd} {objdump -sj.tdata tlspic.td}}
       "libtlspic.so"}
     {"TLS descriptor -fpic -shared transitions"
@@ -78,7 +78,7 @@ set x86_64tests {
     {"TLS with global dynamic and descriptors"
      "-shared -melf_x86_64 --no-ld-generated-unwind-info" ""
      "--64" {tlsgdesc.s}
-     {{readelf -WSsrl tlsgdesc.rd} {objdump -drj.text tlsgdesc.dd}}
+     {{readelf -WSsrl tlsgdesc.rd} {objdump -drj.text\ -Mintel64 tlsgdesc.dd}}
       "libtlsgdesc.so"}
     {"TLS in debug sections" "-melf_x86_64" ""
      "--64" {tlsg.s}
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index dbce2d3..d3f914c 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,23 @@
+2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR binutis/18386
+	* i386-dis.c: Add comments for '@'.
+	(x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
+	(enum x86_64_isa): New.
+	(isa64): Likewise.
+	(print_i386_disassembler_options): Add amd64 and intel64.
+	(print_insn): Handle amd64 and intel64.
+	(putop): Handle '@'.
+	(OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
+	* i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
+	* i386-opc.h (AMD64): New.
+	(CpuIntel64): Likewise.
+	(i386_cpu_flags): Add cpuamd64 and cpuintel64.
+	* i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
+	Mark direct call/jmp without Disp16|Disp32 as Intel64.
+	* i386-init.h: Regenerated.
+	* i386-tbl.h: Likewise.
+
 2015-05-14  Peter Bergner  <bergner@vnet.ibm.com>
 
 	* ppc-opc.c (IH) New define.
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 941f699..76f3ead 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -2418,6 +2418,8 @@ struct dis386 {
    '%' => add 1 upper case letter to the macro.
    '^' => print 'w' or 'l' depending on operand size prefix or
 	  suffix_always is true (lcall/ljmp).
+   '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
+	  on operand size prefix.
 
    2 upper case letter macros:
    "XY" => print 'x' or 'y' if suffix_always is true or no register
@@ -6844,13 +6846,13 @@ static const struct dis386 x86_64_table[][2] = {
   /* X86_64_E8 */
   {
     { "callP",		{ Jv, BND }, 0 },
-    { "callq",		{ Jv, BND }, 0 }
+    { "call@",		{ Jv, BND }, 0 }
   },
 
   /* X86_64_E9 */
   {
     { "jmpP",		{ Jv, BND }, 0 },
-    { "jmpq",		{ Jv, BND }, 0 }
+    { "jmp@",		{ Jv, BND }, 0 }
   },
 
   /* X86_64_EA */
@@ -12342,6 +12344,14 @@ static char close_char;
 static char separator_char;
 static char scale_char;
 
+enum x86_64_isa
+{
+  amd64 = 0,
+  intel64
+};
+
+static enum x86_64_isa isa64;
+
 /* Here for backwards compatibility.  When gdb stops using
    print_insn_i386_att and print_insn_i386_intel these functions can
    disappear, and print_insn_i386 be merged into print_insn.  */
@@ -12391,6 +12401,8 @@ with the -M switch (multiple options should be separated by commas):\n"));
   fprintf (stream, _("  data32      Assume 32bit data size\n"));
   fprintf (stream, _("  data16      Assume 16bit data size\n"));
   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
+  fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
+  fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
 }
 
 /* Bad opcode.  */
@@ -12874,7 +12886,11 @@ print_insn (bfd_vma pc, disassemble_info *info)
 
   for (p = info->disassembler_options; p != NULL; )
     {
-      if (CONST_STRNEQ (p, "x86-64"))
+      if (CONST_STRNEQ (p, "amd64"))
+	isa64 = amd64;
+      else if (CONST_STRNEQ (p, "intel64"))
+	isa64 = intel64;
+      else if (CONST_STRNEQ (p, "x86-64"))
 	{
 	  address_mode = mode_64bit;
 	  priv.orig_sizeflag = AFLAG | DFLAG;
@@ -14208,6 +14224,20 @@ case_S:
 	      used_prefixes |= (prefixes & PREFIX_DATA);
 	    }
 	  break;
+	case '@':
+	  if (intel_syntax)
+	    break;
+	  if (address_mode == mode_64bit
+	      && (isa64 == intel64
+		  || ((sizeflag & DFLAG) || (rex & REX_W))))
+	      *obufp++ = 'q';
+	  else if ((prefixes & PREFIX_DATA))
+	    {
+	      if (!(sizeflag & DFLAG))
+		*obufp++ = 'w';
+	      used_prefixes |= (prefixes & PREFIX_DATA);
+	    }
+	  break;
 	}
       alt = 0;
     }
@@ -15724,7 +15754,11 @@ OP_J (int bytemode, int sizeflag)
 	disp -= 0x100;
       break;
     case v_mode:
-      if (address_mode == mode_64bit || (sizeflag & DFLAG))
+      if (isa64 == amd64)
+	USED_REX (REX_W);
+      if ((sizeflag & DFLAG)
+	  || (address_mode == mode_64bit
+	      && (isa64 != amd64 || (rex & REX_W))))
 	disp = get32s ();
       else
 	{
@@ -15740,7 +15774,8 @@ OP_J (int bytemode, int sizeflag)
 	    segment = ((start_pc + codep - start_codep)
 		       & ~((bfd_vma) 0xffff));
 	}
-      if (address_mode != mode_64bit)
+      if (address_mode != mode_64bit
+	  || (isa64 == amd64 && !(rex & REX_W)))
 	used_prefixes |= (prefixes & PREFIX_DATA);
       break;
     default:
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index 216bc49..0523936 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -458,6 +458,8 @@ static bitfield cpu_flags[] =
   BITFIELD (CpuAVX512IFMA),
   BITFIELD (CpuAVX512VBMI),
   BITFIELD (CpuCLZERO),
+  BITFIELD (CpuAMD64),
+  BITFIELD (CpuIntel64),
 #ifdef CpuUnused
   BITFIELD (CpuUnused),
 #endif
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index ff9b32c..62ac42a 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -200,6 +200,10 @@ enum
   Cpu64,
   /* Not supported in the 64bit mode  */
   CpuNo64,
+  /* AMD64 support required  */
+  CpuAMD64,
+  /* Intel64 support required  */
+  CpuIntel64,
   /* The last bitfield in i386_cpu_flags.  */
   CpuMax = CpuNo64
 };
@@ -303,6 +307,8 @@ typedef union i386_cpu_flags
       unsigned int cpuclzero:1;
       unsigned int cpu64:1;
       unsigned int cpuno64:1;
+      unsigned int cpuamd64:1;
+      unsigned int cpuintel64:1;
 #ifdef CpuUnused
       unsigned int unused:(CpuNumOfBits - CpuUnused);
 #endif
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index ca629c4..56eddbf 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -319,7 +319,8 @@ shrd, 2, 0xfad, None, 2, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, {
 
 // Control transfer instructions.
 call, 1, 0xe8, None, 1, CpuNo64, JumpDword|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp16|Disp32 }
-call, 1, 0xe8, None, 1, Cpu64, JumpDword|DefaultSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk, { Disp32S }
+call, 1, 0xe8, None, 1, Cpu64|CpuAMD64, JumpDword|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk, { Disp16|Disp32|Disp32S }
+call, 1, 0xe8, None, 1, Cpu64|CpuIntel64, JumpDword|DefaultSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk, { Disp32S }
 call, 1, 0xff, 0x2, 1, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|JumpAbsolute }
 call, 1, 0xff, 0x2, 1, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S|JumpAbsolute }
 // Intel Syntax
@@ -330,7 +331,8 @@ lcall, 2, 0x9a, None, 1, CpuNo64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|N
 lcall, 1, 0xff, 0x3, 1, 0, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute }
 
 jmp, 1, 0xeb, None, 1, CpuNo64, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32|Disp32S }
-jmp, 1, 0xeb, None, 1, Cpu64, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp32S }
+jmp, 1, 0xeb, None, 1, Cpu64|CpuAMD64, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32|Disp32S }
+jmp, 1, 0xeb, None, 1, Cpu64|CpuIntel64, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp32S }
 jmp, 1, 0xff, 0x4, 1, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|JumpAbsolute }
 jmp, 1, 0xff, 0x4, 1, Cpu64, Modrm|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S|JumpAbsolute }
 // Intel Syntax.