From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qv1-xf31.google.com (mail-qv1-xf31.google.com [IPv6:2607:f8b0:4864:20::f31]) by sourceware.org (Postfix) with ESMTPS id 012DA3858D32 for ; Mon, 17 Oct 2022 23:24:17 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 012DA3858D32 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-qv1-xf31.google.com with SMTP id i9so8379460qvo.0 for ; Mon, 17 Oct 2022 16:24:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=BmJXwl3Ubicxx/gXBPqOzRsOyfxeuFsAQVg9QJoZzbk=; b=PG6nWlhRKBkaAbWNzhH1/wh984xundkN6/6i2CznSM6aoI9Qn/rt05+PDwPhuit973 F2lrJIancN9jvrVxBKg0f9MGKFrFausnpaVau3dBG7rFVt5VNqEhTU61rvWeUYulhjHZ mQfOVHXMHV3khEoJZip4gh6TgzJjwTb/A5XDta1m3Ebf12XQ37HW77kfNTBYLcyUU4Pk PEKb0rWaejPWsuxqAtV0SHrdUKso4m2p5NJDsaX3BAnE0wo2YYtF74IJkZ80OZfGDze0 dCf8SRCEMvHdNAOwffE0g40K/BZTdcUXbirSOw5XAn4Q4kdXqcIBRZXVVjqKLlBLQEyG mnpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=BmJXwl3Ubicxx/gXBPqOzRsOyfxeuFsAQVg9QJoZzbk=; b=ygwpNa6pAmQ9sesyplgRtUytNODRBHoxJazyBss279PltYS+E+Q8yBnd+rtmq0e4Vo uohvT+4qSLSPVfoEYPysWHOVq0ukWzmm+P8eAiLqBfCWDQ9/ragplXtDa0oBDZAWkQ3H 5Z5v8PynJAlWeCGQ3bxWHZu1tIn9h2Zf2DV4+vhF1CRt48mCKAPv6auPpdPMx9x+k6tz v+Dt172Dn0COjag6Wq6iJkXQMUDpPwzvwEsI1HVrIzIoGAaU3Dc/Lz73FtDboicJh9oe lS0AztScUv5/JK4Ami1RcZlmhZP3ZfiVS3YEQarQxm85UHpKh5bFgFvymSGVyUsyiwo1 hETQ== X-Gm-Message-State: ACrzQf2DTCVyg3quXH13kJ69d0AiWUdOhsxxLowgXAzcVY4Boj7YaSSW L1u5sv+9aFpa76HqC0Dh6a3F4LNivxNDFpEavW8= X-Google-Smtp-Source: AMsMyM4yyRLG7P4Lc9URW8vsQ2o5TWUqIG1TfH/s+P7SLTwpOI3x2OdfeJkMxnUjEBaTFS+3zZFky1gh5Z9ev+7Jz9o= X-Received: by 2002:ad4:4ee4:0:b0:4b1:d60b:c830 with SMTP id dv4-20020ad44ee4000000b004b1d60bc830mr48116qvb.84.1666049057161; Mon, 17 Oct 2022 16:24:17 -0700 (PDT) MIME-Version: 1.0 References: <20221014091248.4920-1-haochen.jiang@intel.com> <20221014091248.4920-7-haochen.jiang@intel.com> In-Reply-To: <20221014091248.4920-7-haochen.jiang@intel.com> From: "H.J. Lu" Date: Mon, 17 Oct 2022 16:23:40 -0700 Message-ID: Subject: Re: [PATCH 06/10] Support Intel RAO-INT To: Haochen Jiang Cc: binutils@sourceware.org, jbeulich@suse.com, Kong Lingling Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-3023.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Fri, Oct 14, 2022 at 2:15 AM Haochen Jiang wrote: > > From: Kong Lingling > > gas/ChangeLog: > > * NEWS: Support Intel RAO-INT. > * config/tc-i386.c: Add raoint. > * doc/c-i386.texi: Document .raoint and noraoint. > * testsuite/gas/i386/i386.exp: Run RAOINT tests. > * testsuite/gas/i386/raoint-intel.d: New test. > * testsuite/gas/i386/raoint.d: Ditto. > * testsuite/gas/i386/raoint.s: Ditto. > * testsuite/gas/i386/x86-64-raoint-intel.d: Ditto. > * testsuite/gas/i386/x86-64-raoint.d: Ditto. > * testsuite/gas/i386/x86-64-raoint.s: Ditto. > > opcodes/ChangeLog: > > * i386-dis.c (MOD_0F38FC): New. > (PREFIX_0F38FC): Ditto. > (mod_table): Add MOD_0F38FC. > (prefix_table): Add PREFIX_0F38FC. > * i386-gen.c: (cpu_flag_init): Add CPU_RAOINT_FLAGS and > CPU_ANY_RAOINT_FLAGS. > * i386-init.h: Regenerated. > * i386-opc.h: (CpuRAOINT): New. > (i386_cpu_flags): Add cpuraoint. > * i386-opc.tbl: Add RAOINT instructions. > * i386-tbl.h: Regenerated. > --- > gas/NEWS | 2 + > gas/config/tc-i386.c | 3 +- > gas/doc/c-i386.texi | 4 +- > gas/testsuite/gas/i386/i386.exp | 4 + > gas/testsuite/gas/i386/raoint-intel.d | 18 + > gas/testsuite/gas/i386/raoint.d | 18 + > gas/testsuite/gas/i386/raoint.s | 15 + > gas/testsuite/gas/i386/x86-64-raoint-intel.d | 18 + > gas/testsuite/gas/i386/x86-64-raoint.d | 18 + > gas/testsuite/gas/i386/x86-64-raoint.s | 15 + > opcodes/i386-dis.c | 16 +- > opcodes/i386-gen.c | 5 + > opcodes/i386-init.h | 514 +- > opcodes/i386-opc.h | 5 +- > opcodes/i386-opc.tbl | 9 + > opcodes/i386-tbl.h | 7874 +++++++++--------- > 16 files changed, 4379 insertions(+), 4159 deletions(-) > create mode 100644 gas/testsuite/gas/i386/raoint-intel.d > create mode 100644 gas/testsuite/gas/i386/raoint.d > create mode 100644 gas/testsuite/gas/i386/raoint.s > create mode 100644 gas/testsuite/gas/i386/x86-64-raoint-intel.d > create mode 100644 gas/testsuite/gas/i386/x86-64-raoint.d > create mode 100644 gas/testsuite/gas/i386/x86-64-raoint.s > > diff --git a/gas/NEWS b/gas/NEWS > index 9757209a9f..f352c5ab89 100644 > --- a/gas/NEWS > +++ b/gas/NEWS > @@ -1,5 +1,7 @@ > -*- text -*- > > +* Add support for Intel RAO-INT instructions. > + > * Add support for Intel CMPccXADD instructions. > > * Add support for Intel AVX-NE-CONVERT instructions. > diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c > index 7045e18cff..07d72d1af1 100644 > --- a/gas/config/tc-i386.c > +++ b/gas/config/tc-i386.c > @@ -1097,7 +1097,8 @@ static const arch_entry cpu_arch[] = > SUBARCH (avx_ifma, AVX_IFMA, ANY_AVX_IFMA, false), > SUBARCH (avx_vnni_int8, AVX_VNNI_INT8, ANY_AVX_VNNI_INT8, false), > SUBARCH (avx_ne_convert, AVX_NE_CONVERT, ANY_AVX_NE_CONVERT, false), > - SUBARCH (cmpccxadd, CMPCCXADD, ANY_CMPCCXADD, false) > + SUBARCH (cmpccxadd, CMPCCXADD, ANY_CMPCCXADD, false), > + SUBARCH (raoint, RAOINT, ANY_RAOINT, false), > }; > > #undef SUBARCH > diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi > index 62202157b3..3832628e6e 100644 > --- a/gas/doc/c-i386.texi > +++ b/gas/doc/c-i386.texi > @@ -217,6 +217,7 @@ accept various extension mnemonics. For example, > @code{avx_vnni_int8}, > @code{avx_ne_convert}, > @code{cmpccxadd}, > +@code{raoint}, > @code{noavx512f}, > @code{noavx512cd}, > @code{noavx512er}, > @@ -241,6 +242,7 @@ accept various extension mnemonics. For example, > @code{noavx_vnni_int8}, > @code{noavx_ne_convert}, > @code{nocmpccxadd}, > +@code{noraoint}, > @code{noenqcmd}, > @code{noserialize}, > @code{notsxldtrk}, > @@ -1542,7 +1544,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are: > @item @samp{.tdx} @tab @samp{.avx_vnni} @tab @samp{.avx512_fp16} > @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt} > @item @samp{.avx_ifma} @tab @samp{.avx_vnni_int8} @tab @samp{.avx_ne_convert} > -@item @samp{.cmpccxadd} > +@item @samp{.cmpccxadd} @tab @samp{.raoint} > @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote} > @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq} > @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk} > diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp > index fb2e2aa446..1eb0eabb6b 100644 > --- a/gas/testsuite/gas/i386/i386.exp > +++ b/gas/testsuite/gas/i386/i386.exp > @@ -486,6 +486,8 @@ if [gas_32_check] then { > run_dump_test "avx-ne-convert" > run_dump_test "avx-ne-convert-intel" > run_list_test "cmpccxadd-inval" > + run_dump_test "raoint" > + run_dump_test "raoint-intel" > run_list_test "sg" > run_dump_test "clzero" > run_dump_test "invlpgb" > @@ -1162,6 +1164,8 @@ if [gas_64_check] then { > run_dump_test "x86-64-avx-ne-convert-intel" > run_dump_test "x86-64-cmpccxadd" > run_dump_test "x86-64-cmpccxadd-intel" > + run_dump_test "x86-64-raoint" > + run_dump_test "x86-64-raoint-intel" > run_dump_test "x86-64-clzero" > run_dump_test "x86-64-mwaitx-bdver4" > run_list_test "x86-64-mwaitx-reg" > diff --git a/gas/testsuite/gas/i386/raoint-intel.d b/gas/testsuite/gas/i386/raoint-intel.d > new file mode 100644 > index 0000000000..b50d423a5f > --- /dev/null > +++ b/gas/testsuite/gas/i386/raoint-intel.d > @@ -0,0 +1,18 @@ > +#as: > +#objdump: -dw -Mintel > +#name: i386 RAOINT insns (Intel disassembly) > +#source: raoint.s > + > +.*: +file format .* > + > +Disassembly of section \.text: > + > +0+ <_start>: > +\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd DWORD PTR \[eax\],edx > +\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand DWORD PTR \[eax\],edx > +\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor DWORD PTR \[eax\],edx > +\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor DWORD PTR \[eax\],edx > +\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd DWORD PTR \[eax\],edx > +\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand DWORD PTR \[eax\],edx > +\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor DWORD PTR \[eax\],edx > +\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor DWORD PTR \[eax\],edx > diff --git a/gas/testsuite/gas/i386/raoint.d b/gas/testsuite/gas/i386/raoint.d > new file mode 100644 > index 0000000000..2c310c5cc7 > --- /dev/null > +++ b/gas/testsuite/gas/i386/raoint.d > @@ -0,0 +1,18 @@ > +#as: > +#objdump: -dw > +#name: i386 RAOINT insns > +#source: raoint.s > + > +.*: +file format .* > + > +Disassembly of section \.text: > + > +0+ <_start>: > +\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd %edx,\(%eax\) > +\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand %edx,\(%eax\) > +\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor %edx,\(%eax\) > +\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor %edx,\(%eax\) > +\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd %edx,\(%eax\) > +\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand %edx,\(%eax\) > +\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor %edx,\(%eax\) > +\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor %edx,\(%eax\) > diff --git a/gas/testsuite/gas/i386/raoint.s b/gas/testsuite/gas/i386/raoint.s > new file mode 100644 > index 0000000000..63398dfb82 > --- /dev/null > +++ b/gas/testsuite/gas/i386/raoint.s > @@ -0,0 +1,15 @@ > +# Check 32bit AVX-NE-CONVERT instructions > + > + .allow_index_reg > + .text > +_start: > + aadd %edx, (%eax) #RAO-INT > + aand %edx, (%eax) #RAO-INT > + aor %edx, (%eax) #RAO-INT > + axor %edx, (%eax) #RAO-INT > + > +.intel_syntax noprefix > + aadd DWORD PTR [eax], %edx #RAO-INT > + aand DWORD PTR [eax], %edx #RAO-INT > + aor DWORD PTR [eax], %edx #RAO-INT > + axor DWORD PTR [eax], %edx #RAO-INT > diff --git a/gas/testsuite/gas/i386/x86-64-raoint-intel.d b/gas/testsuite/gas/i386/x86-64-raoint-intel.d > new file mode 100644 > index 0000000000..d7de4849a2 > --- /dev/null > +++ b/gas/testsuite/gas/i386/x86-64-raoint-intel.d > @@ -0,0 +1,18 @@ > +#as: > +#objdump: -dw -Mintel > +#name: x86_64 RAOINT insns (Intel disassembly) > +#source: x86-64-raoint.s > + > +.*: +file format .* > + > +Disassembly of section \.text: > + > +0+ <_start>: > +\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd QWORD PTR \[rax\],rdx > +\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand QWORD PTR \[rax\],rdx > +\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor QWORD PTR \[rax\],rdx > +\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor QWORD PTR \[rax\],rdx > +\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd QWORD PTR \[rax\],rdx > +\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand QWORD PTR \[rax\],rdx > +\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor QWORD PTR \[rax\],rdx > +\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor QWORD PTR \[rax\],rdx > diff --git a/gas/testsuite/gas/i386/x86-64-raoint.d b/gas/testsuite/gas/i386/x86-64-raoint.d > new file mode 100644 > index 0000000000..711fe48064 > --- /dev/null > +++ b/gas/testsuite/gas/i386/x86-64-raoint.d > @@ -0,0 +1,18 @@ > +#as: > +#objdump: -dw > +#name: x86_64 RAOINT insns > +#source: x86-64-raoint.s > + > +.*: +file format .* > + > +Disassembly of section \.text: > + > +0+ <_start>: > +\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd %rdx,\(%rax\) > +\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand %rdx,\(%rax\) > +\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor %rdx,\(%rax\) > +\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor %rdx,\(%rax\) > +\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd %rdx,\(%rax\) > +\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand %rdx,\(%rax\) > +\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor %rdx,\(%rax\) > +\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor %rdx,\(%rax\) > diff --git a/gas/testsuite/gas/i386/x86-64-raoint.s b/gas/testsuite/gas/i386/x86-64-raoint.s > new file mode 100644 > index 0000000000..28590626ca > --- /dev/null > +++ b/gas/testsuite/gas/i386/x86-64-raoint.s > @@ -0,0 +1,15 @@ > +# Check 64bit RAOINT instructions > + > + .allow_index_reg > + .text > +_start: > + aadd %rdx, (%rax) #RAO-INT > + aand %rdx, (%rax) #RAO-INT > + aor %rdx, (%rax) #RAO-INT > + axor %rdx, (%rax) #RAO-INT > + > +.intel_syntax noprefix > + aadd QWORD PTR [rax], %rdx #RAO-INT > + aand QWORD PTR [rax], %rdx #RAO-INT > + aor QWORD PTR [rax], %rdx #RAO-INT > + axor QWORD PTR [rax], %rdx #RAO-INT > diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c > index 37bbbd3815..60a334bbd6 100644 > --- a/opcodes/i386-dis.c > +++ b/opcodes/i386-dis.c > @@ -887,6 +887,7 @@ enum > MOD_0F38F9, > MOD_0F38FA_PREFIX_1, > MOD_0F38FB_PREFIX_1, > + MOD_0F38FC, > MOD_0F3A0F_PREFIX_1, > > MOD_VEX_0F12_PREFIX_0, > @@ -1086,6 +1087,7 @@ enum > PREFIX_0F38F8, > PREFIX_0F38FA, > PREFIX_0F38FB, > + PREFIX_0F38FC, > PREFIX_0F3A0F, > PREFIX_VEX_0F10, > PREFIX_VEX_0F11, > @@ -3598,6 +3600,14 @@ static const struct dis386 prefix_table[][4] = { > { MOD_TABLE (MOD_0F38FB_PREFIX_1) }, > }, > > + /* PREFIX_0F38FC */ > + { > + { "aadd", { Edq, Gdq }, PREFIX_OPCODE }, > + { "axor", { Edq, Gdq }, PREFIX_OPCODE }, > + { "aand", { Edq, Gdq }, PREFIX_OPCODE }, > + { "aor", { Edq, Gdq }, PREFIX_OPCODE }, -Msuffix doesn't print suffixes. > + }, > + > /* PREFIX_0F3A0F */ > { > { Bad_Opcode }, > @@ -4802,7 +4812,7 @@ static const struct dis386 three_byte_table[][256] = { > { MOD_TABLE (MOD_0F38F9) }, > { PREFIX_TABLE (PREFIX_0F38FA) }, > { PREFIX_TABLE (PREFIX_0F38FB) }, > - { Bad_Opcode }, > + { MOD_TABLE (MOD_0F38FC) }, > { Bad_Opcode }, > { Bad_Opcode }, > { Bad_Opcode }, > @@ -8374,6 +8384,10 @@ static const struct dis386 mod_table[][2] = { > { Bad_Opcode }, > { "encodekey256", { Gd, Ed }, 0 }, > }, > + { > + /* MOD_0F38FC */ > + { PREFIX_TABLE (PREFIX_0F38FC) }, > + }, > { > /* MOD_0F3A0F_PREFIX_1 */ > { Bad_Opcode }, > diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c > index 96d8d2ceb8..3a7511a242 100644 > --- a/opcodes/i386-gen.c > +++ b/opcodes/i386-gen.c > @@ -253,6 +253,8 @@ static initializer cpu_flag_init[] = > "CPU_AVX2_FLAGS|CpuAVX_NE_CONVERT" }, > { "CPU_CMPCCXADD_FLAGS", > "CpuCMPCCXADD" }, > + { "CPU_RAOINT_FLAGS", > + "CpuRAOINT" }, > { "CPU_IAMCU_FLAGS", > "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" }, > { "CPU_ADX_FLAGS", > @@ -455,6 +457,8 @@ static initializer cpu_flag_init[] = > "CpuAVX_NE_CONVERT" }, > { "CPU_ANY_CMPCCXADD_FLAGS", > "CpuCMPCCXADD" }, > + { "CPU_ANY_RAOINT_FLAGS", > + "CpuRAOINT" }, > }; > > static initializer operand_type_init[] = > @@ -660,6 +664,7 @@ static bitfield cpu_flags[] = > BITFIELD (CpuAVX_VNNI_INT8), > BITFIELD (CpuAVX_NE_CONVERT), > BITFIELD (CpuCMPCCXADD), > + BITFIELD (CpuRAOINT), > BITFIELD (CpuMWAITX), > BITFIELD (CpuCLZERO), > BITFIELD (CpuOSPKE), > diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h > index 052c59b162..cb6c372203 100644 > --- a/opcodes/i386-opc.h > +++ b/opcodes/i386-opc.h > @@ -217,6 +217,8 @@ enum > CpuAVX_NE_CONVERT, > /* Intel CMPccXADD instructions support required. */ > CpuCMPCCXADD, > + /* Intel RAO INT Instructions support required. */ > + CpuRAOINT, > /* mwaitx instruction required */ > CpuMWAITX, > /* Clzero instruction required */ > @@ -400,6 +402,7 @@ typedef union i386_cpu_flags > unsigned int cpuavx_vnni_int8:1; > unsigned int cpuavx_ne_convert:1; > unsigned int cpucmpccxadd:1; > + unsigned int cpuraoint:1; > unsigned int cpumwaitx:1; > unsigned int cpuclzero:1; > unsigned int cpuospke:1; > @@ -436,7 +439,7 @@ typedef union i386_cpu_flags > unsigned int cpu64:1; > unsigned int cpuno64:1; > #ifdef CpuUnused > - // unsigned int unused:(CpuNumOfBits - CpuUnused); > + unsigned int unused:(CpuNumOfBits - CpuUnused); > #endif > } bitfield; > unsigned int array[CpuNumOfUints]; > diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl > index 2b704708a4..4affd056b2 100644 > --- a/opcodes/i386-opc.tbl > +++ b/opcodes/i386-opc.tbl > @@ -3317,3 +3317,12 @@ cmpsxadd, 0x66e8, None, CpuCMPCCXADD|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|Swa > cmpzxadd, 0x66e4, None, CpuCMPCCXADD|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|SwapSources|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } > > // CMPCCXADD instructions end. > + > +// RAOINT instructions. > + > +aadd, 0xf38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex} > +aand, 0x660f38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex} > +aor, 0xf20f38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex} > +axor, 0xf30f38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex} l and q suffixes are allowed. Personally, I think l and q suffixes should be used only when they are needed in some forms. > +// RAOINT instructions end. > -- > 2.18.2 > -- H.J.