From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl1-x635.google.com (mail-pl1-x635.google.com [IPv6:2607:f8b0:4864:20::635]) by sourceware.org (Postfix) with ESMTPS id 661A43856276 for ; Fri, 15 Jul 2022 17:48:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 661A43856276 Received: by mail-pl1-x635.google.com with SMTP id b2so3792041plx.7 for ; Fri, 15 Jul 2022 10:48:11 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=pFJ9MgF9nym5sQgU2lm7lPVtdOVxQsjWnaP40+S+by8=; b=UAHc3epZijA84+xDknyy/9jf0jJNLsEEarvpRxxTTsYVRjr6CuzrZvObRdFWHABA9T 19rxZujlII+uQ5xDjl+wJcB7peyk7V35sZvIxv3k/QoBHQU4emJUj6bG4GltkGr9YDO1 l9B8TwmvCarBgBH2NzN/+WeOwDV/EvNsxDCQlF9NCXsfYq2U3LhZHJ2QTT20dI/PHmCr j891c22CJCfgRCR8n58TAOKdmoS8gRUbca+8GgKyc5bZJIkdCmYexthTDGLZmKYhpSoT GcO7aHNJ/H4MDViutQTrnZ+z/Dfo6YExmChwr+tv2KFtDnBL22Q0+esIEqdvG6QhrKXN nSXg== X-Gm-Message-State: AJIora9BcQRDWfp+VcRcceF5UrkuqRGZtwVxcPLQEL94QMJFtpdZ+flZ 7eKvUc7kr5tjLRfZcjhlJ3AbXPnnU91yOPA1vRI= X-Google-Smtp-Source: AGRyM1va/pcalPSnVhh9LJKG37H5MsDS/I9za7WfogeY/4wpJliZiF6FHKYEmN+wU+ldyN/Ze3CfekjDdy1k389wYBI= X-Received: by 2002:a17:90b:1e0e:b0:1ef:97f9:dfb5 with SMTP id pg14-20020a17090b1e0e00b001ef97f9dfb5mr23602342pjb.217.1657907290380; Fri, 15 Jul 2022 10:48:10 -0700 (PDT) MIME-Version: 1.0 References: <72168667-58cd-1a90-ad26-a89e085e679e@suse.com> In-Reply-To: <72168667-58cd-1a90-ad26-a89e085e679e@suse.com> From: "H.J. Lu" Date: Fri, 15 Jul 2022 10:47:34 -0700 Message-ID: Subject: Re: [PATCH v2] x86: re-order insn template fields To: Jan Beulich Cc: Binutils Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-3018.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jul 2022 17:48:12 -0000 On Fri, Jul 15, 2022 at 5:57 AM Jan Beulich wrote: > > This saves quite a number of shift instructions: The "operands" field > can now be retrieved by just masking (no shift), and extracting the > "extension_opcode" field now only requires a (signed) right shift, with > no prereq left one. (Of course there may be architectures where, in a > cross build, there might be no difference at all, e.g. when there are > suitable bitfield extraction insns.) > --- > v2: Add comment to struct insn_template. > > --- a/opcodes/i386-gen.c > +++ b/opcodes/i386-gen.c > @@ -1444,8 +1444,8 @@ output_i386_opcode (FILE *table, const c > fail (_("%s:%d: %s: residual opcode (0x%0*llx) too large\n"), > filename, lineno, name, 2 * length, opcode); > > - fprintf (table, " { \"%s\", 0x%0*llx%s, %s, %lu,\n", > - name, 2 * (int)length, opcode, end, extension_opcode, i); > + fprintf (table, " { \"%s\", 0x%0*llx%s, %lu, %s,\n", > + name, 2 * (int)length, opcode, end, i, extension_opcode); > > process_i386_opcode_modifier (table, opcode_modifier, space, prefix, > operand_types, lineno); > --- a/opcodes/i386-opc.h > +++ b/opcodes/i386-opc.h > @@ -915,6 +915,11 @@ typedef struct insn_template > /* instruction name sans width suffix ("mov" for movl insns) */ > char *name; > > + /* Bitfield arrangement is such that individual fields can be easily > + extracted (in native builds at least) - either by at most a masking > + operation (base_opcode, operands), or by just a (signed) right shift > + (extension_opcode). Please try to maintain this property. */ > + > /* base_opcode is the fundamental opcode byte without optional > prefix(es). */ > unsigned int base_opcode:16; > @@ -929,6 +934,12 @@ typedef struct insn_template > from all other values above. */ > #define Opcode_VexW 0xf /* Operand order controlled by VEX.W. */ > > + /* how many operands */ > + unsigned int operands:3; > + > + /* spare bits */ > + unsigned int :4; > + > /* (Fake) base opcode value for pseudo prefixes. */ > #define PSEUDO_PREFIX 0 > > @@ -952,9 +963,6 @@ typedef struct insn_template > #define Prefix_REX 8 /* {rex} */ > #define Prefix_NoOptimize 9 /* {nooptimize} */ > > - /* how many operands */ > - unsigned int operands:3; > - > /* the bits in opcode_modifier are used to generate the final opcode from > the base_opcode. These bits also are used to detect alternate forms of > the same instruction */ OK. Thanks. -- H.J.