From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 25751 invoked by alias); 17 Feb 2020 16:53:30 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 25741 invoked by uid 89); 17 Feb 2020 16:53:29 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-2.2 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,KAM_NUMSUBJECT,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=no version=3.3.1 spammy=SSE4*, H*f:sk:4f3e523, flavors, sse4* X-HELO: mail-ot1-f66.google.com Received: from mail-ot1-f66.google.com (HELO mail-ot1-f66.google.com) (209.85.210.66) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 17 Feb 2020 16:53:28 +0000 Received: by mail-ot1-f66.google.com with SMTP id i6so16705337otr.7 for ; Mon, 17 Feb 2020 08:53:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=ZPP00wmH7i2axqtdSBPPa1vIp/kdXJ73qoIF7q9tLN4=; b=UhN9ypiBz24qEkYTqLo60I4lH4FeLm+P3ntR6ZZAcnDi5qsV8LLPeeck/X4oJCexUu BzGx02EQXVbEyW6suh85jo7aaRY/v90vZJc3vuLWXPmuv/sjgul+JUKPmJQFvQvdsS3i lEkEv8YVd92qZVM1eQRdOLrsU4+6l2JP5/Q4kqQCIq/HRVexjCpZCYDiUjl4FMr40CKh dM70tb8gb22pJANam0BuTZ7POEUwznh0JvGq6XTbs2aF4i3RDcYf286XGmHgPVjtc2jq wjfPw/UTY/5Y10Lh9DiS6OZk6VxidaY6XlLr3QPvURw2dH9NiLWeAACxAl1J8yLPitDX uwGg== MIME-Version: 1.0 References: <3bc597bb-10f9-80f9-8e00-f28aeb2eea77@suse.com> <4f3e5233-fb2f-a957-2788-8ffde3939ce2@suse.com> <70b8fc74-e036-1064-ab65-5e0cfe5ec401@suse.com> In-Reply-To: From: "H.J. Lu" Date: Mon, 17 Feb 2020 16:53:00 -0000 Message-ID: Subject: Re: [committed, PATCH] x86: Don't disable SSE4a when disabling SSE4 To: Jan Beulich Cc: "binutils@sourceware.org" Content-Type: text/plain; charset="UTF-8" X-IsSubscribed: yes X-SW-Source: 2020-02/txt/msg00408.txt.bz2 On Mon, Feb 17, 2020 at 7:49 AM Jan Beulich wrote: > > On 17.02.2020 16:44, H.J. Lu wrote: > > On Mon, Feb 17, 2020 at 7:32 AM Jan Beulich wrote: > >> > >> On 17.02.2020 16:30, H.J. Lu wrote: > >>> On Mon, Feb 17, 2020 at 7:27 AM Jan Beulich wrote: > >>>> > >>>> On 16.02.2020 17:47, H.J. Lu wrote: > >>>>> On Wed, Feb 12, 2020 at 9:18 AM H.J. Lu wrote: > >>>>>> > >>>>>> On Wed, Feb 12, 2020 at 9:08 AM Jan Beulich wrote: > >>>>>>> > >>>>>>> Since ".arch sse4a" enables SSE3 and earlier, disabling SSE3 should also > >>>>>>> disable SSE4a. And as per its name, ".arch .nosse4" should also do so. > >>>>>>> > >>>>>>> gas/ > >>>>>>> 2020-02-XX Jan Beulich > >>>>>>> > >>>>>>> * config/tc-i386.c (cpu_noarch): Use CPU_ANY_SSE4_FLAGS in > >>>>>>> "nosse4" entry. > >>>>>>> > >>>>>>> opcodes/ > >>>>>>> 2020-02-XX Jan Beulich > >>>>>>> > >>>>>>> * i386-gen.c (cpu_flag_init): Move CpuSSE4a from > >>>>>>> CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add > >>>>>>> CPU_ANY_SSE4_FLAGS entry. > >>>>>>> * i386-init.h: Re-generate. > >>>>>>> > >>>>>> > >>>>>> OK. > >>>>>> > >>>>>> Thanks. > >>>>> > >>>>> commit 7deea9aad8 changed nosse4 to include CpuSSE4a. But AMD SSE4a is > >>>>> a superset of SSE3 and Intel SSE4 is a superset of SSSE3. Disable Intel > >>>>> SSE4 shouldn't disable AMD SSE4a. This patch restores nosse4. It also > >>>>> adds .sse4a and nosse4a. > >>>> > >>>> And where is it said that "nosse4" means only the Intel flavors? As > >>>> said in the commit message of said change, to me the clear implication > >>>> is that anything called SSE4* will get disabled. > >>>> > >>> > >>> SSE4 refers to SSE4 from Intel, which includes SSE4.1 and SSE4.2. > >>> SSE4a from AMD is unrelated from Intel SSE4. > >> > >> Repeating my question then: Where is this being said? (Best imo > >> would be to delete ".arch .nosse4" support then, eliminating > >> the ambiguity.) > > > > We have both .sse4 and nosse4 which are aliases for SSE4.2. Please > > feel free to add documentation. > > If it's not documented, then it's not clear at all what the intention > is. I'm certainly not going to add documentation saying something that > I don't believe should be said. I.e. if I were to add documentation > here, it'd say .nosse4 covers all three SSE4* variants (and it would > then be a bug of the implementation that this isn't the case). >From gcc/config/i386/i386.opt: msse4.1 Target Report Mask(ISA_SSE4_1) Var(ix86_isa_flags) Save Support MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 built-in functions and code generation. msse4.2 Target Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation. msse4 Target RejectNegative Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation. mno-sse4 Target RejectNegative Report InverseMask(ISA_SSE4_1) Var(ix86_isa_flags) Save Do not support SSE4.1 and SSE4.2 built-in functions and code generation. SSE4 is for Intel SSE4 only. > Just like for the MOVSX/MOVZX issue, I really dislike you making > statements of things that were (apparently) never settled on. > > Jan -- H.J.