From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pg1-x52e.google.com (mail-pg1-x52e.google.com [IPv6:2607:f8b0:4864:20::52e]) by sourceware.org (Postfix) with ESMTPS id A357D3858294 for ; Fri, 5 Aug 2022 22:47:05 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org A357D3858294 Received: by mail-pg1-x52e.google.com with SMTP id s206so3810449pgs.3 for ; Fri, 05 Aug 2022 15:47:05 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc; bh=/aYx8nS27maJYmeWb2KebDKBaAVxCv0XiwKeLzhwSW0=; b=vCdibVANnk91DlknIs0DVvMIdDfEX9SKM6MBJOCfeUCcawJoAopM3a6up7upQ3HOC2 qKgwquQ890tKqKb7pIHoI99yGZ6dD+LbHql4HLP82WV5bD1DNyTl6sGIFx1figQLaN1J F29/zayVYXtKQbuePzriuPnFUoqjt52UPWd5yEPi860czGXbh6fGgRQELlP5WkFlNQwP musLumdtble5V4f2fF8SPkUA18WisLN2Y8kXWFpJ6re9RtTbTjmf3LapwJodLyTj7gnZ bZmizHar8ELazXBl3vs2VeW7GG76fcN0YweEfvuUuxsJazfTDkmWdDJlGipxyBxx/wXW MMLg== X-Gm-Message-State: ACgBeo2lzxdQbtl4AV7o6c+BppWs2A8BubIR8nsaLr2QZGBehJE6WqK5 3lHz8EbHXsge2wq9u3MA22N8WXxymJ60qUBIzTnaBneJ X-Google-Smtp-Source: AA6agR71wYvVR38ApIDmV+YZKA+tV51vZM2SFLnR2hN/MQB3TmxWvuQGVOXOE0gcSsorjqzttfycV5jTlpyW3wdxMfc= X-Received: by 2002:a05:6a00:158a:b0:52e:5e04:6bf with SMTP id u10-20020a056a00158a00b0052e5e0406bfmr8844999pfk.64.1659739624583; Fri, 05 Aug 2022 15:47:04 -0700 (PDT) MIME-Version: 1.0 References: <82a24463-2f28-5182-cab0-4867b177bdb5@suse.com> In-Reply-To: <82a24463-2f28-5182-cab0-4867b177bdb5@suse.com> From: "H.J. Lu" Date: Fri, 5 Aug 2022 15:46:28 -0700 Message-ID: Subject: Re: [PATCH 04/12] x86: adjust MOVSD attributes To: Jan Beulich Cc: Binutils Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-3018.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 05 Aug 2022 22:47:07 -0000 On Fri, Aug 5, 2022 at 5:21 AM Jan Beulich wrote: > > The non-SSE2AVX form of the SIMD variant of the instruction needlessly > has the (still multi-purpose) IgnoreSize attribute. All other similar > SSE2 insns use NoRex64 instead. Make this consistent, noting that the > SSE2AVX form can't have the same change made - there the memory operand > doesn't at the same time permit RegXMM (which logic uses when deciding > whether a Q suffix is okay outside of 64-bit mode). > > --- a/opcodes/i386-opc.tbl > +++ b/opcodes/i386-opc.tbl > @@ -1187,7 +1187,7 @@ movmskpd, 0x660f50, None, movntpd, 0x660f2b, None, , Modrm||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex } > movsd, 0xf210, None, CpuAVX, D|Modrm|Vex=3|Space0F|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM } > movsd, 0xf210, None, CpuAVX, D|Modrm|Vex=3|Space0F|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXMM } > -movsd, 0xf20f10, None, CpuSSE2, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } > +movsd, 0xf20f10, None, CpuSSE2, D|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } > movupd, 0x660f10, None, , D|Modrm||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } > mulpd, 0x660f59, None, , Modrm|||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } > mulsd, 0xf20f59, None, , Modrm|||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } > OK. Thanks. -- H.J.