From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qv1-xf2b.google.com (mail-qv1-xf2b.google.com [IPv6:2607:f8b0:4864:20::f2b]) by sourceware.org (Postfix) with ESMTPS id 94CDB3858D28 for ; Tue, 11 Oct 2022 17:45:26 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 94CDB3858D28 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-qv1-xf2b.google.com with SMTP id z18so9419857qvn.6 for ; Tue, 11 Oct 2022 10:45:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=wR2uQTmLOQ+601yOUKX0Ps65emxC4ItjQ4QSTKl8Z58=; b=TcyvvlAeZtkQ/IrdYouC5jrn6WIfUC8oDLtB8wNN/cRmC2r2kNLMkarq1tjFrZrn94 jDoLHBOGcA0gHEDe/MJK/ay9FcDanImDsBE+CiaDjqfiFQ1Qr4v2gjdImRRHas2O59yM QckoUV/HV5Ow2yPyoi5NdwJ0XsntJ1NO/XOaBZ6S2lynT1HxruabJEnFr9oqxfyVHGcK 339RQQtih0MhkxBTvRE+vMuAPtN0hNkZjEuEX8bsn2KXI8gXicSfcZ2fBQ6nLuI21hjj 5hLev5LVw/V6Qvs+YS2ouXBEqJOgHfFB7O2BWqA5Dl6fAGcYnrPuGffH35STwbEuRJKB zpLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=wR2uQTmLOQ+601yOUKX0Ps65emxC4ItjQ4QSTKl8Z58=; b=w+XImfnNsu4AxB+mJL4aE8zPxLRAjeCsdRe9PMqDoAV5BJwTTHktn+fU0jczqaPwao IiaA88b2NAv9Kce+9BJd79A+d90noiAFyiTkQTToCyUMrZ08z/V73xZbjpKEOLdao/1R EapDJL0a96sIPdFAsSIGr1z65ZgTMpf4yZAd0iXqCtDchYULFhAi7L9+LSi73xJvDSoB JU1kM6cxwHxVd9pP1Nc8SWREGdQESNS9H0ppNLQ4VLF4C38elZxSYBHZCC3J76RF/ZVC Kkp8xbUu/j2CCU4bP1Y+08peWBJ3ILy5Hcq0s67c47fEwni31/X6aPvRDqMPM2/JkT+1 mjCQ== X-Gm-Message-State: ACrzQf21SMwz9jLcFnQZ3rsOT/UyAJ7zAuS4kWYidiovqDCbtMIevrWc pNRknCCjTC+ReEIq21wjTeDoyUNlWg0hAODAJZP8Jye3 X-Google-Smtp-Source: AMsMyM7kuPUVnDEmBlr1KuZx91tRFdf+Aerlpb0pS0dJGN5BaLob7tO0xQWfHmKm6oAiGaTpF0QLZ7mIZFEiwf4jEcQ= X-Received: by 2002:a05:6214:4101:b0:4af:8cdc:20c4 with SMTP id kc1-20020a056214410100b004af8cdc20c4mr20475770qvb.6.1665510325822; Tue, 11 Oct 2022 10:45:25 -0700 (PDT) MIME-Version: 1.0 References: <20e2773a-2e47-869b-1900-709f8ad4cd6b@suse.com> In-Reply-To: From: "H.J. Lu" Date: Tue, 11 Oct 2022 10:44:49 -0700 Message-ID: Subject: Re: [PATCH v3 4/7] x86-64: further re-work insn/suffix recognition to also cover MOVSL To: Jan Beulich Cc: Binutils Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-3018.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Wed, Oct 5, 2022 at 12:24 AM Jan Beulich wrote: > > PR gas/29524 > In order to make MOVSL{,Q} behave similarly to MOVSB{W,L,Q} and > MOVSW{L,Q} we need to defer parse_insn()'s emitting of errors unrelated > to prefix parsing. Utilize i.error just like match_template() does. Since movs{b,w,l,q} are string instructions, integer sign extensions require a suffix to specify the destination size. This is different from other integer instructions. Since only the new assembler allows the implicit suffix, it won't be easy to use. We should improve error messages, but allowing new syntax doesn't help much. > --- > v3: Re-base over changes to earlier patches (incl use of Pass2). > > --- a/gas/config/tc-i386.c > +++ b/gas/config/tc-i386.c > @@ -236,6 +236,8 @@ enum i386_error > unsupported_with_intel_mnemonic, > unsupported_syntax, > unsupported, > + unsupported_on_arch, > + unsupported_64bit, > invalid_sib_address, > invalid_vsib_address, > invalid_vector_register_set, > @@ -4849,6 +4851,15 @@ md_assemble (char *line) > { > if (pass1_mnem != NULL) > goto match_error; > + if (i.error != no_error) > + { > + gas_assert (current_templates != NULL); > + if (current_templates->start->opcode_modifier.pass2 && !i.suffix) > + goto no_match; > + /* No point in trying a 2nd pass - it'll only find the same suffix > + again. */ > + goto match_error; > + } > return; > } > if (current_templates->start->opcode_modifier.pass2) > @@ -4948,12 +4959,21 @@ md_assemble (char *line) > { > line = copy; > copy = NULL; > + no_match: > pass1_err = i.error; > pass1_mnem = current_templates->start->name; > goto retry; > } > - free (copy); > + > + /* If a non-/only-64bit template (group) was found in pass 1, and if > + _some_ template (group) was found in pass 2, squash pass 1's > + error. */ > + if (pass1_err == unsupported_64bit) > + pass1_mnem = NULL; > + > match_error: > + free (copy); > + > switch (pass1_mnem ? pass1_err : i.error) > { > default: > @@ -4986,6 +5006,17 @@ md_assemble (char *line) > as_bad (_("unsupported instruction `%s'"), > pass1_mnem ? pass1_mnem : current_templates->start->name); > return; > + case unsupported_on_arch: > + as_bad (_("`%s' is not supported on `%s%s'"), > + pass1_mnem ? pass1_mnem : current_templates->start->name, > + cpu_arch_name ? cpu_arch_name : default_arch, > + cpu_sub_arch_name ? cpu_sub_arch_name : ""); > + return; > + case unsupported_64bit: > + as_bad (_("`%s' is %s supported in 64-bit mode"), > + pass1_mnem ? pass1_mnem : current_templates->start->name, > + flag_code == CODE_64BIT ? _("not") : _("only")); > + return; > case invalid_sib_address: > err_msg = _("invalid SIB address"); > break; > @@ -5601,16 +5632,13 @@ parse_insn (const char *line, char *mnem > return l; > } > > - if (!(supported & CPU_FLAGS_64BIT_MATCH)) > - as_bad (flag_code == CODE_64BIT > - ? _("`%s' is not supported in 64-bit mode") > - : _("`%s' is only supported in 64-bit mode"), > - current_templates->start->name); > - else > - as_bad (_("`%s' is not supported on `%s%s'"), > - current_templates->start->name, > - cpu_arch_name ? cpu_arch_name : default_arch, > - cpu_sub_arch_name ? cpu_sub_arch_name : ""); > + if (pass1) > + { > + if (supported & CPU_FLAGS_64BIT_MATCH) > + i.error = unsupported_on_arch; > + else > + i.error = unsupported_64bit; > + } > > return NULL; > } > --- a/gas/testsuite/gas/i386/movs.s > +++ b/gas/testsuite/gas/i386/movs.s > @@ -30,4 +30,10 @@ movs: > .ifdef x86_64 > movswq %ax,%rax > movswq (%rax),%rax > + > + movsl %eax,%rax > + movsl (%rax),%rax > + > + movslq %eax,%rax > + movslq (%rax),%rax > .endif > --- a/gas/testsuite/gas/i386/movx64.l > +++ b/gas/testsuite/gas/i386/movx64.l > @@ -241,6 +241,46 @@ > [ ]*[1-9][0-9]*[ ]+movswq %eax, %rcx > [ ]*[1-9][0-9]*[ ]+movswq %rax, %rcx > [ ]*[1-9][0-9]*[ ]* > +[ ]*[1-9][0-9]*[ ]+movsl %al, %cl > +[ ]*[1-9][0-9]*[ ]+movsl %ax, %cl > +[ ]*[1-9][0-9]*[ ]+movsl %eax, %cl > +[ ]*[1-9][0-9]*[ ]+movsl %rax, %cl > +[ ]*[1-9][0-9]*[ ]* > +[ ]*[1-9][0-9]*[ ]+movsl %al, %cx > +[ ]*[1-9][0-9]*[ ]+movsl %ax, %cx > +[ ]*[1-9][0-9]*[ ]+movsl %eax, %cx > +[ ]*[1-9][0-9]*[ ]+movsl %rax, %cx > +[ ]*[1-9][0-9]*[ ]* > +[ ]*[1-9][0-9]*[ ]+movsl %al, %ecx > +[ ]*[1-9][0-9]*[ ]+movsl %ax, %ecx > +[ ]*[1-9][0-9]*[ ]+movsl %eax, %ecx > +[ ]*[1-9][0-9]*[ ]+movsl %rax, %ecx > +[ ]*[1-9][0-9]*[ ]* > +[ ]*[1-9][0-9]*[ ]+movsl %al, %rcx > +[ ]*[1-9][0-9]*[ ]+movsl %ax, %rcx > +[ ]*[1-9][0-9]* \?\?\?\? 4863C8[ ]+movsl %eax, %rcx > +[ ]*[1-9][0-9]*[ ]+movsl %rax, %rcx > +[ ]*[1-9][0-9]*[ ]* > +[ ]*[1-9][0-9]*[ ]+movslq %al, %cl > +[ ]*[1-9][0-9]*[ ]+movslq %ax, %cl > +[ ]*[1-9][0-9]*[ ]+movslq %eax, %cl > +[ ]*[1-9][0-9]*[ ]+movslq %rax, %cl > +[ ]*[1-9][0-9]*[ ]* > +[ ]*[1-9][0-9]*[ ]+movslq %al, %cx > +[ ]*[1-9][0-9]*[ ]+movslq %ax, %cx > +[ ]*[1-9][0-9]*[ ]+movslq %eax, %cx > +[ ]*[1-9][0-9]*[ ]+movslq %rax, %cx > +[ ]*[1-9][0-9]*[ ]* > +[ ]*[1-9][0-9]*[ ]+movslq %al, %ecx > +[ ]*[1-9][0-9]*[ ]+movslq %ax, %ecx > +[ ]*[1-9][0-9]*[ ]+movslq %eax, %ecx > +[ ]*[1-9][0-9]*[ ]+movslq %rax, %ecx > +[ ]*[1-9][0-9]*[ ]* > +[ ]*[1-9][0-9]*[ ]+movslq %al, %rcx > +[ ]*[1-9][0-9]*[ ]+movslq %ax, %rcx > +[ ]*[1-9][0-9]* \?\?\?\? 4863C8[ ]+movslq %eax, %rcx > +[ ]*[1-9][0-9]*[ ]+movslq %rax, %rcx > +[ ]*[1-9][0-9]*[ ]* > [ ]*[1-9][0-9]*[ ]+movzx: > [ ]*[1-9][0-9]*[ ]+movzx %al, %cl > [ ]*[1-9][0-9]*[ ]+movzx %ax, %cl > --- a/gas/testsuite/gas/i386/movx64.s > +++ b/gas/testsuite/gas/i386/movx64.s > @@ -241,6 +241,46 @@ movsx: > movswq %eax, %rcx > movswq %rax, %rcx > > + movsl %al, %cl > + movsl %ax, %cl > + movsl %eax, %cl > + movsl %rax, %cl > + > + movsl %al, %cx > + movsl %ax, %cx > + movsl %eax, %cx > + movsl %rax, %cx > + > + movsl %al, %ecx > + movsl %ax, %ecx > + movsl %eax, %ecx > + movsl %rax, %ecx > + > + movsl %al, %rcx > + movsl %ax, %rcx > + movsl %eax, %rcx > + movsl %rax, %rcx > + > + movslq %al, %cl > + movslq %ax, %cl > + movslq %eax, %cl > + movslq %rax, %cl > + > + movslq %al, %cx > + movslq %ax, %cx > + movslq %eax, %cx > + movslq %rax, %cx > + > + movslq %al, %ecx > + movslq %ax, %ecx > + movslq %eax, %ecx > + movslq %rax, %ecx > + > + movslq %al, %rcx > + movslq %ax, %rcx > + movslq %eax, %rcx > + movslq %rax, %rcx > + > movzx: > movzx %al, %cl > movzx %ax, %cl > --- a/opcodes/i386-opc.tbl > +++ b/opcodes/i386-opc.tbl > @@ -164,9 +164,7 @@ movbe, 0x0f38f0, None, CpuMovbe, D|Modrm > // Move with sign extend. > movsb, 0xfbe, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf|Pass2, { Reg8|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } > movsw, 0xfbf, None, Cpu386, Modrm|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|Pass2, { Reg16|Unspecified|BaseIndex, Reg32|Reg64 } > -// "movslq" must not be converted into "movsl" to avoid conflict with the > -// "movsl" string move instruction. > -movslq, 0x63, None, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg32|Dword|Unspecified|BaseIndex, Reg64 } > +movsl, 0x63, None, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|Pass2, { Reg32|Unspecified|BaseIndex, Reg64 } > movsx, 0xfbe, None, Cpu386, W|Modrm|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } > movsx, 0x63, None, Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, Reg32|Reg64 } > movsxd, 0x63, None, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, Reg32|Reg64 } > -- H.J.