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Lu" Date: Wed, 2 Nov 2022 19:44:25 -0700 Message-ID: Subject: Re: [PATCH 2/2] Support Intel AVX-NE-CONVERT To: "Kong, Lingling" Cc: "Beulich, Jan" , "Jiang, Haochen" , "binutils@sourceware.org" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-3023.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Wed, Nov 2, 2022 at 1:50 AM Kong, Lingling wro= te: > > > On 01.11.2022 10:04, Kong, Lingling wrote: > > > --- a/opcodes/i386-dis.c > > > +++ b/opcodes/i386-dis.c > > > @@ -942,6 +942,8 @@ enum > > > MOD_VEX_0F385E_X86_64_P_3_W_0, > > > MOD_VEX_0F388C, > > > MOD_VEX_0F388E, > > > + MOD_VEX_0F38B0, > > > + MOD_VEX_0F38B1, > > > MOD_VEX_0F3A30_L_0, > > > MOD_VEX_0F3A31_L_0, > > > MOD_VEX_0F3A32_L_0, > > > @@ -1140,6 +1142,9 @@ enum > > > PREFIX_VEX_0F3851_W_0, > > > PREFIX_VEX_0F385C_X86_64, > > > PREFIX_VEX_0F385E_X86_64, > > > + PREFIX_VEX_0F3872, > > > + PREFIX_VEX_0F38B0_M_0_W_0, > > > + PREFIX_VEX_0F38B1_M_0_W_0, > > > PREFIX_VEX_0F38F5_L_0, > > > PREFIX_VEX_0F38F6_L_0, > > > PREFIX_VEX_0F38F7_L_0, > > > @@ -1556,8 +1561,11 @@ enum > > > VEX_W_0F385E_X86_64_P_1, > > > VEX_W_0F385E_X86_64_P_2, > > > VEX_W_0F385E_X86_64_P_3, > > > + VEX_W_0F3872_P_1, > > > VEX_W_0F3878, > > > VEX_W_0F3879, > > > + VEX_W_0F38B0_M_0, > > > + VEX_W_0F38B1_M_0, > > > VEX_W_0F38B4, > > > VEX_W_0F38B5, > > > VEX_W_0F38CF, > > > @@ -4093,6 +4101,27 @@ static const struct dis386 prefix_table[][4] = =3D { > > > { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3) }, > > > }, > > > > > > + /* PREFIX_VEX_0F3872 */ > > > + { > > > + { Bad_Opcode }, > > > + { VEX_W_TABLE (VEX_W_0F3872_P_1) }, }, > > > + > > > + /* PREFIX_VEX_0F38B0_M_0_W_0 */ > > > + { > > > + { "vcvtneoph2ps", { XM, Mx }, 0 }, > > > + { "vcvtneebf162ps", { XM, Mx }, 0 }, > > > + { "vcvtneeph2ps", { XM, Mx }, 0 }, > > > + { "vcvtneobf162ps", { XM, Mx }, 0 }, }, > > > > With the use of Mx here I see no reason to have decode go through mod_t= able[]. > > And then ... > > Yes, Fixed. Thanks a lot! > > > > + /* PREFIX_VEX_0F38B1_M_0_W_0 */ > > > + { > > > + { Bad_Opcode }, > > > + { "vbcstnebf162ps", { XM, Ew }, 0 }, > > > + { "vbcstnesh2ps", { XM, Ew }, 0 }, }, > > > > ... this should also engage OP_M() rather than OP_E(), removing the mod= _table[] > > decode step here as well. Obviously you'll need to add Mw for that to w= ork. > > > Good advice! Now Changed Ew to Mw, and no longer go through the w table. > Patch changes as follows. > > Subject: [PATCH 1/2] Support Intel AVX-NE-CONVERT > > gas/ChangeLog: > > * NEWS: Support Intel AVX-NE-CONVERT. > * config/tc-i386.c: Add avx_ne_convert. > * doc/c-i386.texi: Document .avx_ne_convert. > * testsuite/gas/i386/i386.exp: Run AVX NE CONVERT tests. > * testsuite/gas/i386/avx-ne-convert-intel.d: New test. > * testsuite/gas/i386/avx-ne-convert.d: Ditto. > * testsuite/gas/i386/avx-ne-convert.s: Ditto. > * testsuite/gas/i386/x86-64-avx-ne-convert-intel.d: Ditto. > * testsuite/gas/i386/x86-64-avx-ne-convert.d: Ditto. > * testsuite/gas/i386/x86-64-avx-ne-convert.s: Ditto. > > opcodes/ChangeLog: > > * i386-dis.c (Mw): New. > (PREFIX_VEX_0F3872): Ditto. > (PREFIX_VEX_0F38B0_W_0): Ditto. > (PREFIX_VEX_0F38B1_W_0): Ditto. > (VEX_W_0F3872_P_1): Ditto. > (VEX_W_0F38B0): Ditto. > (VEX_W_0F38B1): Ditto. > (prefix_table): Add PREFIX_VEX_0F3872, PREFIX_VEX_0F38B0_W_0, > PREFIX_VEX_0F38B1_W_0. > (vex_w_table): Add VEX_W_0F3872_P_1, VEX_W_0F38B0, VEX_W_0F38B1. > * i386-gen.c (cpu_flag_init): Add CPU_AVX_NE_CONVERT_FLGAS and > CPU_ANY_AVX_NE_CONVERT_FLAGS. > (cpu_flags): Add CpuAVX_NE_CONVERT. > * i386-init.h: Regenerated. > * i386-opc.h (CpuAVX_NE CONVERT): New. > (i386_cpu_flags): Add cpuavx_ne_convert. > * i386-opc.tbl: Add Intel AVX-NE-CONVERT instructions. > * i386-tbl.h: Regenerated. > --- > gas/NEWS | 2 + > gas/config/tc-i386.c | 1 + > gas/doc/c-i386.texi | 2 + > gas/testsuite/gas/i386/avx-ne-convert-intel.d | 170 + > gas/testsuite/gas/i386/avx-ne-convert.d | 170 + > gas/testsuite/gas/i386/avx-ne-convert.s | 167 + > gas/testsuite/gas/i386/i386.exp | 4 + > .../gas/i386/x86-64-avx-ne-convert-intel.d | 170 + > .../gas/i386/x86-64-avx-ne-convert.d | 170 + > .../gas/i386/x86-64-avx-ne-convert.s | 167 + > opcodes/i386-dis.c | 46 +- > opcodes/i386-gen.c | 7 +- > opcodes/i386-init.h | 520 +- > opcodes/i386-opc.h | 3 + > opcodes/i386-opc.tbl | 12 + > opcodes/i386-tbl.h | 7978 +++++++++-------- > 16 files changed, 5420 insertions(+), 4169 deletions(-) > create mode 100644 gas/testsuite/gas/i386/avx-ne-convert-intel.d > create mode 100644 gas/testsuite/gas/i386/avx-ne-convert.d > create mode 100644 gas/testsuite/gas/i386/avx-ne-convert.s > create mode 100644 gas/testsuite/gas/i386/x86-64-avx-ne-convert-intel.d > create mode 100644 gas/testsuite/gas/i386/x86-64-avx-ne-convert.d > create mode 100644 gas/testsuite/gas/i386/x86-64-avx-ne-convert.s > > diff --git a/gas/NEWS b/gas/NEWS > index e7cf4d5bfc..f35e8a93a0 100644 > --- a/gas/NEWS > +++ b/gas/NEWS > @@ -1,5 +1,7 @@ > -*- text -*- > > +* Add support for Intel AVX-NE-CONVERT instructions. > + > * Add support for Intel MSRLIST instructions. > > * Add support for Intel WRMSRNS instructions. > diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c > index 992ae94f1f..b6004ce327 100644 > --- a/gas/config/tc-i386.c > +++ b/gas/config/tc-i386.c > @@ -1101,6 +1101,7 @@ static const arch_entry cpu_arch[] =3D > SUBARCH (cmpccxadd, CMPCCXADD, ANY_CMPCCXADD, false), > SUBARCH (wrmsrns, WRMSRNS, ANY_WRMSRNS, false), > SUBARCH (msrlist, MSRLIST, ANY_MSRLIST, false), > + SUBARCH (avx_ne_convert, AVX_NE_CONVERT, ANY_AVX_NE_CONVERT, false), > }; > > #undef SUBARCH > diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi > index 1774979a83..0ef1cece48 100644 > --- a/gas/doc/c-i386.texi > +++ b/gas/doc/c-i386.texi > @@ -200,6 +200,7 @@ accept various extension mnemonics. For example, > @code{cmpccxadd}, > @code{wrmsrns}, > @code{msrlist}, > +@code{avx_ne_convert}, > @code{amx_int8}, > @code{amx_bf16}, > @code{amx_fp16}, > @@ -1495,6 +1496,7 @@ supported on the CPU specified. The choices for @v= ar{cpu_type} are: > @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.i= bt} > @item @samp{.prefetchi} @tab @samp{.avx_ifma} @tab @samp{.avx_vnni_int8} > @item @samp{.cmpccxadd} @tab @samp{.wrmsrns} @tab @samp{.msrlist} > +@item @samp{.avx_ne_convert} > @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @s= amp{.cldemote} > @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpcl= mulqdq} > @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @s= amp{.tsxldtrk} > diff --git a/gas/testsuite/gas/i386/avx-ne-convert-intel.d b/gas/testsuit= e/gas/i386/avx-ne-convert-intel.d > new file mode 100644 > index 0000000000..490fd9516f > --- /dev/null > +++ b/gas/testsuite/gas/i386/avx-ne-convert-intel.d > @@ -0,0 +1,170 @@ > +#as: > +#objdump: -dw -Mintel > +#name: i386 AVX-NE-CONVERT insns (Intel disassembly) > +#source: avx-ne-convert.s > + > +.*: +file format .* > + > +Disassembly of section \.text: > + > +0+ <_start>: > +\s*[a-f0-9]+:\s*c4 e2 7a b1 b4 f4 00 00 00 10\s+vbcstnebf162ps xmm6,WORD= PTR \[esp\+esi\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 e2 7a b1 31\s+vbcstnebf162ps xmm6,WORD PTR \[ecx\] > +\s*[a-f0-9]+:\s*c4 e2 7a b1 b1 fe 00 00 00\s+vbcstnebf162ps xmm6,WORD PT= R \[ecx\+0xfe\] > +\s*[a-f0-9]+:\s*c4 e2 7a b1 b2 00 ff ff ff\s+vbcstnebf162ps xmm6,WORD PT= R \[edx-0x100\] > +\s*[a-f0-9]+:\s*c4 e2 7e b1 b4 f4 00 00 00 10\s+vbcstnebf162ps ymm6,WORD= PTR \[esp\+esi\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 e2 7e b1 31\s+vbcstnebf162ps ymm6,WORD PTR \[ecx\] > +\s*[a-f0-9]+:\s*c4 e2 7e b1 b1 fe 00 00 00\s+vbcstnebf162ps ymm6,WORD PT= R \[ecx\+0xfe\] > +\s*[a-f0-9]+:\s*c4 e2 7e b1 b2 00 ff ff ff\s+vbcstnebf162ps ymm6,WORD PT= R \[edx-0x100\] > +\s*[a-f0-9]+:\s*c4 e2 79 b1 b4 f4 00 00 00 10\s+vbcstnesh2ps xmm6,WORD P= TR \[esp\+esi\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 e2 79 b1 31\s+vbcstnesh2ps xmm6,WORD PTR \[ecx\] > +\s*[a-f0-9]+:\s*c4 e2 79 b1 b1 fe 00 00 00\s+vbcstnesh2ps xmm6,WORD PTR = \[ecx\+0xfe\] > +\s*[a-f0-9]+:\s*c4 e2 79 b1 b2 00 ff ff ff\s+vbcstnesh2ps xmm6,WORD PTR = \[edx-0x100\] > +\s*[a-f0-9]+:\s*c4 e2 7d b1 b4 f4 00 00 00 10\s+vbcstnesh2ps ymm6,WORD P= TR \[esp\+esi\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 e2 7d b1 31\s+vbcstnesh2ps ymm6,WORD PTR \[ecx\] > +\s*[a-f0-9]+:\s*c4 e2 7d b1 b1 fe 00 00 00\s+vbcstnesh2ps ymm6,WORD PTR = \[ecx\+0xfe\] > +\s*[a-f0-9]+:\s*c4 e2 7d b1 b2 00 ff ff ff\s+vbcstnesh2ps ymm6,WORD PTR = \[edx-0x100\] > +\s*[a-f0-9]+:\s*c4 e2 7a b0 b4 f4 00 00 00 10\s+vcvtneebf162ps xmm6,XMMW= ORD PTR \[esp\+esi\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 e2 7a b0 31\s+vcvtneebf162ps xmm6,XMMWORD PTR \[ecx\] > +\s*[a-f0-9]+:\s*c4 e2 7a b0 b1 f0 07 00 00\s+vcvtneebf162ps xmm6,XMMWORD= PTR \[ecx\+0x7f0\] > +\s*[a-f0-9]+:\s*c4 e2 7a b0 b2 00 f8 ff ff\s+vcvtneebf162ps xmm6,XMMWORD= PTR \[edx-0x800\] > +\s*[a-f0-9]+:\s*c4 e2 7e b0 b4 f4 00 00 00 10\s+vcvtneebf162ps ymm6,YMMW= ORD PTR \[esp\+esi\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 e2 7e b0 31\s+vcvtneebf162ps ymm6,YMMWORD PTR \[ecx\] > +\s*[a-f0-9]+:\s*c4 e2 7e b0 b1 e0 0f 00 00\s+vcvtneebf162ps ymm6,YMMWORD= PTR \[ecx\+0xfe0\] > +\s*[a-f0-9]+:\s*c4 e2 7e b0 b2 00 f0 ff ff\s+vcvtneebf162ps ymm6,YMMWORD= PTR \[edx-0x1000\] > +\s*[a-f0-9]+:\s*c4 e2 79 b0 b4 f4 00 00 00 10\s+vcvtneeph2ps xmm6,XMMWOR= D PTR \[esp\+esi\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 e2 79 b0 31\s+vcvtneeph2ps xmm6,XMMWORD PTR \[ecx\] > +\s*[a-f0-9]+:\s*c4 e2 79 b0 b1 f0 07 00 00\s+vcvtneeph2ps xmm6,XMMWORD P= TR \[ecx\+0x7f0\] > +\s*[a-f0-9]+:\s*c4 e2 79 b0 b2 00 f8 ff ff\s+vcvtneeph2ps xmm6,XMMWORD P= TR \[edx-0x800\] > +\s*[a-f0-9]+:\s*c4 e2 7d b0 b4 f4 00 00 00 10\s+vcvtneeph2ps ymm6,YMMWOR= D PTR \[esp\+esi\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 e2 7d b0 31\s+vcvtneeph2ps ymm6,YMMWORD PTR \[ecx\] > +\s*[a-f0-9]+:\s*c4 e2 7d b0 b1 e0 0f 00 00\s+vcvtneeph2ps ymm6,YMMWORD P= TR \[ecx\+0xfe0\] > +\s*[a-f0-9]+:\s*c4 e2 7d b0 b2 00 f0 ff ff\s+vcvtneeph2ps ymm6,YMMWORD P= TR \[edx-0x1000\] > +\s*[a-f0-9]+:\s*c4 e2 7b b0 b4 f4 00 00 00 10\s+vcvtneobf162ps xmm6,XMMW= ORD PTR \[esp\+esi\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 e2 7b b0 31\s+vcvtneobf162ps xmm6,XMMWORD PTR \[ecx\] > +\s*[a-f0-9]+:\s*c4 e2 7b b0 b1 f0 07 00 00\s+vcvtneobf162ps xmm6,XMMWORD= PTR \[ecx\+0x7f0\] > +\s*[a-f0-9]+:\s*c4 e2 7b b0 b2 00 f8 ff ff\s+vcvtneobf162ps xmm6,XMMWORD= PTR \[edx-0x800\] > +\s*[a-f0-9]+:\s*c4 e2 7f b0 b4 f4 00 00 00 10\s+vcvtneobf162ps ymm6,YMMW= ORD PTR \[esp\+esi\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 e2 7f b0 31\s+vcvtneobf162ps ymm6,YMMWORD PTR \[ecx\] > +\s*[a-f0-9]+:\s*c4 e2 7f b0 b1 e0 0f 00 00\s+vcvtneobf162ps ymm6,YMMWORD= PTR \[ecx\+0xfe0\] > +\s*[a-f0-9]+:\s*c4 e2 7f b0 b2 00 f0 ff ff\s+vcvtneobf162ps ymm6,YMMWORD= PTR \[edx-0x1000\] > +\s*[a-f0-9]+:\s*c4 e2 78 b0 b4 f4 00 00 00 10\s+vcvtneoph2ps xmm6,XMMWOR= D PTR \[esp\+esi\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 e2 78 b0 31\s+vcvtneoph2ps xmm6,XMMWORD PTR \[ecx\] > +\s*[a-f0-9]+:\s*c4 e2 78 b0 b1 f0 07 00 00\s+vcvtneoph2ps xmm6,XMMWORD P= TR \[ecx\+0x7f0\] > +\s*[a-f0-9]+:\s*c4 e2 78 b0 b2 00 f8 ff ff\s+vcvtneoph2ps xmm6,XMMWORD P= TR \[edx-0x800\] > +\s*[a-f0-9]+:\s*c4 e2 7c b0 b4 f4 00 00 00 10\s+vcvtneoph2ps ymm6,YMMWOR= D PTR \[esp\+esi\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 e2 7c b0 31\s+vcvtneoph2ps ymm6,YMMWORD PTR \[ecx\] > +\s*[a-f0-9]+:\s*c4 e2 7c b0 b1 e0 0f 00 00\s+vcvtneoph2ps ymm6,YMMWORD P= TR \[ecx\+0xfe0\] > +\s*[a-f0-9]+:\s*c4 e2 7c b0 b2 00 f0 ff ff\s+vcvtneoph2ps ymm6,YMMWORD P= TR \[edx-0x1000\] > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 f5\s+vcvtneps2bf16 xmm6,xmm5 > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 f5\s+vcvtneps2bf16 xmm6,xmm5 > +\s*[a-f0-9]+:\s*c4 e2 7a 72 f5\s+\{vex\} vcvtneps2bf16 xmm6,xmm5 > +\s*[a-f0-9]+:\s*c4 e2 7a 72 f5\s+\{vex\} vcvtneps2bf16 xmm6,xmm5 > +\s*[a-f0-9]+:\s*62 f2 7e 28 72 f5\s+vcvtneps2bf16 xmm6,ymm5 > +\s*[a-f0-9]+:\s*62 f2 7e 28 72 f5\s+vcvtneps2bf16 xmm6,ymm5 > +\s*[a-f0-9]+:\s*c4 e2 7e 72 f5\s+\{vex\} vcvtneps2bf16 xmm6,ymm5 > +\s*[a-f0-9]+:\s*c4 e2 7e 72 f5\s+\{vex\} vcvtneps2bf16 xmm6,ymm5 > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 b4 f4 00 00 00 10\s+vcvtneps2bf16 xmm6,XM= MWORD PTR \[esp\+esi\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 b4 f4 00 00 00 10\s+vcvtneps2bf16 xmm6,XM= MWORD PTR \[esp\+esi\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 e2 7a 72 b4 f4 00 00 00 10\s+\{vex\} vcvtneps2bf16 xm= m6,XMMWORD PTR \[esp\+esi\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 e2 7a 72 b4 f4 00 00 00 10\s+\{vex\} vcvtneps2bf16 xm= m6,XMMWORD PTR \[esp\+esi\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 31\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[ecx= \] > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 31\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[ecx= \] > +\s*[a-f0-9]+:\s*c4 e2 7a 72 31\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR = \[ecx\] > +\s*[a-f0-9]+:\s*c4 e2 7a 72 31\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR = \[ecx\] > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 71 7f\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[= ecx\+0x7f0\] > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 71 7f\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[= ecx\+0x7f0\] > +\s*[a-f0-9]+:\s*c4 e2 7a 72 b1 f0 07 00 00\s+\{vex\} vcvtneps2bf16 xmm6,= XMMWORD PTR \[ecx\+0x7f0\] > +\s*[a-f0-9]+:\s*c4 e2 7a 72 b1 f0 07 00 00\s+\{vex\} vcvtneps2bf16 xmm6,= XMMWORD PTR \[ecx\+0x7f0\] > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 72 80\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[= edx-0x800\] > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 72 80\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[= edx-0x800\] > +\s*[a-f0-9]+:\s*c4 e2 7a 72 b2 00 f8 ff ff\s+\{vex\} vcvtneps2bf16 xmm6,= XMMWORD PTR \[edx-0x800\] > +\s*[a-f0-9]+:\s*c4 e2 7a 72 b2 00 f8 ff ff\s+\{vex\} vcvtneps2bf16 xmm6,= XMMWORD PTR \[edx-0x800\] > +\s*[a-f0-9]+:\s*62 f2 7e 28 72 71 7f\s+vcvtneps2bf16 xmm6,YMMWORD PTR \[= ecx\+0xfe0\] > +\s*[a-f0-9]+:\s*62 f2 7e 28 72 71 7f\s+vcvtneps2bf16 xmm6,YMMWORD PTR \[= ecx\+0xfe0\] > +\s*[a-f0-9]+:\s*c4 e2 7e 72 b1 e0 0f 00 00\s+\{vex\} vcvtneps2bf16 xmm6,= YMMWORD PTR \[ecx\+0xfe0\] > +\s*[a-f0-9]+:\s*c4 e2 7e 72 b1 e0 0f 00 00\s+\{vex\} vcvtneps2bf16 xmm6,= YMMWORD PTR \[ecx\+0xfe0\] > +\s*[a-f0-9]+:\s*62 f2 7e 28 72 72 80\s+vcvtneps2bf16 xmm6,YMMWORD PTR \[= edx-0x1000\] > +\s*[a-f0-9]+:\s*62 f2 7e 28 72 72 80\s+vcvtneps2bf16 xmm6,YMMWORD PTR \[= edx-0x1000\] > +\s*[a-f0-9]+:\s*c4 e2 7e 72 b2 00 f0 ff ff\s+\{vex\} vcvtneps2bf16 xmm6,= YMMWORD PTR \[edx-0x1000\] > +\s*[a-f0-9]+:\s*c4 e2 7e 72 b2 00 f0 ff ff\s+\{vex\} vcvtneps2bf16 xmm6,= YMMWORD PTR \[edx-0x1000\] > +\s*[a-f0-9]+:\s*c4 e2 7a b1 b4 f4 00 00 00 10\s+vbcstnebf162ps xmm6,WORD= PTR \[esp\+esi\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 e2 7a b1 31\s+vbcstnebf162ps xmm6,WORD PTR \[ecx\] > +\s*[a-f0-9]+:\s*c4 e2 7a b1 b1 fe 00 00 00\s+vbcstnebf162ps xmm6,WORD PT= R \[ecx\+0xfe\] > +\s*[a-f0-9]+:\s*c4 e2 7a b1 b2 00 ff ff ff\s+vbcstnebf162ps xmm6,WORD PT= R \[edx-0x100\] > +\s*[a-f0-9]+:\s*c4 e2 7e b1 b4 f4 00 00 00 10\s+vbcstnebf162ps ymm6,WORD= PTR \[esp\+esi\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 e2 7e b1 31\s+vbcstnebf162ps ymm6,WORD PTR \[ecx\] > +\s*[a-f0-9]+:\s*c4 e2 7e b1 b1 fe 00 00 00\s+vbcstnebf162ps ymm6,WORD PT= R \[ecx\+0xfe\] > +\s*[a-f0-9]+:\s*c4 e2 7e b1 b2 00 ff ff ff\s+vbcstnebf162ps ymm6,WORD PT= R \[edx-0x100\] > +\s*[a-f0-9]+:\s*c4 e2 79 b1 b4 f4 00 00 00 10\s+vbcstnesh2ps xmm6,WORD P= TR \[esp\+esi\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 e2 79 b1 31\s+vbcstnesh2ps xmm6,WORD PTR \[ecx\] > +\s*[a-f0-9]+:\s*c4 e2 79 b1 b1 fe 00 00 00\s+vbcstnesh2ps xmm6,WORD PTR = \[ecx\+0xfe\] > +\s*[a-f0-9]+:\s*c4 e2 79 b1 b2 00 ff ff ff\s+vbcstnesh2ps xmm6,WORD PTR = \[edx-0x100\] > +\s*[a-f0-9]+:\s*c4 e2 7d b1 b4 f4 00 00 00 10\s+vbcstnesh2ps ymm6,WORD P= TR \[esp\+esi\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 e2 7d b1 31\s+vbcstnesh2ps ymm6,WORD PTR \[ecx\] > +\s*[a-f0-9]+:\s*c4 e2 7d b1 b1 fe 00 00 00\s+vbcstnesh2ps ymm6,WORD PTR = \[ecx\+0xfe\] > +\s*[a-f0-9]+:\s*c4 e2 7d b1 b2 00 ff ff ff\s+vbcstnesh2ps ymm6,WORD PTR = \[edx-0x100\] > +\s*[a-f0-9]+:\s*c4 e2 7a b0 b4 f4 00 00 00 10\s+vcvtneebf162ps xmm6,XMMW= ORD PTR \[esp\+esi\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 e2 7a b0 31\s+vcvtneebf162ps xmm6,XMMWORD PTR \[ecx\] > +\s*[a-f0-9]+:\s*c4 e2 7a b0 b1 f0 07 00 00\s+vcvtneebf162ps xmm6,XMMWORD= PTR \[ecx\+0x7f0\] > +\s*[a-f0-9]+:\s*c4 e2 7a b0 b2 00 f8 ff ff\s+vcvtneebf162ps xmm6,XMMWORD= PTR \[edx-0x800\] > +\s*[a-f0-9]+:\s*c4 e2 7e b0 b4 f4 00 00 00 10\s+vcvtneebf162ps ymm6,YMMW= ORD PTR \[esp\+esi\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 e2 7e b0 31\s+vcvtneebf162ps ymm6,YMMWORD PTR \[ecx\] > +\s*[a-f0-9]+:\s*c4 e2 7e b0 b1 e0 0f 00 00\s+vcvtneebf162ps ymm6,YMMWORD= PTR \[ecx\+0xfe0\] > +\s*[a-f0-9]+:\s*c4 e2 7e b0 b2 00 f0 ff ff\s+vcvtneebf162ps ymm6,YMMWORD= PTR \[edx-0x1000\] > +\s*[a-f0-9]+:\s*c4 e2 79 b0 b4 f4 00 00 00 10\s+vcvtneeph2ps xmm6,XMMWOR= D PTR \[esp\+esi\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 e2 79 b0 31\s+vcvtneeph2ps xmm6,XMMWORD PTR \[ecx\] > +\s*[a-f0-9]+:\s*c4 e2 79 b0 b1 f0 07 00 00\s+vcvtneeph2ps xmm6,XMMWORD P= TR \[ecx\+0x7f0\] > +\s*[a-f0-9]+:\s*c4 e2 79 b0 b2 00 f8 ff ff\s+vcvtneeph2ps xmm6,XMMWORD P= TR \[edx-0x800\] > +\s*[a-f0-9]+:\s*c4 e2 7d b0 b4 f4 00 00 00 10\s+vcvtneeph2ps ymm6,YMMWOR= D PTR \[esp\+esi\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 e2 7d b0 31\s+vcvtneeph2ps ymm6,YMMWORD PTR \[ecx\] > +\s*[a-f0-9]+:\s*c4 e2 7d b0 b1 e0 0f 00 00\s+vcvtneeph2ps ymm6,YMMWORD P= TR \[ecx\+0xfe0\] > +\s*[a-f0-9]+:\s*c4 e2 7d b0 b2 00 f0 ff ff\s+vcvtneeph2ps ymm6,YMMWORD P= TR \[edx-0x1000\] > +\s*[a-f0-9]+:\s*c4 e2 7b b0 b4 f4 00 00 00 10\s+vcvtneobf162ps xmm6,XMMW= ORD PTR \[esp\+esi\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 e2 7b b0 31\s+vcvtneobf162ps xmm6,XMMWORD PTR \[ecx\] > +\s*[a-f0-9]+:\s*c4 e2 7b b0 b1 f0 07 00 00\s+vcvtneobf162ps xmm6,XMMWORD= PTR \[ecx\+0x7f0\] > +\s*[a-f0-9]+:\s*c4 e2 7b b0 b2 00 f8 ff ff\s+vcvtneobf162ps xmm6,XMMWORD= PTR \[edx-0x800\] > +\s*[a-f0-9]+:\s*c4 e2 7f b0 b4 f4 00 00 00 10\s+vcvtneobf162ps ymm6,YMMW= ORD PTR \[esp\+esi\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 e2 7f b0 31\s+vcvtneobf162ps ymm6,YMMWORD PTR \[ecx\] > +\s*[a-f0-9]+:\s*c4 e2 7f b0 b1 e0 0f 00 00\s+vcvtneobf162ps ymm6,YMMWORD= PTR \[ecx\+0xfe0\] > +\s*[a-f0-9]+:\s*c4 e2 7f b0 b2 00 f0 ff ff\s+vcvtneobf162ps ymm6,YMMWORD= PTR \[edx-0x1000\] > +\s*[a-f0-9]+:\s*c4 e2 78 b0 b4 f4 00 00 00 10\s+vcvtneoph2ps xmm6,XMMWOR= D PTR \[esp\+esi\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 e2 78 b0 31\s+vcvtneoph2ps xmm6,XMMWORD PTR \[ecx\] > +\s*[a-f0-9]+:\s*c4 e2 78 b0 b1 f0 07 00 00\s+vcvtneoph2ps xmm6,XMMWORD P= TR \[ecx\+0x7f0\] > +\s*[a-f0-9]+:\s*c4 e2 78 b0 b2 00 f8 ff ff\s+vcvtneoph2ps xmm6,XMMWORD P= TR \[edx-0x800\] > +\s*[a-f0-9]+:\s*c4 e2 7c b0 b4 f4 00 00 00 10\s+vcvtneoph2ps ymm6,YMMWOR= D PTR \[esp\+esi\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 e2 7c b0 31\s+vcvtneoph2ps ymm6,YMMWORD PTR \[ecx\] > +\s*[a-f0-9]+:\s*c4 e2 7c b0 b1 e0 0f 00 00\s+vcvtneoph2ps ymm6,YMMWORD P= TR \[ecx\+0xfe0\] > +\s*[a-f0-9]+:\s*c4 e2 7c b0 b2 00 f0 ff ff\s+vcvtneoph2ps ymm6,YMMWORD P= TR \[edx-0x1000\] > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 f5\s+vcvtneps2bf16 xmm6,xmm5 > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 f5\s+vcvtneps2bf16 xmm6,xmm5 > +\s*[a-f0-9]+:\s*c4 e2 7a 72 f5\s+\{vex\} vcvtneps2bf16 xmm6,xmm5 > +\s*[a-f0-9]+:\s*c4 e2 7a 72 f5\s+\{vex\} vcvtneps2bf16 xmm6,xmm5 > +\s*[a-f0-9]+:\s*62 f2 7e 28 72 f5\s+vcvtneps2bf16 xmm6,ymm5 > +\s*[a-f0-9]+:\s*62 f2 7e 28 72 f5\s+vcvtneps2bf16 xmm6,ymm5 > +\s*[a-f0-9]+:\s*c4 e2 7e 72 f5\s+\{vex\} vcvtneps2bf16 xmm6,ymm5 > +\s*[a-f0-9]+:\s*c4 e2 7e 72 f5\s+\{vex\} vcvtneps2bf16 xmm6,ymm5 > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 b4 f4 00 00 00 10\s+vcvtneps2bf16 xmm6,XM= MWORD PTR \[esp\+esi\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 b4 f4 00 00 00 10\s+vcvtneps2bf16 xmm6,XM= MWORD PTR \[esp\+esi\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 e2 7a 72 b4 f4 00 00 00 10\s+\{vex\} vcvtneps2bf16 xm= m6,XMMWORD PTR \[esp\+esi\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 e2 7a 72 b4 f4 00 00 00 10\s+\{vex\} vcvtneps2bf16 xm= m6,XMMWORD PTR \[esp\+esi\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 31\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[ecx= \] > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 31\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[ecx= \] > +\s*[a-f0-9]+:\s*c4 e2 7a 72 31\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR = \[ecx\] > +\s*[a-f0-9]+:\s*c4 e2 7a 72 31\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR = \[ecx\] > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 71 7f\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[= ecx\+0x7f0\] > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 71 7f\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[= ecx\+0x7f0\] > +\s*[a-f0-9]+:\s*c4 e2 7a 72 b1 f0 07 00 00\s+\{vex\} vcvtneps2bf16 xmm6,= XMMWORD PTR \[ecx\+0x7f0\] > +\s*[a-f0-9]+:\s*c4 e2 7a 72 b1 f0 07 00 00\s+\{vex\} vcvtneps2bf16 xmm6,= XMMWORD PTR \[ecx\+0x7f0\] > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 72 80\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[= edx-0x800\] > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 72 80\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[= edx-0x800\] > +\s*[a-f0-9]+:\s*c4 e2 7a 72 b2 00 f8 ff ff\s+\{vex\} vcvtneps2bf16 xmm6,= XMMWORD PTR \[edx-0x800\] > +\s*[a-f0-9]+:\s*c4 e2 7a 72 b2 00 f8 ff ff\s+\{vex\} vcvtneps2bf16 xmm6,= XMMWORD PTR \[edx-0x800\] > +\s*[a-f0-9]+:\s*62 f2 7e 28 72 71 7f\s+vcvtneps2bf16 xmm6,YMMWORD PTR \[= ecx\+0xfe0\] > +\s*[a-f0-9]+:\s*62 f2 7e 28 72 71 7f\s+vcvtneps2bf16 xmm6,YMMWORD PTR \[= ecx\+0xfe0\] > +\s*[a-f0-9]+:\s*c4 e2 7e 72 b1 e0 0f 00 00\s+\{vex\} vcvtneps2bf16 xmm6,= YMMWORD PTR \[ecx\+0xfe0\] > +\s*[a-f0-9]+:\s*c4 e2 7e 72 b1 e0 0f 00 00\s+\{vex\} vcvtneps2bf16 xmm6,= YMMWORD PTR \[ecx\+0xfe0\] > +\s*[a-f0-9]+:\s*62 f2 7e 28 72 72 80\s+vcvtneps2bf16 xmm6,YMMWORD PTR \[= edx-0x1000\] > +\s*[a-f0-9]+:\s*62 f2 7e 28 72 72 80\s+vcvtneps2bf16 xmm6,YMMWORD PTR \[= edx-0x1000\] > +\s*[a-f0-9]+:\s*c4 e2 7e 72 b2 00 f0 ff ff\s+\{vex\} vcvtneps2bf16 xmm6,= YMMWORD PTR \[edx-0x1000\] > +\s*[a-f0-9]+:\s*c4 e2 7e 72 b2 00 f0 ff ff\s+\{vex\} vcvtneps2bf16 xmm6,= YMMWORD PTR \[edx-0x1000\] > diff --git a/gas/testsuite/gas/i386/avx-ne-convert.d b/gas/testsuite/gas/= i386/avx-ne-convert.d > new file mode 100644 > index 0000000000..24f6ae09fe > --- /dev/null > +++ b/gas/testsuite/gas/i386/avx-ne-convert.d > @@ -0,0 +1,170 @@ > +#as: > +#objdump: -dw > +#name: i386 AVX-NE-CONVERT insns > +#source: avx-ne-convert.s > + > +.*: +file format .* > + > +Disassembly of section \.text: > + > +0+ <_start>: > +\s*[a-f0-9]+:\s*c4 e2 7a b1 b4 f4 00 00 00 10\s+vbcstnebf162ps 0x1000000= 0\(%esp,%esi,8\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7a b1 31\s+vbcstnebf162ps \(%ecx\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7a b1 b1 fe 00 00 00\s+vbcstnebf162ps 0xfe\(%ecx\)= ,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7a b1 b2 00 ff ff ff\s+vbcstnebf162ps -0x100\(%edx= \),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7e b1 b4 f4 00 00 00 10\s+vbcstnebf162ps 0x1000000= 0\(%esp,%esi,8\),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7e b1 31\s+vbcstnebf162ps \(%ecx\),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7e b1 b1 fe 00 00 00\s+vbcstnebf162ps 0xfe\(%ecx\)= ,%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7e b1 b2 00 ff ff ff\s+vbcstnebf162ps -0x100\(%edx= \),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 79 b1 b4 f4 00 00 00 10\s+vbcstnesh2ps 0x10000000\= (%esp,%esi,8\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 79 b1 31\s+vbcstnesh2ps \(%ecx\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 79 b1 b1 fe 00 00 00\s+vbcstnesh2ps 0xfe\(%ecx\),%= xmm6 > +\s*[a-f0-9]+:\s*c4 e2 79 b1 b2 00 ff ff ff\s+vbcstnesh2ps -0x100\(%edx\)= ,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7d b1 b4 f4 00 00 00 10\s+vbcstnesh2ps 0x10000000\= (%esp,%esi,8\),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7d b1 31\s+vbcstnesh2ps \(%ecx\),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7d b1 b1 fe 00 00 00\s+vbcstnesh2ps 0xfe\(%ecx\),%= ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7d b1 b2 00 ff ff ff\s+vbcstnesh2ps -0x100\(%edx\)= ,%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7a b0 b4 f4 00 00 00 10\s+vcvtneebf162ps 0x1000000= 0\(%esp,%esi,8\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7a b0 31\s+vcvtneebf162ps \(%ecx\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7a b0 b1 f0 07 00 00\s+vcvtneebf162ps 0x7f0\(%ecx\= ),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7a b0 b2 00 f8 ff ff\s+vcvtneebf162ps -0x800\(%edx= \),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7e b0 b4 f4 00 00 00 10\s+vcvtneebf162ps 0x1000000= 0\(%esp,%esi,8\),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7e b0 31\s+vcvtneebf162ps \(%ecx\),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7e b0 b1 e0 0f 00 00\s+vcvtneebf162ps 0xfe0\(%ecx\= ),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7e b0 b2 00 f0 ff ff\s+vcvtneebf162ps -0x1000\(%ed= x\),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 79 b0 b4 f4 00 00 00 10\s+vcvtneeph2ps 0x10000000\= (%esp,%esi,8\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 79 b0 31\s+vcvtneeph2ps \(%ecx\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 79 b0 b1 f0 07 00 00\s+vcvtneeph2ps 0x7f0\(%ecx\),= %xmm6 > +\s*[a-f0-9]+:\s*c4 e2 79 b0 b2 00 f8 ff ff\s+vcvtneeph2ps -0x800\(%edx\)= ,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7d b0 b4 f4 00 00 00 10\s+vcvtneeph2ps 0x10000000\= (%esp,%esi,8\),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7d b0 31\s+vcvtneeph2ps \(%ecx\),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7d b0 b1 e0 0f 00 00\s+vcvtneeph2ps 0xfe0\(%ecx\),= %ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7d b0 b2 00 f0 ff ff\s+vcvtneeph2ps -0x1000\(%edx\= ),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7b b0 b4 f4 00 00 00 10\s+vcvtneobf162ps 0x1000000= 0\(%esp,%esi,8\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7b b0 31\s+vcvtneobf162ps \(%ecx\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7b b0 b1 f0 07 00 00\s+vcvtneobf162ps 0x7f0\(%ecx\= ),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7b b0 b2 00 f8 ff ff\s+vcvtneobf162ps -0x800\(%edx= \),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7f b0 b4 f4 00 00 00 10\s+vcvtneobf162ps 0x1000000= 0\(%esp,%esi,8\),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7f b0 31\s+vcvtneobf162ps \(%ecx\),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7f b0 b1 e0 0f 00 00\s+vcvtneobf162ps 0xfe0\(%ecx\= ),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7f b0 b2 00 f0 ff ff\s+vcvtneobf162ps -0x1000\(%ed= x\),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 78 b0 b4 f4 00 00 00 10\s+vcvtneoph2ps 0x10000000\= (%esp,%esi,8\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 78 b0 31\s+vcvtneoph2ps \(%ecx\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 78 b0 b1 f0 07 00 00\s+vcvtneoph2ps 0x7f0\(%ecx\),= %xmm6 > +\s*[a-f0-9]+:\s*c4 e2 78 b0 b2 00 f8 ff ff\s+vcvtneoph2ps -0x800\(%edx\)= ,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7c b0 b4 f4 00 00 00 10\s+vcvtneoph2ps 0x10000000\= (%esp,%esi,8\),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7c b0 31\s+vcvtneoph2ps \(%ecx\),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7c b0 b1 e0 0f 00 00\s+vcvtneoph2ps 0xfe0\(%ecx\),= %ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7c b0 b2 00 f0 ff ff\s+vcvtneoph2ps -0x1000\(%edx\= ),%ymm6 > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 f5\s+vcvtneps2bf16 %xmm5,%xmm6 > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 f5\s+vcvtneps2bf16 %xmm5,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7a 72 f5\s+\{vex\} vcvtneps2bf16 %xmm5,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7a 72 f5\s+\{vex\} vcvtneps2bf16 %xmm5,%xmm6 > +\s*[a-f0-9]+:\s*62 f2 7e 28 72 f5\s+vcvtneps2bf16 %ymm5,%xmm6 > +\s*[a-f0-9]+:\s*62 f2 7e 28 72 f5\s+vcvtneps2bf16 %ymm5,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7e 72 f5\s+\{vex\} vcvtneps2bf16 %ymm5,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7e 72 f5\s+\{vex\} vcvtneps2bf16 %ymm5,%xmm6 > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 b4 f4 00 00 00 10\s+vcvtneps2bf16x 0x1000= 0000\(%esp,%esi,8\),%xmm6 > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 b4 f4 00 00 00 10\s+vcvtneps2bf16x 0x1000= 0000\(%esp,%esi,8\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7a 72 b4 f4 00 00 00 10\s+\{vex\} vcvtneps2bf16x 0= x10000000\(%esp,%esi,8\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7a 72 b4 f4 00 00 00 10\s+\{vex\} vcvtneps2bf16x 0= x10000000\(%esp,%esi,8\),%xmm6 > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 31\s+vcvtneps2bf16x \(%ecx\),%xmm6 > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 31\s+vcvtneps2bf16x \(%ecx\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7a 72 31\s+\{vex\} vcvtneps2bf16x \(%ecx\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7a 72 31\s+\{vex\} vcvtneps2bf16x \(%ecx\),%xmm6 > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 71 7f\s+vcvtneps2bf16x 0x7f0\(%ecx\),%xmm= 6 > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 71 7f\s+vcvtneps2bf16x 0x7f0\(%ecx\),%xmm= 6 > +\s*[a-f0-9]+:\s*c4 e2 7a 72 b1 f0 07 00 00\s+\{vex\} vcvtneps2bf16x 0x7f= 0\(%ecx\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7a 72 b1 f0 07 00 00\s+\{vex\} vcvtneps2bf16x 0x7f= 0\(%ecx\),%xmm6 > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 72 80\s+vcvtneps2bf16x -0x800\(%edx\),%xm= m6 > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 72 80\s+vcvtneps2bf16x -0x800\(%edx\),%xm= m6 > +\s*[a-f0-9]+:\s*c4 e2 7a 72 b2 00 f8 ff ff\s+\{vex\} vcvtneps2bf16x -0x8= 00\(%edx\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7a 72 b2 00 f8 ff ff\s+\{vex\} vcvtneps2bf16x -0x8= 00\(%edx\),%xmm6 > +\s*[a-f0-9]+:\s*62 f2 7e 28 72 71 7f\s+vcvtneps2bf16y 0xfe0\(%ecx\),%xmm= 6 > +\s*[a-f0-9]+:\s*62 f2 7e 28 72 71 7f\s+vcvtneps2bf16y 0xfe0\(%ecx\),%xmm= 6 > +\s*[a-f0-9]+:\s*c4 e2 7e 72 b1 e0 0f 00 00\s+\{vex\} vcvtneps2bf16y 0xfe= 0\(%ecx\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7e 72 b1 e0 0f 00 00\s+\{vex\} vcvtneps2bf16y 0xfe= 0\(%ecx\),%xmm6 > +\s*[a-f0-9]+:\s*62 f2 7e 28 72 72 80\s+vcvtneps2bf16y -0x1000\(%edx\),%x= mm6 > +\s*[a-f0-9]+:\s*62 f2 7e 28 72 72 80\s+vcvtneps2bf16y -0x1000\(%edx\),%x= mm6 > +\s*[a-f0-9]+:\s*c4 e2 7e 72 b2 00 f0 ff ff\s+\{vex\} vcvtneps2bf16y -0x1= 000\(%edx\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7e 72 b2 00 f0 ff ff\s+\{vex\} vcvtneps2bf16y -0x1= 000\(%edx\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7a b1 b4 f4 00 00 00 10\s+vbcstnebf162ps 0x1000000= 0\(%esp,%esi,8\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7a b1 31\s+vbcstnebf162ps \(%ecx\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7a b1 b1 fe 00 00 00\s+vbcstnebf162ps 0xfe\(%ecx\)= ,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7a b1 b2 00 ff ff ff\s+vbcstnebf162ps -0x100\(%edx= \),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7e b1 b4 f4 00 00 00 10\s+vbcstnebf162ps 0x1000000= 0\(%esp,%esi,8\),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7e b1 31\s+vbcstnebf162ps \(%ecx\),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7e b1 b1 fe 00 00 00\s+vbcstnebf162ps 0xfe\(%ecx\)= ,%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7e b1 b2 00 ff ff ff\s+vbcstnebf162ps -0x100\(%edx= \),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 79 b1 b4 f4 00 00 00 10\s+vbcstnesh2ps 0x10000000\= (%esp,%esi,8\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 79 b1 31\s+vbcstnesh2ps \(%ecx\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 79 b1 b1 fe 00 00 00\s+vbcstnesh2ps 0xfe\(%ecx\),%= xmm6 > +\s*[a-f0-9]+:\s*c4 e2 79 b1 b2 00 ff ff ff\s+vbcstnesh2ps -0x100\(%edx\)= ,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7d b1 b4 f4 00 00 00 10\s+vbcstnesh2ps 0x10000000\= (%esp,%esi,8\),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7d b1 31\s+vbcstnesh2ps \(%ecx\),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7d b1 b1 fe 00 00 00\s+vbcstnesh2ps 0xfe\(%ecx\),%= ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7d b1 b2 00 ff ff ff\s+vbcstnesh2ps -0x100\(%edx\)= ,%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7a b0 b4 f4 00 00 00 10\s+vcvtneebf162ps 0x1000000= 0\(%esp,%esi,8\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7a b0 31\s+vcvtneebf162ps \(%ecx\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7a b0 b1 f0 07 00 00\s+vcvtneebf162ps 0x7f0\(%ecx\= ),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7a b0 b2 00 f8 ff ff\s+vcvtneebf162ps -0x800\(%edx= \),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7e b0 b4 f4 00 00 00 10\s+vcvtneebf162ps 0x1000000= 0\(%esp,%esi,8\),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7e b0 31\s+vcvtneebf162ps \(%ecx\),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7e b0 b1 e0 0f 00 00\s+vcvtneebf162ps 0xfe0\(%ecx\= ),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7e b0 b2 00 f0 ff ff\s+vcvtneebf162ps -0x1000\(%ed= x\),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 79 b0 b4 f4 00 00 00 10\s+vcvtneeph2ps 0x10000000\= (%esp,%esi,8\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 79 b0 31\s+vcvtneeph2ps \(%ecx\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 79 b0 b1 f0 07 00 00\s+vcvtneeph2ps 0x7f0\(%ecx\),= %xmm6 > +\s*[a-f0-9]+:\s*c4 e2 79 b0 b2 00 f8 ff ff\s+vcvtneeph2ps -0x800\(%edx\)= ,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7d b0 b4 f4 00 00 00 10\s+vcvtneeph2ps 0x10000000\= (%esp,%esi,8\),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7d b0 31\s+vcvtneeph2ps \(%ecx\),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7d b0 b1 e0 0f 00 00\s+vcvtneeph2ps 0xfe0\(%ecx\),= %ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7d b0 b2 00 f0 ff ff\s+vcvtneeph2ps -0x1000\(%edx\= ),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7b b0 b4 f4 00 00 00 10\s+vcvtneobf162ps 0x1000000= 0\(%esp,%esi,8\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7b b0 31\s+vcvtneobf162ps \(%ecx\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7b b0 b1 f0 07 00 00\s+vcvtneobf162ps 0x7f0\(%ecx\= ),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7b b0 b2 00 f8 ff ff\s+vcvtneobf162ps -0x800\(%edx= \),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7f b0 b4 f4 00 00 00 10\s+vcvtneobf162ps 0x1000000= 0\(%esp,%esi,8\),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7f b0 31\s+vcvtneobf162ps \(%ecx\),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7f b0 b1 e0 0f 00 00\s+vcvtneobf162ps 0xfe0\(%ecx\= ),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7f b0 b2 00 f0 ff ff\s+vcvtneobf162ps -0x1000\(%ed= x\),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 78 b0 b4 f4 00 00 00 10\s+vcvtneoph2ps 0x10000000\= (%esp,%esi,8\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 78 b0 31\s+vcvtneoph2ps \(%ecx\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 78 b0 b1 f0 07 00 00\s+vcvtneoph2ps 0x7f0\(%ecx\),= %xmm6 > +\s*[a-f0-9]+:\s*c4 e2 78 b0 b2 00 f8 ff ff\s+vcvtneoph2ps -0x800\(%edx\)= ,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7c b0 b4 f4 00 00 00 10\s+vcvtneoph2ps 0x10000000\= (%esp,%esi,8\),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7c b0 31\s+vcvtneoph2ps \(%ecx\),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7c b0 b1 e0 0f 00 00\s+vcvtneoph2ps 0xfe0\(%ecx\),= %ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7c b0 b2 00 f0 ff ff\s+vcvtneoph2ps -0x1000\(%edx\= ),%ymm6 > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 f5\s+vcvtneps2bf16 %xmm5,%xmm6 > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 f5\s+vcvtneps2bf16 %xmm5,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7a 72 f5\s+\{vex\} vcvtneps2bf16 %xmm5,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7a 72 f5\s+\{vex\} vcvtneps2bf16 %xmm5,%xmm6 > +\s*[a-f0-9]+:\s*62 f2 7e 28 72 f5\s+vcvtneps2bf16 %ymm5,%xmm6 > +\s*[a-f0-9]+:\s*62 f2 7e 28 72 f5\s+vcvtneps2bf16 %ymm5,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7e 72 f5\s+\{vex\} vcvtneps2bf16 %ymm5,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7e 72 f5\s+\{vex\} vcvtneps2bf16 %ymm5,%xmm6 > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 b4 f4 00 00 00 10\s+vcvtneps2bf16x 0x1000= 0000\(%esp,%esi,8\),%xmm6 > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 b4 f4 00 00 00 10\s+vcvtneps2bf16x 0x1000= 0000\(%esp,%esi,8\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7a 72 b4 f4 00 00 00 10\s+\{vex\} vcvtneps2bf16x 0= x10000000\(%esp,%esi,8\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7a 72 b4 f4 00 00 00 10\s+\{vex\} vcvtneps2bf16x 0= x10000000\(%esp,%esi,8\),%xmm6 > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 31\s+vcvtneps2bf16x \(%ecx\),%xmm6 > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 31\s+vcvtneps2bf16x \(%ecx\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7a 72 31\s+\{vex\} vcvtneps2bf16x \(%ecx\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7a 72 31\s+\{vex\} vcvtneps2bf16x \(%ecx\),%xmm6 > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 71 7f\s+vcvtneps2bf16x 0x7f0\(%ecx\),%xmm= 6 > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 71 7f\s+vcvtneps2bf16x 0x7f0\(%ecx\),%xmm= 6 > +\s*[a-f0-9]+:\s*c4 e2 7a 72 b1 f0 07 00 00\s+\{vex\} vcvtneps2bf16x 0x7f= 0\(%ecx\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7a 72 b1 f0 07 00 00\s+\{vex\} vcvtneps2bf16x 0x7f= 0\(%ecx\),%xmm6 > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 72 80\s+vcvtneps2bf16x -0x800\(%edx\),%xm= m6 > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 72 80\s+vcvtneps2bf16x -0x800\(%edx\),%xm= m6 > +\s*[a-f0-9]+:\s*c4 e2 7a 72 b2 00 f8 ff ff\s+\{vex\} vcvtneps2bf16x -0x8= 00\(%edx\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7a 72 b2 00 f8 ff ff\s+\{vex\} vcvtneps2bf16x -0x8= 00\(%edx\),%xmm6 > +\s*[a-f0-9]+:\s*62 f2 7e 28 72 71 7f\s+vcvtneps2bf16y 0xfe0\(%ecx\),%xmm= 6 > +\s*[a-f0-9]+:\s*62 f2 7e 28 72 71 7f\s+vcvtneps2bf16y 0xfe0\(%ecx\),%xmm= 6 > +\s*[a-f0-9]+:\s*c4 e2 7e 72 b1 e0 0f 00 00\s+\{vex\} vcvtneps2bf16y 0xfe= 0\(%ecx\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7e 72 b1 e0 0f 00 00\s+\{vex\} vcvtneps2bf16y 0xfe= 0\(%ecx\),%xmm6 > +\s*[a-f0-9]+:\s*62 f2 7e 28 72 72 80\s+vcvtneps2bf16y -0x1000\(%edx\),%x= mm6 > +\s*[a-f0-9]+:\s*62 f2 7e 28 72 72 80\s+vcvtneps2bf16y -0x1000\(%edx\),%x= mm6 > +\s*[a-f0-9]+:\s*c4 e2 7e 72 b2 00 f0 ff ff\s+\{vex\} vcvtneps2bf16y -0x1= 000\(%edx\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7e 72 b2 00 f0 ff ff\s+\{vex\} vcvtneps2bf16y -0x1= 000\(%edx\),%xmm6 > diff --git a/gas/testsuite/gas/i386/avx-ne-convert.s b/gas/testsuite/gas/= i386/avx-ne-convert.s > new file mode 100644 > index 0000000000..7fb866630d > --- /dev/null > +++ b/gas/testsuite/gas/i386/avx-ne-convert.s > @@ -0,0 +1,167 @@ > +# Check 32bit AVX-NE-CONVERT instructions > + > + .allow_index_reg > + .text > +_start: > + vbcstnebf162ps 0x10000000(%esp, %esi, 8), %xmm6 #AVX-NE-= CONVERT > + vbcstnebf162ps (%ecx), %xmm6 #AVX-NE-CONVERT > + vbcstnebf162ps 254(%ecx), %xmm6 #AVX-NE-CONVERT Disp32(f= e000000) > + vbcstnebf162ps -256(%edx), %xmm6 #AVX-NE-CONVERT Disp32(0= 0ffffff) > + vbcstnebf162ps 0x10000000(%esp, %esi, 8), %ymm6 #AVX-NE-= CONVERT > + vbcstnebf162ps (%ecx), %ymm6 #AVX-NE-CONVERT > + vbcstnebf162ps 254(%ecx), %ymm6 #AVX-NE-CONVERT Disp32(f= e000000) > + vbcstnebf162ps -256(%edx), %ymm6 #AVX-NE-CONVERT Disp32(0= 0ffffff) > + vbcstnesh2ps 0x10000000(%esp, %esi, 8), %xmm6 #AVX-NE-= CONVERT > + vbcstnesh2ps (%ecx), %xmm6 #AVX-NE-CONVERT > + vbcstnesh2ps 254(%ecx), %xmm6 #AVX-NE-CONVERT Disp32(f= e000000) > + vbcstnesh2ps -256(%edx), %xmm6 #AVX-NE-CONVERT Disp32(0= 0ffffff) > + vbcstnesh2ps 0x10000000(%esp, %esi, 8), %ymm6 #AVX-NE-= CONVERT > + vbcstnesh2ps (%ecx), %ymm6 #AVX-NE-CONVERT > + vbcstnesh2ps 254(%ecx), %ymm6 #AVX-NE-CONVERT Disp32(f= e000000) > + vbcstnesh2ps -256(%edx), %ymm6 #AVX-NE-CONVERT Disp32(0= 0ffffff) > + vcvtneebf162ps 0x10000000(%esp, %esi, 8), %xmm6 #AVX-NE-= CONVERT > + vcvtneebf162ps (%ecx), %xmm6 #AVX-NE-CONVERT > + vcvtneebf162ps 2032(%ecx), %xmm6 #AVX-NE-CONVERT Disp32(f= 0070000) > + vcvtneebf162ps -2048(%edx), %xmm6 #AVX-NE-CONVERT Disp32(0= 0f8ffff) > + vcvtneebf162ps 0x10000000(%esp, %esi, 8), %ymm6 #AVX-NE-= CONVERT > + vcvtneebf162ps (%ecx), %ymm6 #AVX-NE-CONVERT > + vcvtneebf162ps 4064(%ecx), %ymm6 #AVX-NE-CONVERT Disp32(e= 00f0000) > + vcvtneebf162ps -4096(%edx), %ymm6 #AVX-NE-CONVERT Disp32(0= 0f0ffff) > + vcvtneeph2ps 0x10000000(%esp, %esi, 8), %xmm6 #AVX-NE-= CONVERT > + vcvtneeph2ps (%ecx), %xmm6 #AVX-NE-CONVERT > + vcvtneeph2ps 2032(%ecx), %xmm6 #AVX-NE-CONVERT Disp32(f= 0070000) > + vcvtneeph2ps -2048(%edx), %xmm6 #AVX-NE-CONVERT Disp32(0= 0f8ffff) > + vcvtneeph2ps 0x10000000(%esp, %esi, 8), %ymm6 #AVX-NE-= CONVERT > + vcvtneeph2ps (%ecx), %ymm6 #AVX-NE-CONVERT > + vcvtneeph2ps 4064(%ecx), %ymm6 #AVX-NE-CONVERT Disp32(e= 00f0000) > + vcvtneeph2ps -4096(%edx), %ymm6 #AVX-NE-CONVERT Disp32(0= 0f0ffff) > + vcvtneobf162ps 0x10000000(%esp, %esi, 8), %xmm6 #AVX-NE-= CONVERT > + vcvtneobf162ps (%ecx), %xmm6 #AVX-NE-CONVERT > + vcvtneobf162ps 2032(%ecx), %xmm6 #AVX-NE-CONVERT Disp32(f= 0070000) > + vcvtneobf162ps -2048(%edx), %xmm6 #AVX-NE-CONVERT Disp32(0= 0f8ffff) > + vcvtneobf162ps 0x10000000(%esp, %esi, 8), %ymm6 #AVX-NE-= CONVERT > + vcvtneobf162ps (%ecx), %ymm6 #AVX-NE-CONVERT > + vcvtneobf162ps 4064(%ecx), %ymm6 #AVX-NE-CONVERT Disp32(e= 00f0000) > + vcvtneobf162ps -4096(%edx), %ymm6 #AVX-NE-CONVERT Disp32(0= 0f0ffff) > + vcvtneoph2ps 0x10000000(%esp, %esi, 8), %xmm6 #AVX-NE-= CONVERT > + vcvtneoph2ps (%ecx), %xmm6 #AVX-NE-CONVERT > + vcvtneoph2ps 2032(%ecx), %xmm6 #AVX-NE-CONVERT Disp32(f= 0070000) > + vcvtneoph2ps -2048(%edx), %xmm6 #AVX-NE-CONVERT Disp32(0= 0f8ffff) > + vcvtneoph2ps 0x10000000(%esp, %esi, 8), %ymm6 #AVX-NE-= CONVERT > + vcvtneoph2ps (%ecx), %ymm6 #AVX-NE-CONVERT > + vcvtneoph2ps 4064(%ecx), %ymm6 #AVX-NE-CONVERT Disp32(e= 00f0000) > + vcvtneoph2ps -4096(%edx), %ymm6 #AVX-NE-CONVERT Disp32(0= 0f0ffff) > + vcvtneps2bf16 %xmm5, %xmm6 #AVX-NE-CONVERT > + {evex} vcvtneps2bf16 %xmm5, %xmm6 #AVX-NE-CONVERT > + {vex} vcvtneps2bf16 %xmm5, %xmm6 #AVX-NE-CONVERT > + {vex3} vcvtneps2bf16 %xmm5, %xmm6 #AVX-NE-CONVERT > + vcvtneps2bf16 %ymm5, %xmm6 #AVX-NE-CONVERT > + {evex} vcvtneps2bf16 %ymm5, %xmm6 #AVX-NE-CONVERT > + {vex} vcvtneps2bf16 %ymm5, %xmm6 #AVX-NE-CONVERT > + {vex3} vcvtneps2bf16 %ymm5, %xmm6 #AVX-NE-CONVERT > + vcvtneps2bf16x 0x10000000(%esp, %esi, 8), %xmm6 #AVX-NE-= CONVERT > + {evex} vcvtneps2bf16x 0x10000000(%esp, %esi, 8), %xmm6 = #AVX-NE-CONVERT > + {vex} vcvtneps2bf16x 0x10000000(%esp, %esi, 8), %xmm6 = #AVX-NE-CONVERT > + {vex3} vcvtneps2bf16x 0x10000000(%esp, %esi, 8), %xmm6 = #AVX-NE-CONVERT > + vcvtneps2bf16x (%ecx), %xmm6 #AVX-NE-CONVERT > + {evex} vcvtneps2bf16x (%ecx), %xmm6 #AVX-NE-CONVERT > + {vex} vcvtneps2bf16x (%ecx), %xmm6 #AVX-NE-CONVERT > + {vex3} vcvtneps2bf16x (%ecx), %xmm6 #AVX-NE-CONVERT > + vcvtneps2bf16x 2032(%ecx), %xmm6 #AVX-NE-CONVERT Disp32(f= 0070000) > + {evex} vcvtneps2bf16x 2032(%ecx), %xmm6 #AVX-NE-CONVERT = Disp32(f0070000) > + {vex} vcvtneps2bf16x 2032(%ecx), %xmm6 #AVX-NE-CONVERT = Disp32(f0070000) > + {vex3} vcvtneps2bf16x 2032(%ecx), %xmm6 #AVX-NE-CONVERT = Disp32(f0070000) > + vcvtneps2bf16x -2048(%edx), %xmm6 #AVX-NE-CONVERT Disp32(0= 0f8ffff) > + {evex} vcvtneps2bf16x -2048(%edx), %xmm6 #AVX-NE-CONVERT = Disp32(00f8ffff) > + {vex} vcvtneps2bf16x -2048(%edx), %xmm6 #AVX-NE-CONVERT = Disp32(00f8ffff) > + {vex3} vcvtneps2bf16x -2048(%edx), %xmm6 #AVX-NE-CONVERT = Disp32(00f8ffff) > + vcvtneps2bf16y 4064(%ecx), %xmm6 #AVX-NE-CONVERT Disp32(e= 00f0000) > + {evex} vcvtneps2bf16y 4064(%ecx), %xmm6 #AVX-NE-CONVERT = Disp32(e00f0000) > + {vex} vcvtneps2bf16y 4064(%ecx), %xmm6 #AVX-NE-CONVERT = Disp32(e00f0000) > + {vex3} vcvtneps2bf16y 4064(%ecx), %xmm6 #AVX-NE-CONVERT = Disp32(e00f0000) > + vcvtneps2bf16y -4096(%edx), %xmm6 #AVX-NE-CONVERT Disp32(0= 0f0ffff) > + {evex} vcvtneps2bf16y -4096(%edx), %xmm6 #AVX-NE-CONVERT = Disp32(00f0ffff) > + {vex} vcvtneps2bf16y -4096(%edx), %xmm6 #AVX-NE-CONVERT = Disp32(00f0ffff) > + {vex3} vcvtneps2bf16y -4096(%edx), %xmm6 #AVX-NE-CONVERT = Disp32(00f0ffff) > + > +.intel_syntax noprefix > + vbcstnebf162ps xmm6, WORD PTR [esp+esi*8+0x10000000] #AVX-NE-= CONVERT > + vbcstnebf162ps xmm6, WORD PTR [ecx] #AVX-NE-CONVERT > + vbcstnebf162ps xmm6, WORD PTR [ecx+254] #AVX-NE-CONVERT = Disp32(fe000000) > + vbcstnebf162ps xmm6, WORD PTR [edx-256] #AVX-NE-CONVERT = Disp32(00ffffff) > + vbcstnebf162ps ymm6, WORD PTR [esp+esi*8+0x10000000] #AVX-NE-= CONVERT > + vbcstnebf162ps ymm6, WORD PTR [ecx] #AVX-NE-CONVERT > + vbcstnebf162ps ymm6, WORD PTR [ecx+254] #AVX-NE-CONVERT = Disp32(fe000000) > + vbcstnebf162ps ymm6, WORD PTR [edx-256] #AVX-NE-CONVERT = Disp32(00ffffff) > + vbcstnesh2ps xmm6, WORD PTR [esp+esi*8+0x10000000] #AVX-NE-= CONVERT > + vbcstnesh2ps xmm6, WORD PTR [ecx] #AVX-NE-CONVERT > + vbcstnesh2ps xmm6, WORD PTR [ecx+254] #AVX-NE-CONVERT = Disp32(fe000000) > + vbcstnesh2ps xmm6, WORD PTR [edx-256] #AVX-NE-CONVERT = Disp32(00ffffff) > + vbcstnesh2ps ymm6, WORD PTR [esp+esi*8+0x10000000] #AVX-NE-= CONVERT > + vbcstnesh2ps ymm6, WORD PTR [ecx] #AVX-NE-CONVERT > + vbcstnesh2ps ymm6, WORD PTR [ecx+254] #AVX-NE-CONVERT = Disp32(fe000000) > + vbcstnesh2ps ymm6, WORD PTR [edx-256] #AVX-NE-CONVERT = Disp32(00ffffff) > + vcvtneebf162ps xmm6, XMMWORD PTR [esp+esi*8+0x10000000] = #AVX-NE-CONVERT > + vcvtneebf162ps xmm6, XMMWORD PTR [ecx] #AVX-NE-CONVERT > + vcvtneebf162ps xmm6, XMMWORD PTR [ecx+2032] #AVX-NE-CONVERT = Disp32(f0070000) > + vcvtneebf162ps xmm6, XMMWORD PTR [edx-2048] #AVX-NE-CONVERT = Disp32(00f8ffff) > + vcvtneebf162ps ymm6, YMMWORD PTR [esp+esi*8+0x10000000] = #AVX-NE-CONVERT > + vcvtneebf162ps ymm6, YMMWORD PTR [ecx] #AVX-NE-CONVERT > + vcvtneebf162ps ymm6, YMMWORD PTR [ecx+4064] #AVX-NE-CONVERT = Disp32(e00f0000) > + vcvtneebf162ps ymm6, YMMWORD PTR [edx-4096] #AVX-NE-CONVERT = Disp32(00f0ffff) > + vcvtneeph2ps xmm6, XMMWORD PTR [esp+esi*8+0x10000000] = #AVX-NE-CONVERT > + vcvtneeph2ps xmm6, XMMWORD PTR [ecx] #AVX-NE-CONVERT > + vcvtneeph2ps xmm6, XMMWORD PTR [ecx+2032] #AVX-NE-CONVERT = Disp32(f0070000) > + vcvtneeph2ps xmm6, XMMWORD PTR [edx-2048] #AVX-NE-CONVERT = Disp32(00f8ffff) > + vcvtneeph2ps ymm6, YMMWORD PTR [esp+esi*8+0x10000000] = #AVX-NE-CONVERT > + vcvtneeph2ps ymm6, YMMWORD PTR [ecx] #AVX-NE-CONVERT > + vcvtneeph2ps ymm6, YMMWORD PTR [ecx+4064] #AVX-NE-CONVERT = Disp32(e00f0000) > + vcvtneeph2ps ymm6, YMMWORD PTR [edx-4096] #AVX-NE-CONVERT = Disp32(00f0ffff) > + vcvtneobf162ps xmm6, XMMWORD PTR [esp+esi*8+0x10000000] = #AVX-NE-CONVERT > + vcvtneobf162ps xmm6, XMMWORD PTR [ecx] #AVX-NE-CONVERT > + vcvtneobf162ps xmm6, XMMWORD PTR [ecx+2032] #AVX-NE-CONVERT = Disp32(f0070000) > + vcvtneobf162ps xmm6, XMMWORD PTR [edx-2048] #AVX-NE-CONVERT = Disp32(00f8ffff) > + vcvtneobf162ps ymm6, YMMWORD PTR [esp+esi*8+0x10000000] = #AVX-NE-CONVERT > + vcvtneobf162ps ymm6, YMMWORD PTR [ecx] #AVX-NE-CONVERT > + vcvtneobf162ps ymm6, YMMWORD PTR [ecx+4064] #AVX-NE-CONVERT = Disp32(e00f0000) > + vcvtneobf162ps ymm6, YMMWORD PTR [edx-4096] #AVX-NE-CONVERT = Disp32(00f0ffff) > + vcvtneoph2ps xmm6, XMMWORD PTR [esp+esi*8+0x10000000] = #AVX-NE-CONVERT > + vcvtneoph2ps xmm6, XMMWORD PTR [ecx] #AVX-NE-CONVERT > + vcvtneoph2ps xmm6, XMMWORD PTR [ecx+2032] #AVX-NE-CONVERT = Disp32(f0070000) > + vcvtneoph2ps xmm6, XMMWORD PTR [edx-2048] #AVX-NE-CONVERT = Disp32(00f8ffff) > + vcvtneoph2ps ymm6, YMMWORD PTR [esp+esi*8+0x10000000] = #AVX-NE-CONVERT > + vcvtneoph2ps ymm6, YMMWORD PTR [ecx] #AVX-NE-CONVERT > + vcvtneoph2ps ymm6, YMMWORD PTR [ecx+4064] #AVX-NE-CONVERT = Disp32(e00f0000) > + vcvtneoph2ps ymm6, YMMWORD PTR [edx-4096] #AVX-NE-CONVERT = Disp32(00f0ffff) > + vcvtneps2bf16 xmm6, xmm5 #AVX-NE-CONVERT > + {evex} vcvtneps2bf16 xmm6, xmm5 #AVX-NE-CONVERT > + {vex} vcvtneps2bf16 xmm6, xmm5 #AVX-NE-CONVERT > + {vex3} vcvtneps2bf16 xmm6, xmm5 #AVX-NE-CONVERT > + vcvtneps2bf16 xmm6, ymm5 #AVX-NE-CONVERT > + {evex} vcvtneps2bf16 xmm6, ymm5 #AVX-NE-CONVERT > + {vex} vcvtneps2bf16 xmm6, ymm5 #AVX-NE-CONVERT > + {vex3} vcvtneps2bf16 xmm6, ymm5 #AVX-NE-CONVERT > + vcvtneps2bf16 xmm6, XMMWORD PTR [esp+esi*8+0x10000000] = #AVX-NE-CONVERT > + {evex} vcvtneps2bf16 xmm6, XMMWORD PTR [esp+esi*8+0x10000000] = #AVX-NE-CONVERT > + {vex} vcvtneps2bf16 xmm6, XMMWORD PTR [esp+esi*8+0x10000000] = #AVX-NE-CONVERT > + {vex3} vcvtneps2bf16 xmm6, XMMWORD PTR [esp+esi*8+0x10000000] = #AVX-NE-CONVERT > + vcvtneps2bf16 xmm6, XMMWORD PTR [ecx] #AVX-NE-CONVERT > + {evex} vcvtneps2bf16 xmm6, XMMWORD PTR [ecx] #AVX-NE-CONVERT > + {vex} vcvtneps2bf16 xmm6, XMMWORD PTR [ecx] #AVX-NE-CONVERT > + {vex3} vcvtneps2bf16 xmm6, XMMWORD PTR [ecx] #AVX-NE-CONVERT > + vcvtneps2bf16 xmm6, XMMWORD PTR [ecx+2032] #AVX-NE-CONVERT = Disp32(f0070000) > + {evex} vcvtneps2bf16 xmm6, XMMWORD PTR [ecx+2032] #AVX-NE-= CONVERT Disp32(f0070000) > + {vex} vcvtneps2bf16 xmm6, XMMWORD PTR [ecx+2032] #AVX-NE-= CONVERT Disp32(f0070000) > + {vex3} vcvtneps2bf16 xmm6, XMMWORD PTR [ecx+2032] #AVX-NE-= CONVERT Disp32(f0070000) > + vcvtneps2bf16 xmm6, XMMWORD PTR [edx-2048] #AVX-NE-CONVERT = Disp32(00f8ffff) > + {evex} vcvtneps2bf16 xmm6, XMMWORD PTR [edx-2048] #AVX-NE-= CONVERT Disp32(00f8ffff) > + {vex} vcvtneps2bf16 xmm6, XMMWORD PTR [edx-2048] #AVX-NE-= CONVERT Disp32(00f8ffff) > + {vex3} vcvtneps2bf16 xmm6, XMMWORD PTR [edx-2048] #AVX-NE-= CONVERT Disp32(00f8ffff) > + vcvtneps2bf16 xmm6, YMMWORD PTR [ecx+4064] #AVX-NE-CONVERT = Disp32(e00f0000) > + {evex} vcvtneps2bf16 xmm6, YMMWORD PTR [ecx+4064] #AVX-NE-= CONVERT Disp32(e00f0000) > + {vex} vcvtneps2bf16 xmm6, YMMWORD PTR [ecx+4064] #AVX-NE-= CONVERT Disp32(e00f0000) > + {vex3} vcvtneps2bf16 xmm6, YMMWORD PTR [ecx+4064] #AVX-NE-= CONVERT Disp32(e00f0000) > + vcvtneps2bf16 xmm6, YMMWORD PTR [edx-4096] #AVX-NE-CONVERT = Disp32(00f0ffff) > + {evex} vcvtneps2bf16 xmm6, YMMWORD PTR [edx-4096] #AVX-NE-= CONVERT Disp32(00f0ffff) > + {vex} vcvtneps2bf16 xmm6, YMMWORD PTR [edx-4096] #AVX-NE-= CONVERT Disp32(00f0ffff) > + {vex3} vcvtneps2bf16 xmm6, YMMWORD PTR [edx-4096] #AVX-NE-= CONVERT Disp32(00f0ffff) > diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i38= 6.exp > index f7cb734e7f..9ddf2b451e 100644 > --- a/gas/testsuite/gas/i386/i386.exp > +++ b/gas/testsuite/gas/i386/i386.exp > @@ -483,6 +483,8 @@ if [gas_32_check] then { > run_dump_test "wrmsrns" > run_dump_test "wrmsrns-intel" > run_list_test "msrlist-inval" > + run_dump_test "avx-ne-convert" > + run_dump_test "avx-ne-convert-intel" > run_list_test "sg" > run_dump_test "clzero" > run_dump_test "invlpgb" > @@ -1162,6 +1164,8 @@ if [gas_64_check] then { > run_dump_test "x86-64-wrmsrns-intel" > run_dump_test "x86-64-msrlist" > run_dump_test "x86-64-msrlist-intel" > + run_dump_test "x86-64-avx-ne-convert" > + run_dump_test "x86-64-avx-ne-convert-intel" > run_dump_test "x86-64-clzero" > run_dump_test "x86-64-mwaitx-bdver4" > run_list_test "x86-64-mwaitx-reg" > diff --git a/gas/testsuite/gas/i386/x86-64-avx-ne-convert-intel.d b/gas/t= estsuite/gas/i386/x86-64-avx-ne-convert-intel.d > new file mode 100644 > index 0000000000..96ec69a12c > --- /dev/null > +++ b/gas/testsuite/gas/i386/x86-64-avx-ne-convert-intel.d > @@ -0,0 +1,170 @@ > +#as: > +#objdump: -dw -Mintel > +#name: x86_64 AVX-NE-CONVERT insns (Intel disassembly) > +#source: x86-64-avx-ne-convert.s > + > +.*: +file format .* > + > +Disassembly of section \.text: > + > +0+ <_start>: > +\s*[a-f0-9]+:\s*c4 a2 7a b1 b4 f5 00 00 00 10\s+vbcstnebf162ps xmm6,WORD= PTR \[rbp\+r14\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 c2 7a b1 31\s+vbcstnebf162ps xmm6,WORD PTR \[r9\] > +\s*[a-f0-9]+:\s*c4 e2 7a b1 b1 fe 00 00 00\s+vbcstnebf162ps xmm6,WORD PT= R \[rcx\+0xfe\] > +\s*[a-f0-9]+:\s*c4 e2 7a b1 b2 00 ff ff ff\s+vbcstnebf162ps xmm6,WORD PT= R \[rdx-0x100\] > +\s*[a-f0-9]+:\s*c4 a2 7e b1 b4 f5 00 00 00 10\s+vbcstnebf162ps ymm6,WORD= PTR \[rbp\+r14\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 c2 7e b1 31\s+vbcstnebf162ps ymm6,WORD PTR \[r9\] > +\s*[a-f0-9]+:\s*c4 e2 7e b1 b1 fe 00 00 00\s+vbcstnebf162ps ymm6,WORD PT= R \[rcx\+0xfe\] > +\s*[a-f0-9]+:\s*c4 e2 7e b1 b2 00 ff ff ff\s+vbcstnebf162ps ymm6,WORD PT= R \[rdx-0x100\] > +\s*[a-f0-9]+:\s*c4 a2 79 b1 b4 f5 00 00 00 10\s+vbcstnesh2ps xmm6,WORD P= TR \[rbp\+r14\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 c2 79 b1 31\s+vbcstnesh2ps xmm6,WORD PTR \[r9\] > +\s*[a-f0-9]+:\s*c4 e2 79 b1 b1 fe 00 00 00\s+vbcstnesh2ps xmm6,WORD PTR = \[rcx\+0xfe\] > +\s*[a-f0-9]+:\s*c4 e2 79 b1 b2 00 ff ff ff\s+vbcstnesh2ps xmm6,WORD PTR = \[rdx-0x100\] > +\s*[a-f0-9]+:\s*c4 a2 7d b1 b4 f5 00 00 00 10\s+vbcstnesh2ps ymm6,WORD P= TR \[rbp\+r14\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 c2 7d b1 31\s+vbcstnesh2ps ymm6,WORD PTR \[r9\] > +\s*[a-f0-9]+:\s*c4 e2 7d b1 b1 fe 00 00 00\s+vbcstnesh2ps ymm6,WORD PTR = \[rcx\+0xfe\] > +\s*[a-f0-9]+:\s*c4 e2 7d b1 b2 00 ff ff ff\s+vbcstnesh2ps ymm6,WORD PTR = \[rdx-0x100\] > +\s*[a-f0-9]+:\s*c4 a2 7a b0 b4 f5 00 00 00 10\s+vcvtneebf162ps xmm6,XMMW= ORD PTR \[rbp\+r14\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 c2 7a b0 31\s+vcvtneebf162ps xmm6,XMMWORD PTR \[r9\] > +\s*[a-f0-9]+:\s*c4 e2 7a b0 b1 f0 07 00 00\s+vcvtneebf162ps xmm6,XMMWORD= PTR \[rcx\+0x7f0\] > +\s*[a-f0-9]+:\s*c4 e2 7a b0 b2 00 f8 ff ff\s+vcvtneebf162ps xmm6,XMMWORD= PTR \[rdx-0x800\] > +\s*[a-f0-9]+:\s*c4 a2 7e b0 b4 f5 00 00 00 10\s+vcvtneebf162ps ymm6,YMMW= ORD PTR \[rbp\+r14\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 c2 7e b0 31\s+vcvtneebf162ps ymm6,YMMWORD PTR \[r9\] > +\s*[a-f0-9]+:\s*c4 e2 7e b0 b1 e0 0f 00 00\s+vcvtneebf162ps ymm6,YMMWORD= PTR \[rcx\+0xfe0\] > +\s*[a-f0-9]+:\s*c4 e2 7e b0 b2 00 f0 ff ff\s+vcvtneebf162ps ymm6,YMMWORD= PTR \[rdx-0x1000\] > +\s*[a-f0-9]+:\s*c4 a2 79 b0 b4 f5 00 00 00 10\s+vcvtneeph2ps xmm6,XMMWOR= D PTR \[rbp\+r14\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 c2 79 b0 31\s+vcvtneeph2ps xmm6,XMMWORD PTR \[r9\] > +\s*[a-f0-9]+:\s*c4 e2 79 b0 b1 f0 07 00 00\s+vcvtneeph2ps xmm6,XMMWORD P= TR \[rcx\+0x7f0\] > +\s*[a-f0-9]+:\s*c4 e2 79 b0 b2 00 f8 ff ff\s+vcvtneeph2ps xmm6,XMMWORD P= TR \[rdx-0x800\] > +\s*[a-f0-9]+:\s*c4 a2 7d b0 b4 f5 00 00 00 10\s+vcvtneeph2ps ymm6,YMMWOR= D PTR \[rbp\+r14\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 c2 7d b0 31\s+vcvtneeph2ps ymm6,YMMWORD PTR \[r9\] > +\s*[a-f0-9]+:\s*c4 e2 7d b0 b1 e0 0f 00 00\s+vcvtneeph2ps ymm6,YMMWORD P= TR \[rcx\+0xfe0\] > +\s*[a-f0-9]+:\s*c4 e2 7d b0 b2 00 f0 ff ff\s+vcvtneeph2ps ymm6,YMMWORD P= TR \[rdx-0x1000\] > +\s*[a-f0-9]+:\s*c4 a2 7b b0 b4 f5 00 00 00 10\s+vcvtneobf162ps xmm6,XMMW= ORD PTR \[rbp\+r14\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 c2 7b b0 31\s+vcvtneobf162ps xmm6,XMMWORD PTR \[r9\] > +\s*[a-f0-9]+:\s*c4 e2 7b b0 b1 f0 07 00 00\s+vcvtneobf162ps xmm6,XMMWORD= PTR \[rcx\+0x7f0\] > +\s*[a-f0-9]+:\s*c4 e2 7b b0 b2 00 f8 ff ff\s+vcvtneobf162ps xmm6,XMMWORD= PTR \[rdx-0x800\] > +\s*[a-f0-9]+:\s*c4 a2 7f b0 b4 f5 00 00 00 10\s+vcvtneobf162ps ymm6,YMMW= ORD PTR \[rbp\+r14\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 c2 7f b0 31\s+vcvtneobf162ps ymm6,YMMWORD PTR \[r9\] > +\s*[a-f0-9]+:\s*c4 e2 7f b0 b1 e0 0f 00 00\s+vcvtneobf162ps ymm6,YMMWORD= PTR \[rcx\+0xfe0\] > +\s*[a-f0-9]+:\s*c4 e2 7f b0 b2 00 f0 ff ff\s+vcvtneobf162ps ymm6,YMMWORD= PTR \[rdx-0x1000\] > +\s*[a-f0-9]+:\s*c4 a2 78 b0 b4 f5 00 00 00 10\s+vcvtneoph2ps xmm6,XMMWOR= D PTR \[rbp\+r14\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 c2 78 b0 31\s+vcvtneoph2ps xmm6,XMMWORD PTR \[r9\] > +\s*[a-f0-9]+:\s*c4 e2 78 b0 b1 f0 07 00 00\s+vcvtneoph2ps xmm6,XMMWORD P= TR \[rcx\+0x7f0\] > +\s*[a-f0-9]+:\s*c4 e2 78 b0 b2 00 f8 ff ff\s+vcvtneoph2ps xmm6,XMMWORD P= TR \[rdx-0x800\] > +\s*[a-f0-9]+:\s*c4 a2 7c b0 b4 f5 00 00 00 10\s+vcvtneoph2ps ymm6,YMMWOR= D PTR \[rbp\+r14\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 c2 7c b0 31\s+vcvtneoph2ps ymm6,YMMWORD PTR \[r9\] > +\s*[a-f0-9]+:\s*c4 e2 7c b0 b1 e0 0f 00 00\s+vcvtneoph2ps ymm6,YMMWORD P= TR \[rcx\+0xfe0\] > +\s*[a-f0-9]+:\s*c4 e2 7c b0 b2 00 f0 ff ff\s+vcvtneoph2ps ymm6,YMMWORD P= TR \[rdx-0x1000\] > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 f5\s+vcvtneps2bf16 xmm6,xmm5 > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 f5\s+vcvtneps2bf16 xmm6,xmm5 > +\s*[a-f0-9]+:\s*c4 e2 7a 72 f5\s+\{vex\} vcvtneps2bf16 xmm6,xmm5 > +\s*[a-f0-9]+:\s*c4 e2 7a 72 f5\s+\{vex\} vcvtneps2bf16 xmm6,xmm5 > +\s*[a-f0-9]+:\s*62 f2 7e 28 72 f5\s+vcvtneps2bf16 xmm6,ymm5 > +\s*[a-f0-9]+:\s*62 f2 7e 28 72 f5\s+vcvtneps2bf16 xmm6,ymm5 > +\s*[a-f0-9]+:\s*c4 e2 7e 72 f5\s+\{vex\} vcvtneps2bf16 xmm6,ymm5 > +\s*[a-f0-9]+:\s*c4 e2 7e 72 f5\s+\{vex\} vcvtneps2bf16 xmm6,ymm5 > +\s*[a-f0-9]+:\s*62 b2 7e 08 72 b4 f5 00 00 00 10\s+vcvtneps2bf16 xmm6,XM= MWORD PTR \[rbp\+r14\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*62 b2 7e 08 72 b4 f5 00 00 00 10\s+vcvtneps2bf16 xmm6,XM= MWORD PTR \[rbp\+r14\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 a2 7a 72 b4 f5 00 00 00 10\s+\{vex\} vcvtneps2bf16 xm= m6,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 a2 7a 72 b4 f5 00 00 00 10\s+\{vex\} vcvtneps2bf16 xm= m6,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*62 d2 7e 08 72 31\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[r9\= ] > +\s*[a-f0-9]+:\s*62 d2 7e 08 72 31\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[r9\= ] > +\s*[a-f0-9]+:\s*c4 c2 7a 72 31\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR = \[r9\] > +\s*[a-f0-9]+:\s*c4 c2 7a 72 31\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR = \[r9\] > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 71 7f\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[= rcx\+0x7f0\] > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 71 7f\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[= rcx\+0x7f0\] > +\s*[a-f0-9]+:\s*c4 e2 7a 72 b1 f0 07 00 00\s+\{vex\} vcvtneps2bf16 xmm6,= XMMWORD PTR \[rcx\+0x7f0\] > +\s*[a-f0-9]+:\s*c4 e2 7a 72 b1 f0 07 00 00\s+\{vex\} vcvtneps2bf16 xmm6,= XMMWORD PTR \[rcx\+0x7f0\] > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 72 80\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[= rdx-0x800\] > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 72 80\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[= rdx-0x800\] > +\s*[a-f0-9]+:\s*c4 e2 7a 72 b2 00 f8 ff ff\s+\{vex\} vcvtneps2bf16 xmm6,= XMMWORD PTR \[rdx-0x800\] > +\s*[a-f0-9]+:\s*c4 e2 7a 72 b2 00 f8 ff ff\s+\{vex\} vcvtneps2bf16 xmm6,= XMMWORD PTR \[rdx-0x800\] > +\s*[a-f0-9]+:\s*62 f2 7e 28 72 71 7f\s+vcvtneps2bf16 xmm6,YMMWORD PTR \[= rcx\+0xfe0\] > +\s*[a-f0-9]+:\s*62 f2 7e 28 72 71 7f\s+vcvtneps2bf16 xmm6,YMMWORD PTR \[= rcx\+0xfe0\] > +\s*[a-f0-9]+:\s*c4 e2 7e 72 b1 e0 0f 00 00\s+\{vex\} vcvtneps2bf16 xmm6,= YMMWORD PTR \[rcx\+0xfe0\] > +\s*[a-f0-9]+:\s*c4 e2 7e 72 b1 e0 0f 00 00\s+\{vex\} vcvtneps2bf16 xmm6,= YMMWORD PTR \[rcx\+0xfe0\] > +\s*[a-f0-9]+:\s*62 f2 7e 28 72 72 80\s+vcvtneps2bf16 xmm6,YMMWORD PTR \[= rdx-0x1000\] > +\s*[a-f0-9]+:\s*62 f2 7e 28 72 72 80\s+vcvtneps2bf16 xmm6,YMMWORD PTR \[= rdx-0x1000\] > +\s*[a-f0-9]+:\s*c4 e2 7e 72 b2 00 f0 ff ff\s+\{vex\} vcvtneps2bf16 xmm6,= YMMWORD PTR \[rdx-0x1000\] > +\s*[a-f0-9]+:\s*c4 e2 7e 72 b2 00 f0 ff ff\s+\{vex\} vcvtneps2bf16 xmm6,= YMMWORD PTR \[rdx-0x1000\] > +\s*[a-f0-9]+:\s*c4 a2 7a b1 b4 f5 00 00 00 10\s+vbcstnebf162ps xmm6,WORD= PTR \[rbp\+r14\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 c2 7a b1 31\s+vbcstnebf162ps xmm6,WORD PTR \[r9\] > +\s*[a-f0-9]+:\s*c4 e2 7a b1 b1 fe 00 00 00\s+vbcstnebf162ps xmm6,WORD PT= R \[rcx\+0xfe\] > +\s*[a-f0-9]+:\s*c4 e2 7a b1 b2 00 ff ff ff\s+vbcstnebf162ps xmm6,WORD PT= R \[rdx-0x100\] > +\s*[a-f0-9]+:\s*c4 a2 7e b1 b4 f5 00 00 00 10\s+vbcstnebf162ps ymm6,WORD= PTR \[rbp\+r14\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 c2 7e b1 31\s+vbcstnebf162ps ymm6,WORD PTR \[r9\] > +\s*[a-f0-9]+:\s*c4 e2 7e b1 b1 fe 00 00 00\s+vbcstnebf162ps ymm6,WORD PT= R \[rcx\+0xfe\] > +\s*[a-f0-9]+:\s*c4 e2 7e b1 b2 00 ff ff ff\s+vbcstnebf162ps ymm6,WORD PT= R \[rdx-0x100\] > +\s*[a-f0-9]+:\s*c4 a2 79 b1 b4 f5 00 00 00 10\s+vbcstnesh2ps xmm6,WORD P= TR \[rbp\+r14\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 c2 79 b1 31\s+vbcstnesh2ps xmm6,WORD PTR \[r9\] > +\s*[a-f0-9]+:\s*c4 e2 79 b1 b1 fe 00 00 00\s+vbcstnesh2ps xmm6,WORD PTR = \[rcx\+0xfe\] > +\s*[a-f0-9]+:\s*c4 e2 79 b1 b2 00 ff ff ff\s+vbcstnesh2ps xmm6,WORD PTR = \[rdx-0x100\] > +\s*[a-f0-9]+:\s*c4 a2 7d b1 b4 f5 00 00 00 10\s+vbcstnesh2ps ymm6,WORD P= TR \[rbp\+r14\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 c2 7d b1 31\s+vbcstnesh2ps ymm6,WORD PTR \[r9\] > +\s*[a-f0-9]+:\s*c4 e2 7d b1 b1 fe 00 00 00\s+vbcstnesh2ps ymm6,WORD PTR = \[rcx\+0xfe\] > +\s*[a-f0-9]+:\s*c4 e2 7d b1 b2 00 ff ff ff\s+vbcstnesh2ps ymm6,WORD PTR = \[rdx-0x100\] > +\s*[a-f0-9]+:\s*c4 a2 7a b0 b4 f5 00 00 00 10\s+vcvtneebf162ps xmm6,XMMW= ORD PTR \[rbp\+r14\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 c2 7a b0 31\s+vcvtneebf162ps xmm6,XMMWORD PTR \[r9\] > +\s*[a-f0-9]+:\s*c4 e2 7a b0 b1 f0 07 00 00\s+vcvtneebf162ps xmm6,XMMWORD= PTR \[rcx\+0x7f0\] > +\s*[a-f0-9]+:\s*c4 e2 7a b0 b2 00 f8 ff ff\s+vcvtneebf162ps xmm6,XMMWORD= PTR \[rdx-0x800\] > +\s*[a-f0-9]+:\s*c4 a2 7e b0 b4 f5 00 00 00 10\s+vcvtneebf162ps ymm6,YMMW= ORD PTR \[rbp\+r14\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 c2 7e b0 31\s+vcvtneebf162ps ymm6,YMMWORD PTR \[r9\] > +\s*[a-f0-9]+:\s*c4 e2 7e b0 b1 e0 0f 00 00\s+vcvtneebf162ps ymm6,YMMWORD= PTR \[rcx\+0xfe0\] > +\s*[a-f0-9]+:\s*c4 e2 7e b0 b2 00 f0 ff ff\s+vcvtneebf162ps ymm6,YMMWORD= PTR \[rdx-0x1000\] > +\s*[a-f0-9]+:\s*c4 a2 79 b0 b4 f5 00 00 00 10\s+vcvtneeph2ps xmm6,XMMWOR= D PTR \[rbp\+r14\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 c2 79 b0 31\s+vcvtneeph2ps xmm6,XMMWORD PTR \[r9\] > +\s*[a-f0-9]+:\s*c4 e2 79 b0 b1 f0 07 00 00\s+vcvtneeph2ps xmm6,XMMWORD P= TR \[rcx\+0x7f0\] > +\s*[a-f0-9]+:\s*c4 e2 79 b0 b2 00 f8 ff ff\s+vcvtneeph2ps xmm6,XMMWORD P= TR \[rdx-0x800\] > +\s*[a-f0-9]+:\s*c4 a2 7d b0 b4 f5 00 00 00 10\s+vcvtneeph2ps ymm6,YMMWOR= D PTR \[rbp\+r14\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 c2 7d b0 31\s+vcvtneeph2ps ymm6,YMMWORD PTR \[r9\] > +\s*[a-f0-9]+:\s*c4 e2 7d b0 b1 e0 0f 00 00\s+vcvtneeph2ps ymm6,YMMWORD P= TR \[rcx\+0xfe0\] > +\s*[a-f0-9]+:\s*c4 e2 7d b0 b2 00 f0 ff ff\s+vcvtneeph2ps ymm6,YMMWORD P= TR \[rdx-0x1000\] > +\s*[a-f0-9]+:\s*c4 a2 7b b0 b4 f5 00 00 00 10\s+vcvtneobf162ps xmm6,XMMW= ORD PTR \[rbp\+r14\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 c2 7b b0 31\s+vcvtneobf162ps xmm6,XMMWORD PTR \[r9\] > +\s*[a-f0-9]+:\s*c4 e2 7b b0 b1 f0 07 00 00\s+vcvtneobf162ps xmm6,XMMWORD= PTR \[rcx\+0x7f0\] > +\s*[a-f0-9]+:\s*c4 e2 7b b0 b2 00 f8 ff ff\s+vcvtneobf162ps xmm6,XMMWORD= PTR \[rdx-0x800\] > +\s*[a-f0-9]+:\s*c4 a2 7f b0 b4 f5 00 00 00 10\s+vcvtneobf162ps ymm6,YMMW= ORD PTR \[rbp\+r14\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 c2 7f b0 31\s+vcvtneobf162ps ymm6,YMMWORD PTR \[r9\] > +\s*[a-f0-9]+:\s*c4 e2 7f b0 b1 e0 0f 00 00\s+vcvtneobf162ps ymm6,YMMWORD= PTR \[rcx\+0xfe0\] > +\s*[a-f0-9]+:\s*c4 e2 7f b0 b2 00 f0 ff ff\s+vcvtneobf162ps ymm6,YMMWORD= PTR \[rdx-0x1000\] > +\s*[a-f0-9]+:\s*c4 a2 78 b0 b4 f5 00 00 00 10\s+vcvtneoph2ps xmm6,XMMWOR= D PTR \[rbp\+r14\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 c2 78 b0 31\s+vcvtneoph2ps xmm6,XMMWORD PTR \[r9\] > +\s*[a-f0-9]+:\s*c4 e2 78 b0 b1 f0 07 00 00\s+vcvtneoph2ps xmm6,XMMWORD P= TR \[rcx\+0x7f0\] > +\s*[a-f0-9]+:\s*c4 e2 78 b0 b2 00 f8 ff ff\s+vcvtneoph2ps xmm6,XMMWORD P= TR \[rdx-0x800\] > +\s*[a-f0-9]+:\s*c4 a2 7c b0 b4 f5 00 00 00 10\s+vcvtneoph2ps ymm6,YMMWOR= D PTR \[rbp\+r14\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 c2 7c b0 31\s+vcvtneoph2ps ymm6,YMMWORD PTR \[r9\] > +\s*[a-f0-9]+:\s*c4 e2 7c b0 b1 e0 0f 00 00\s+vcvtneoph2ps ymm6,YMMWORD P= TR \[rcx\+0xfe0\] > +\s*[a-f0-9]+:\s*c4 e2 7c b0 b2 00 f0 ff ff\s+vcvtneoph2ps ymm6,YMMWORD P= TR \[rdx-0x1000\] > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 f5\s+vcvtneps2bf16 xmm6,xmm5 > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 f5\s+vcvtneps2bf16 xmm6,xmm5 > +\s*[a-f0-9]+:\s*c4 e2 7a 72 f5\s+\{vex\} vcvtneps2bf16 xmm6,xmm5 > +\s*[a-f0-9]+:\s*c4 e2 7a 72 f5\s+\{vex\} vcvtneps2bf16 xmm6,xmm5 > +\s*[a-f0-9]+:\s*62 f2 7e 28 72 f5\s+vcvtneps2bf16 xmm6,ymm5 > +\s*[a-f0-9]+:\s*62 f2 7e 28 72 f5\s+vcvtneps2bf16 xmm6,ymm5 > +\s*[a-f0-9]+:\s*c4 e2 7e 72 f5\s+\{vex\} vcvtneps2bf16 xmm6,ymm5 > +\s*[a-f0-9]+:\s*c4 e2 7e 72 f5\s+\{vex\} vcvtneps2bf16 xmm6,ymm5 > +\s*[a-f0-9]+:\s*62 b2 7e 08 72 b4 f5 00 00 00 10\s+vcvtneps2bf16 xmm6,XM= MWORD PTR \[rbp\+r14\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*62 b2 7e 08 72 b4 f5 00 00 00 10\s+vcvtneps2bf16 xmm6,XM= MWORD PTR \[rbp\+r14\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 a2 7a 72 b4 f5 00 00 00 10\s+\{vex\} vcvtneps2bf16 xm= m6,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 a2 7a 72 b4 f5 00 00 00 10\s+\{vex\} vcvtneps2bf16 xm= m6,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*62 d2 7e 08 72 31\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[r9\= ] > +\s*[a-f0-9]+:\s*62 d2 7e 08 72 31\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[r9\= ] > +\s*[a-f0-9]+:\s*c4 c2 7a 72 31\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR = \[r9\] > +\s*[a-f0-9]+:\s*c4 c2 7a 72 31\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR = \[r9\] > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 71 7f\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[= rcx\+0x7f0\] > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 71 7f\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[= rcx\+0x7f0\] > +\s*[a-f0-9]+:\s*c4 e2 7a 72 b1 f0 07 00 00\s+\{vex\} vcvtneps2bf16 xmm6,= XMMWORD PTR \[rcx\+0x7f0\] > +\s*[a-f0-9]+:\s*c4 e2 7a 72 b1 f0 07 00 00\s+\{vex\} vcvtneps2bf16 xmm6,= XMMWORD PTR \[rcx\+0x7f0\] > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 72 80\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[= rdx-0x800\] > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 72 80\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[= rdx-0x800\] > +\s*[a-f0-9]+:\s*c4 e2 7a 72 b2 00 f8 ff ff\s+\{vex\} vcvtneps2bf16 xmm6,= XMMWORD PTR \[rdx-0x800\] > +\s*[a-f0-9]+:\s*c4 e2 7a 72 b2 00 f8 ff ff\s+\{vex\} vcvtneps2bf16 xmm6,= XMMWORD PTR \[rdx-0x800\] > +\s*[a-f0-9]+:\s*62 f2 7e 28 72 71 7f\s+vcvtneps2bf16 xmm6,YMMWORD PTR \[= rcx\+0xfe0\] > +\s*[a-f0-9]+:\s*62 f2 7e 28 72 71 7f\s+vcvtneps2bf16 xmm6,YMMWORD PTR \[= rcx\+0xfe0\] > +\s*[a-f0-9]+:\s*c4 e2 7e 72 b1 e0 0f 00 00\s+\{vex\} vcvtneps2bf16 xmm6,= YMMWORD PTR \[rcx\+0xfe0\] > +\s*[a-f0-9]+:\s*c4 e2 7e 72 b1 e0 0f 00 00\s+\{vex\} vcvtneps2bf16 xmm6,= YMMWORD PTR \[rcx\+0xfe0\] > +\s*[a-f0-9]+:\s*62 f2 7e 28 72 72 80\s+vcvtneps2bf16 xmm6,YMMWORD PTR \[= rdx-0x1000\] > +\s*[a-f0-9]+:\s*62 f2 7e 28 72 72 80\s+vcvtneps2bf16 xmm6,YMMWORD PTR \[= rdx-0x1000\] > +\s*[a-f0-9]+:\s*c4 e2 7e 72 b2 00 f0 ff ff\s+\{vex\} vcvtneps2bf16 xmm6,= YMMWORD PTR \[rdx-0x1000\] > +\s*[a-f0-9]+:\s*c4 e2 7e 72 b2 00 f0 ff ff\s+\{vex\} vcvtneps2bf16 xmm6,= YMMWORD PTR \[rdx-0x1000\] > diff --git a/gas/testsuite/gas/i386/x86-64-avx-ne-convert.d b/gas/testsui= te/gas/i386/x86-64-avx-ne-convert.d > new file mode 100644 > index 0000000000..6bd8391ed5 > --- /dev/null > +++ b/gas/testsuite/gas/i386/x86-64-avx-ne-convert.d > @@ -0,0 +1,170 @@ > +#as: > +#objdump: -dw > +#name: x86_64 AVX-NE-CONVERT insns > +#source: x86-64-avx-ne-convert.s > + > +.*: +file format .* > + > +Disassembly of section \.text: > + > +0+ <_start>: > +\s*[a-f0-9]+:\s*c4 a2 7a b1 b4 f5 00 00 00 10\s+vbcstnebf162ps 0x1000000= 0\(%rbp,%r14,8\),%xmm6 > +\s*[a-f0-9]+:\s*c4 c2 7a b1 31\s+vbcstnebf162ps \(%r9\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7a b1 b1 fe 00 00 00\s+vbcstnebf162ps 0xfe\(%rcx\)= ,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7a b1 b2 00 ff ff ff\s+vbcstnebf162ps -0x100\(%rdx= \),%xmm6 > +\s*[a-f0-9]+:\s*c4 a2 7e b1 b4 f5 00 00 00 10\s+vbcstnebf162ps 0x1000000= 0\(%rbp,%r14,8\),%ymm6 > +\s*[a-f0-9]+:\s*c4 c2 7e b1 31\s+vbcstnebf162ps \(%r9\),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7e b1 b1 fe 00 00 00\s+vbcstnebf162ps 0xfe\(%rcx\)= ,%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7e b1 b2 00 ff ff ff\s+vbcstnebf162ps -0x100\(%rdx= \),%ymm6 > +\s*[a-f0-9]+:\s*c4 a2 79 b1 b4 f5 00 00 00 10\s+vbcstnesh2ps 0x10000000\= (%rbp,%r14,8\),%xmm6 > +\s*[a-f0-9]+:\s*c4 c2 79 b1 31\s+vbcstnesh2ps \(%r9\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 79 b1 b1 fe 00 00 00\s+vbcstnesh2ps 0xfe\(%rcx\),%= xmm6 > +\s*[a-f0-9]+:\s*c4 e2 79 b1 b2 00 ff ff ff\s+vbcstnesh2ps -0x100\(%rdx\)= ,%xmm6 > +\s*[a-f0-9]+:\s*c4 a2 7d b1 b4 f5 00 00 00 10\s+vbcstnesh2ps 0x10000000\= (%rbp,%r14,8\),%ymm6 > +\s*[a-f0-9]+:\s*c4 c2 7d b1 31\s+vbcstnesh2ps \(%r9\),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7d b1 b1 fe 00 00 00\s+vbcstnesh2ps 0xfe\(%rcx\),%= ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7d b1 b2 00 ff ff ff\s+vbcstnesh2ps -0x100\(%rdx\)= ,%ymm6 > +\s*[a-f0-9]+:\s*c4 a2 7a b0 b4 f5 00 00 00 10\s+vcvtneebf162ps 0x1000000= 0\(%rbp,%r14,8\),%xmm6 > +\s*[a-f0-9]+:\s*c4 c2 7a b0 31\s+vcvtneebf162ps \(%r9\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7a b0 b1 f0 07 00 00\s+vcvtneebf162ps 0x7f0\(%rcx\= ),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7a b0 b2 00 f8 ff ff\s+vcvtneebf162ps -0x800\(%rdx= \),%xmm6 > +\s*[a-f0-9]+:\s*c4 a2 7e b0 b4 f5 00 00 00 10\s+vcvtneebf162ps 0x1000000= 0\(%rbp,%r14,8\),%ymm6 > +\s*[a-f0-9]+:\s*c4 c2 7e b0 31\s+vcvtneebf162ps \(%r9\),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7e b0 b1 e0 0f 00 00\s+vcvtneebf162ps 0xfe0\(%rcx\= ),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7e b0 b2 00 f0 ff ff\s+vcvtneebf162ps -0x1000\(%rd= x\),%ymm6 > +\s*[a-f0-9]+:\s*c4 a2 79 b0 b4 f5 00 00 00 10\s+vcvtneeph2ps 0x10000000\= (%rbp,%r14,8\),%xmm6 > +\s*[a-f0-9]+:\s*c4 c2 79 b0 31\s+vcvtneeph2ps \(%r9\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 79 b0 b1 f0 07 00 00\s+vcvtneeph2ps 0x7f0\(%rcx\),= %xmm6 > +\s*[a-f0-9]+:\s*c4 e2 79 b0 b2 00 f8 ff ff\s+vcvtneeph2ps -0x800\(%rdx\)= ,%xmm6 > +\s*[a-f0-9]+:\s*c4 a2 7d b0 b4 f5 00 00 00 10\s+vcvtneeph2ps 0x10000000\= (%rbp,%r14,8\),%ymm6 > +\s*[a-f0-9]+:\s*c4 c2 7d b0 31\s+vcvtneeph2ps \(%r9\),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7d b0 b1 e0 0f 00 00\s+vcvtneeph2ps 0xfe0\(%rcx\),= %ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7d b0 b2 00 f0 ff ff\s+vcvtneeph2ps -0x1000\(%rdx\= ),%ymm6 > +\s*[a-f0-9]+:\s*c4 a2 7b b0 b4 f5 00 00 00 10\s+vcvtneobf162ps 0x1000000= 0\(%rbp,%r14,8\),%xmm6 > +\s*[a-f0-9]+:\s*c4 c2 7b b0 31\s+vcvtneobf162ps \(%r9\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7b b0 b1 f0 07 00 00\s+vcvtneobf162ps 0x7f0\(%rcx\= ),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7b b0 b2 00 f8 ff ff\s+vcvtneobf162ps -0x800\(%rdx= \),%xmm6 > +\s*[a-f0-9]+:\s*c4 a2 7f b0 b4 f5 00 00 00 10\s+vcvtneobf162ps 0x1000000= 0\(%rbp,%r14,8\),%ymm6 > +\s*[a-f0-9]+:\s*c4 c2 7f b0 31\s+vcvtneobf162ps \(%r9\),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7f b0 b1 e0 0f 00 00\s+vcvtneobf162ps 0xfe0\(%rcx\= ),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7f b0 b2 00 f0 ff ff\s+vcvtneobf162ps -0x1000\(%rd= x\),%ymm6 > +\s*[a-f0-9]+:\s*c4 a2 78 b0 b4 f5 00 00 00 10\s+vcvtneoph2ps 0x10000000\= (%rbp,%r14,8\),%xmm6 > +\s*[a-f0-9]+:\s*c4 c2 78 b0 31\s+vcvtneoph2ps \(%r9\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 78 b0 b1 f0 07 00 00\s+vcvtneoph2ps 0x7f0\(%rcx\),= %xmm6 > +\s*[a-f0-9]+:\s*c4 e2 78 b0 b2 00 f8 ff ff\s+vcvtneoph2ps -0x800\(%rdx\)= ,%xmm6 > +\s*[a-f0-9]+:\s*c4 a2 7c b0 b4 f5 00 00 00 10\s+vcvtneoph2ps 0x10000000\= (%rbp,%r14,8\),%ymm6 > +\s*[a-f0-9]+:\s*c4 c2 7c b0 31\s+vcvtneoph2ps \(%r9\),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7c b0 b1 e0 0f 00 00\s+vcvtneoph2ps 0xfe0\(%rcx\),= %ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7c b0 b2 00 f0 ff ff\s+vcvtneoph2ps -0x1000\(%rdx\= ),%ymm6 > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 f5\s+vcvtneps2bf16 %xmm5,%xmm6 > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 f5\s+vcvtneps2bf16 %xmm5,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7a 72 f5\s+\{vex\} vcvtneps2bf16 %xmm5,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7a 72 f5\s+\{vex\} vcvtneps2bf16 %xmm5,%xmm6 > +\s*[a-f0-9]+:\s*62 f2 7e 28 72 f5\s+vcvtneps2bf16 %ymm5,%xmm6 > +\s*[a-f0-9]+:\s*62 f2 7e 28 72 f5\s+vcvtneps2bf16 %ymm5,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7e 72 f5\s+\{vex\} vcvtneps2bf16 %ymm5,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7e 72 f5\s+\{vex\} vcvtneps2bf16 %ymm5,%xmm6 > +\s*[a-f0-9]+:\s*62 b2 7e 08 72 b4 f5 00 00 00 10\s+vcvtneps2bf16x 0x1000= 0000\(%rbp,%r14,8\),%xmm6 > +\s*[a-f0-9]+:\s*62 b2 7e 08 72 b4 f5 00 00 00 10\s+vcvtneps2bf16x 0x1000= 0000\(%rbp,%r14,8\),%xmm6 > +\s*[a-f0-9]+:\s*c4 a2 7a 72 b4 f5 00 00 00 10\s+\{vex\} vcvtneps2bf16x 0= x10000000\(%rbp,%r14,8\),%xmm6 > +\s*[a-f0-9]+:\s*c4 a2 7a 72 b4 f5 00 00 00 10\s+\{vex\} vcvtneps2bf16x 0= x10000000\(%rbp,%r14,8\),%xmm6 > +\s*[a-f0-9]+:\s*62 d2 7e 08 72 31\s+vcvtneps2bf16x \(%r9\),%xmm6 > +\s*[a-f0-9]+:\s*62 d2 7e 08 72 31\s+vcvtneps2bf16x \(%r9\),%xmm6 > +\s*[a-f0-9]+:\s*c4 c2 7a 72 31\s+\{vex\} vcvtneps2bf16x \(%r9\),%xmm6 > +\s*[a-f0-9]+:\s*c4 c2 7a 72 31\s+\{vex\} vcvtneps2bf16x \(%r9\),%xmm6 > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 71 7f\s+vcvtneps2bf16x 0x7f0\(%rcx\),%xmm= 6 > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 71 7f\s+vcvtneps2bf16x 0x7f0\(%rcx\),%xmm= 6 > +\s*[a-f0-9]+:\s*c4 e2 7a 72 b1 f0 07 00 00\s+\{vex\} vcvtneps2bf16x 0x7f= 0\(%rcx\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7a 72 b1 f0 07 00 00\s+\{vex\} vcvtneps2bf16x 0x7f= 0\(%rcx\),%xmm6 > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 72 80\s+vcvtneps2bf16x -0x800\(%rdx\),%xm= m6 > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 72 80\s+vcvtneps2bf16x -0x800\(%rdx\),%xm= m6 > +\s*[a-f0-9]+:\s*c4 e2 7a 72 b2 00 f8 ff ff\s+\{vex\} vcvtneps2bf16x -0x8= 00\(%rdx\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7a 72 b2 00 f8 ff ff\s+\{vex\} vcvtneps2bf16x -0x8= 00\(%rdx\),%xmm6 > +\s*[a-f0-9]+:\s*62 f2 7e 28 72 71 7f\s+vcvtneps2bf16y 0xfe0\(%rcx\),%xmm= 6 > +\s*[a-f0-9]+:\s*62 f2 7e 28 72 71 7f\s+vcvtneps2bf16y 0xfe0\(%rcx\),%xmm= 6 > +\s*[a-f0-9]+:\s*c4 e2 7e 72 b1 e0 0f 00 00\s+\{vex\} vcvtneps2bf16y 0xfe= 0\(%rcx\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7e 72 b1 e0 0f 00 00\s+\{vex\} vcvtneps2bf16y 0xfe= 0\(%rcx\),%xmm6 > +\s*[a-f0-9]+:\s*62 f2 7e 28 72 72 80\s+vcvtneps2bf16y -0x1000\(%rdx\),%x= mm6 > +\s*[a-f0-9]+:\s*62 f2 7e 28 72 72 80\s+vcvtneps2bf16y -0x1000\(%rdx\),%x= mm6 > +\s*[a-f0-9]+:\s*c4 e2 7e 72 b2 00 f0 ff ff\s+\{vex\} vcvtneps2bf16y -0x1= 000\(%rdx\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7e 72 b2 00 f0 ff ff\s+\{vex\} vcvtneps2bf16y -0x1= 000\(%rdx\),%xmm6 > +\s*[a-f0-9]+:\s*c4 a2 7a b1 b4 f5 00 00 00 10\s+vbcstnebf162ps 0x1000000= 0\(%rbp,%r14,8\),%xmm6 > +\s*[a-f0-9]+:\s*c4 c2 7a b1 31\s+vbcstnebf162ps \(%r9\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7a b1 b1 fe 00 00 00\s+vbcstnebf162ps 0xfe\(%rcx\)= ,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7a b1 b2 00 ff ff ff\s+vbcstnebf162ps -0x100\(%rdx= \),%xmm6 > +\s*[a-f0-9]+:\s*c4 a2 7e b1 b4 f5 00 00 00 10\s+vbcstnebf162ps 0x1000000= 0\(%rbp,%r14,8\),%ymm6 > +\s*[a-f0-9]+:\s*c4 c2 7e b1 31\s+vbcstnebf162ps \(%r9\),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7e b1 b1 fe 00 00 00\s+vbcstnebf162ps 0xfe\(%rcx\)= ,%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7e b1 b2 00 ff ff ff\s+vbcstnebf162ps -0x100\(%rdx= \),%ymm6 > +\s*[a-f0-9]+:\s*c4 a2 79 b1 b4 f5 00 00 00 10\s+vbcstnesh2ps 0x10000000\= (%rbp,%r14,8\),%xmm6 > +\s*[a-f0-9]+:\s*c4 c2 79 b1 31\s+vbcstnesh2ps \(%r9\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 79 b1 b1 fe 00 00 00\s+vbcstnesh2ps 0xfe\(%rcx\),%= xmm6 > +\s*[a-f0-9]+:\s*c4 e2 79 b1 b2 00 ff ff ff\s+vbcstnesh2ps -0x100\(%rdx\)= ,%xmm6 > +\s*[a-f0-9]+:\s*c4 a2 7d b1 b4 f5 00 00 00 10\s+vbcstnesh2ps 0x10000000\= (%rbp,%r14,8\),%ymm6 > +\s*[a-f0-9]+:\s*c4 c2 7d b1 31\s+vbcstnesh2ps \(%r9\),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7d b1 b1 fe 00 00 00\s+vbcstnesh2ps 0xfe\(%rcx\),%= ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7d b1 b2 00 ff ff ff\s+vbcstnesh2ps -0x100\(%rdx\)= ,%ymm6 > +\s*[a-f0-9]+:\s*c4 a2 7a b0 b4 f5 00 00 00 10\s+vcvtneebf162ps 0x1000000= 0\(%rbp,%r14,8\),%xmm6 > +\s*[a-f0-9]+:\s*c4 c2 7a b0 31\s+vcvtneebf162ps \(%r9\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7a b0 b1 f0 07 00 00\s+vcvtneebf162ps 0x7f0\(%rcx\= ),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7a b0 b2 00 f8 ff ff\s+vcvtneebf162ps -0x800\(%rdx= \),%xmm6 > +\s*[a-f0-9]+:\s*c4 a2 7e b0 b4 f5 00 00 00 10\s+vcvtneebf162ps 0x1000000= 0\(%rbp,%r14,8\),%ymm6 > +\s*[a-f0-9]+:\s*c4 c2 7e b0 31\s+vcvtneebf162ps \(%r9\),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7e b0 b1 e0 0f 00 00\s+vcvtneebf162ps 0xfe0\(%rcx\= ),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7e b0 b2 00 f0 ff ff\s+vcvtneebf162ps -0x1000\(%rd= x\),%ymm6 > +\s*[a-f0-9]+:\s*c4 a2 79 b0 b4 f5 00 00 00 10\s+vcvtneeph2ps 0x10000000\= (%rbp,%r14,8\),%xmm6 > +\s*[a-f0-9]+:\s*c4 c2 79 b0 31\s+vcvtneeph2ps \(%r9\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 79 b0 b1 f0 07 00 00\s+vcvtneeph2ps 0x7f0\(%rcx\),= %xmm6 > +\s*[a-f0-9]+:\s*c4 e2 79 b0 b2 00 f8 ff ff\s+vcvtneeph2ps -0x800\(%rdx\)= ,%xmm6 > +\s*[a-f0-9]+:\s*c4 a2 7d b0 b4 f5 00 00 00 10\s+vcvtneeph2ps 0x10000000\= (%rbp,%r14,8\),%ymm6 > +\s*[a-f0-9]+:\s*c4 c2 7d b0 31\s+vcvtneeph2ps \(%r9\),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7d b0 b1 e0 0f 00 00\s+vcvtneeph2ps 0xfe0\(%rcx\),= %ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7d b0 b2 00 f0 ff ff\s+vcvtneeph2ps -0x1000\(%rdx\= ),%ymm6 > +\s*[a-f0-9]+:\s*c4 a2 7b b0 b4 f5 00 00 00 10\s+vcvtneobf162ps 0x1000000= 0\(%rbp,%r14,8\),%xmm6 > +\s*[a-f0-9]+:\s*c4 c2 7b b0 31\s+vcvtneobf162ps \(%r9\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7b b0 b1 f0 07 00 00\s+vcvtneobf162ps 0x7f0\(%rcx\= ),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7b b0 b2 00 f8 ff ff\s+vcvtneobf162ps -0x800\(%rdx= \),%xmm6 > +\s*[a-f0-9]+:\s*c4 a2 7f b0 b4 f5 00 00 00 10\s+vcvtneobf162ps 0x1000000= 0\(%rbp,%r14,8\),%ymm6 > +\s*[a-f0-9]+:\s*c4 c2 7f b0 31\s+vcvtneobf162ps \(%r9\),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7f b0 b1 e0 0f 00 00\s+vcvtneobf162ps 0xfe0\(%rcx\= ),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7f b0 b2 00 f0 ff ff\s+vcvtneobf162ps -0x1000\(%rd= x\),%ymm6 > +\s*[a-f0-9]+:\s*c4 a2 78 b0 b4 f5 00 00 00 10\s+vcvtneoph2ps 0x10000000\= (%rbp,%r14,8\),%xmm6 > +\s*[a-f0-9]+:\s*c4 c2 78 b0 31\s+vcvtneoph2ps \(%r9\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 78 b0 b1 f0 07 00 00\s+vcvtneoph2ps 0x7f0\(%rcx\),= %xmm6 > +\s*[a-f0-9]+:\s*c4 e2 78 b0 b2 00 f8 ff ff\s+vcvtneoph2ps -0x800\(%rdx\)= ,%xmm6 > +\s*[a-f0-9]+:\s*c4 a2 7c b0 b4 f5 00 00 00 10\s+vcvtneoph2ps 0x10000000\= (%rbp,%r14,8\),%ymm6 > +\s*[a-f0-9]+:\s*c4 c2 7c b0 31\s+vcvtneoph2ps \(%r9\),%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7c b0 b1 e0 0f 00 00\s+vcvtneoph2ps 0xfe0\(%rcx\),= %ymm6 > +\s*[a-f0-9]+:\s*c4 e2 7c b0 b2 00 f0 ff ff\s+vcvtneoph2ps -0x1000\(%rdx\= ),%ymm6 > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 f5\s+vcvtneps2bf16 %xmm5,%xmm6 > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 f5\s+vcvtneps2bf16 %xmm5,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7a 72 f5\s+\{vex\} vcvtneps2bf16 %xmm5,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7a 72 f5\s+\{vex\} vcvtneps2bf16 %xmm5,%xmm6 > +\s*[a-f0-9]+:\s*62 f2 7e 28 72 f5\s+vcvtneps2bf16 %ymm5,%xmm6 > +\s*[a-f0-9]+:\s*62 f2 7e 28 72 f5\s+vcvtneps2bf16 %ymm5,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7e 72 f5\s+\{vex\} vcvtneps2bf16 %ymm5,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7e 72 f5\s+\{vex\} vcvtneps2bf16 %ymm5,%xmm6 > +\s*[a-f0-9]+:\s*62 b2 7e 08 72 b4 f5 00 00 00 10\s+vcvtneps2bf16x 0x1000= 0000\(%rbp,%r14,8\),%xmm6 > +\s*[a-f0-9]+:\s*62 b2 7e 08 72 b4 f5 00 00 00 10\s+vcvtneps2bf16x 0x1000= 0000\(%rbp,%r14,8\),%xmm6 > +\s*[a-f0-9]+:\s*c4 a2 7a 72 b4 f5 00 00 00 10\s+\{vex\} vcvtneps2bf16x 0= x10000000\(%rbp,%r14,8\),%xmm6 > +\s*[a-f0-9]+:\s*c4 a2 7a 72 b4 f5 00 00 00 10\s+\{vex\} vcvtneps2bf16x 0= x10000000\(%rbp,%r14,8\),%xmm6 > +\s*[a-f0-9]+:\s*62 d2 7e 08 72 31\s+vcvtneps2bf16x \(%r9\),%xmm6 > +\s*[a-f0-9]+:\s*62 d2 7e 08 72 31\s+vcvtneps2bf16x \(%r9\),%xmm6 > +\s*[a-f0-9]+:\s*c4 c2 7a 72 31\s+\{vex\} vcvtneps2bf16x \(%r9\),%xmm6 > +\s*[a-f0-9]+:\s*c4 c2 7a 72 31\s+\{vex\} vcvtneps2bf16x \(%r9\),%xmm6 > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 71 7f\s+vcvtneps2bf16x 0x7f0\(%rcx\),%xmm= 6 > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 71 7f\s+vcvtneps2bf16x 0x7f0\(%rcx\),%xmm= 6 > +\s*[a-f0-9]+:\s*c4 e2 7a 72 b1 f0 07 00 00\s+\{vex\} vcvtneps2bf16x 0x7f= 0\(%rcx\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7a 72 b1 f0 07 00 00\s+\{vex\} vcvtneps2bf16x 0x7f= 0\(%rcx\),%xmm6 > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 72 80\s+vcvtneps2bf16x -0x800\(%rdx\),%xm= m6 > +\s*[a-f0-9]+:\s*62 f2 7e 08 72 72 80\s+vcvtneps2bf16x -0x800\(%rdx\),%xm= m6 > +\s*[a-f0-9]+:\s*c4 e2 7a 72 b2 00 f8 ff ff\s+\{vex\} vcvtneps2bf16x -0x8= 00\(%rdx\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7a 72 b2 00 f8 ff ff\s+\{vex\} vcvtneps2bf16x -0x8= 00\(%rdx\),%xmm6 > +\s*[a-f0-9]+:\s*62 f2 7e 28 72 71 7f\s+vcvtneps2bf16y 0xfe0\(%rcx\),%xmm= 6 > +\s*[a-f0-9]+:\s*62 f2 7e 28 72 71 7f\s+vcvtneps2bf16y 0xfe0\(%rcx\),%xmm= 6 > +\s*[a-f0-9]+:\s*c4 e2 7e 72 b1 e0 0f 00 00\s+\{vex\} vcvtneps2bf16y 0xfe= 0\(%rcx\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7e 72 b1 e0 0f 00 00\s+\{vex\} vcvtneps2bf16y 0xfe= 0\(%rcx\),%xmm6 > +\s*[a-f0-9]+:\s*62 f2 7e 28 72 72 80\s+vcvtneps2bf16y -0x1000\(%rdx\),%x= mm6 > +\s*[a-f0-9]+:\s*62 f2 7e 28 72 72 80\s+vcvtneps2bf16y -0x1000\(%rdx\),%x= mm6 > +\s*[a-f0-9]+:\s*c4 e2 7e 72 b2 00 f0 ff ff\s+\{vex\} vcvtneps2bf16y -0x1= 000\(%rdx\),%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 7e 72 b2 00 f0 ff ff\s+\{vex\} vcvtneps2bf16y -0x1= 000\(%rdx\),%xmm6 > diff --git a/gas/testsuite/gas/i386/x86-64-avx-ne-convert.s b/gas/testsui= te/gas/i386/x86-64-avx-ne-convert.s > new file mode 100644 > index 0000000000..c01a95d943 > --- /dev/null > +++ b/gas/testsuite/gas/i386/x86-64-avx-ne-convert.s > @@ -0,0 +1,167 @@ > +# Check 64bit AVX-NE-CONVERT instructions > + > + .allow_index_reg > + .text > +_start: > + vbcstnebf162ps 0x10000000(%rbp, %r14, 8), %xmm6 #AVX-NE-= CONVERT > + vbcstnebf162ps (%r9), %xmm6 #AVX-NE-CONVERT > + vbcstnebf162ps 254(%rcx), %xmm6 #AVX-NE-CONVERT Disp32(f= e000000) > + vbcstnebf162ps -256(%rdx), %xmm6 #AVX-NE-CONVERT Disp32(0= 0ffffff) > + vbcstnebf162ps 0x10000000(%rbp, %r14, 8), %ymm6 #AVX-NE-= CONVERT > + vbcstnebf162ps (%r9), %ymm6 #AVX-NE-CONVERT > + vbcstnebf162ps 254(%rcx), %ymm6 #AVX-NE-CONVERT Disp32(f= e000000) > + vbcstnebf162ps -256(%rdx), %ymm6 #AVX-NE-CONVERT Disp32(0= 0ffffff) > + vbcstnesh2ps 0x10000000(%rbp, %r14, 8), %xmm6 #AVX-NE-= CONVERT > + vbcstnesh2ps (%r9), %xmm6 #AVX-NE-CONVERT > + vbcstnesh2ps 254(%rcx), %xmm6 #AVX-NE-CONVERT Disp32(f= e000000) > + vbcstnesh2ps -256(%rdx), %xmm6 #AVX-NE-CONVERT Disp32(0= 0ffffff) > + vbcstnesh2ps 0x10000000(%rbp, %r14, 8), %ymm6 #AVX-NE-= CONVERT > + vbcstnesh2ps (%r9), %ymm6 #AVX-NE-CONVERT > + vbcstnesh2ps 254(%rcx), %ymm6 #AVX-NE-CONVERT Disp32(f= e000000) > + vbcstnesh2ps -256(%rdx), %ymm6 #AVX-NE-CONVERT Disp32(0= 0ffffff) > + vcvtneebf162ps 0x10000000(%rbp, %r14, 8), %xmm6 #AVX-NE-= CONVERT > + vcvtneebf162ps (%r9), %xmm6 #AVX-NE-CONVERT > + vcvtneebf162ps 2032(%rcx), %xmm6 #AVX-NE-CONVERT Disp32(f= 0070000) > + vcvtneebf162ps -2048(%rdx), %xmm6 #AVX-NE-CONVERT Disp32(0= 0f8ffff) > + vcvtneebf162ps 0x10000000(%rbp, %r14, 8), %ymm6 #AVX-NE-= CONVERT > + vcvtneebf162ps (%r9), %ymm6 #AVX-NE-CONVERT > + vcvtneebf162ps 4064(%rcx), %ymm6 #AVX-NE-CONVERT Disp32(e= 00f0000) > + vcvtneebf162ps -4096(%rdx), %ymm6 #AVX-NE-CONVERT Disp32(0= 0f0ffff) > + vcvtneeph2ps 0x10000000(%rbp, %r14, 8), %xmm6 #AVX-NE-= CONVERT > + vcvtneeph2ps (%r9), %xmm6 #AVX-NE-CONVERT > + vcvtneeph2ps 2032(%rcx), %xmm6 #AVX-NE-CONVERT Disp32(f= 0070000) > + vcvtneeph2ps -2048(%rdx), %xmm6 #AVX-NE-CONVERT Disp32(0= 0f8ffff) > + vcvtneeph2ps 0x10000000(%rbp, %r14, 8), %ymm6 #AVX-NE-= CONVERT > + vcvtneeph2ps (%r9), %ymm6 #AVX-NE-CONVERT > + vcvtneeph2ps 4064(%rcx), %ymm6 #AVX-NE-CONVERT Disp32(e= 00f0000) > + vcvtneeph2ps -4096(%rdx), %ymm6 #AVX-NE-CONVERT Disp32(0= 0f0ffff) > + vcvtneobf162ps 0x10000000(%rbp, %r14, 8), %xmm6 #AVX-NE-= CONVERT > + vcvtneobf162ps (%r9), %xmm6 #AVX-NE-CONVERT > + vcvtneobf162ps 2032(%rcx), %xmm6 #AVX-NE-CONVERT Disp32(f= 0070000) > + vcvtneobf162ps -2048(%rdx), %xmm6 #AVX-NE-CONVERT Disp32(0= 0f8ffff) > + vcvtneobf162ps 0x10000000(%rbp, %r14, 8), %ymm6 #AVX-NE-= CONVERT > + vcvtneobf162ps (%r9), %ymm6 #AVX-NE-CONVERT > + vcvtneobf162ps 4064(%rcx), %ymm6 #AVX-NE-CONVERT Disp32(e= 00f0000) > + vcvtneobf162ps -4096(%rdx), %ymm6 #AVX-NE-CONVERT Disp32(0= 0f0ffff) > + vcvtneoph2ps 0x10000000(%rbp, %r14, 8), %xmm6 #AVX-NE-= CONVERT > + vcvtneoph2ps (%r9), %xmm6 #AVX-NE-CONVERT > + vcvtneoph2ps 2032(%rcx), %xmm6 #AVX-NE-CONVERT Disp32(f= 0070000) > + vcvtneoph2ps -2048(%rdx), %xmm6 #AVX-NE-CONVERT Disp32(0= 0f8ffff) > + vcvtneoph2ps 0x10000000(%rbp, %r14, 8), %ymm6 #AVX-NE-= CONVERT > + vcvtneoph2ps (%r9), %ymm6 #AVX-NE-CONVERT > + vcvtneoph2ps 4064(%rcx), %ymm6 #AVX-NE-CONVERT Disp32(e= 00f0000) > + vcvtneoph2ps -4096(%rdx), %ymm6 #AVX-NE-CONVERT Disp32(0= 0f0ffff) > + vcvtneps2bf16 %xmm5, %xmm6 #AVX-NE-CONVERT > + {evex} vcvtneps2bf16 %xmm5, %xmm6 #AVX-NE-CONVERT > + {vex} vcvtneps2bf16 %xmm5, %xmm6 #AVX-NE-CONVERT > + {vex3} vcvtneps2bf16 %xmm5, %xmm6 #AVX-NE-CONVERT > + vcvtneps2bf16 %ymm5, %xmm6 #AVX-NE-CONVERT > + {evex} vcvtneps2bf16 %ymm5, %xmm6 #AVX-NE-CONVERT > + {vex} vcvtneps2bf16 %ymm5, %xmm6 #AVX-NE-CONVERT > + {vex3} vcvtneps2bf16 %ymm5, %xmm6 #AVX-NE-CONVERT > + vcvtneps2bf16x 0x10000000(%rbp, %r14, 8), %xmm6 #AVX-NE-= CONVERT > + {evex} vcvtneps2bf16x 0x10000000(%rbp, %r14, 8), %xmm6 = #AVX-NE-CONVERT > + {vex} vcvtneps2bf16x 0x10000000(%rbp, %r14, 8), %xmm6 = #AVX-NE-CONVERT > + {vex3} vcvtneps2bf16x 0x10000000(%rbp, %r14, 8), %xmm6 = #AVX-NE-CONVERT > + vcvtneps2bf16x (%r9), %xmm6 #AVX-NE-CONVERT > + {evex} vcvtneps2bf16x (%r9), %xmm6 #AVX-NE-CONVERT > + {vex} vcvtneps2bf16x (%r9), %xmm6 #AVX-NE-CONVERT > + {vex3} vcvtneps2bf16x (%r9), %xmm6 #AVX-NE-CONVERT > + vcvtneps2bf16x 2032(%rcx), %xmm6 #AVX-NE-CONVERT Disp32(f= 0070000) > + {evex} vcvtneps2bf16x 2032(%rcx), %xmm6 #AVX-NE-CONVERT = Disp32(f0070000) > + {vex} vcvtneps2bf16x 2032(%rcx), %xmm6 #AVX-NE-CONVERT = Disp32(f0070000) > + {vex3} vcvtneps2bf16x 2032(%rcx), %xmm6 #AVX-NE-CONVERT = Disp32(f0070000) > + vcvtneps2bf16x -2048(%rdx), %xmm6 #AVX-NE-CONVERT Disp32(0= 0f8ffff) > + {evex} vcvtneps2bf16x -2048(%rdx), %xmm6 #AVX-NE-CONVERT = Disp32(00f8ffff) > + {vex} vcvtneps2bf16x -2048(%rdx), %xmm6 #AVX-NE-CONVERT = Disp32(00f8ffff) > + {vex3} vcvtneps2bf16x -2048(%rdx), %xmm6 #AVX-NE-CONVERT = Disp32(00f8ffff) > + vcvtneps2bf16y 4064(%rcx), %xmm6 #AVX-NE-CONVERT Disp32(e= 00f0000) > + {evex} vcvtneps2bf16y 4064(%rcx), %xmm6 #AVX-NE-CONVERT = Disp32(e00f0000) > + {vex} vcvtneps2bf16y 4064(%rcx), %xmm6 #AVX-NE-CONVERT = Disp32(e00f0000) > + {vex3} vcvtneps2bf16y 4064(%rcx), %xmm6 #AVX-NE-CONVERT = Disp32(e00f0000) > + vcvtneps2bf16y -4096(%rdx), %xmm6 #AVX-NE-CONVERT Disp32(0= 0f0ffff) > + {evex} vcvtneps2bf16y -4096(%rdx), %xmm6 #AVX-NE-CONVERT = Disp32(00f0ffff) > + {vex} vcvtneps2bf16y -4096(%rdx), %xmm6 #AVX-NE-CONVERT = Disp32(00f0ffff) > + {vex3} vcvtneps2bf16y -4096(%rdx), %xmm6 #AVX-NE-CONVERT = Disp32(00f0ffff) > + > +.intel_syntax noprefix > + vbcstnebf162ps xmm6, WORD PTR [rbp+r14*8+0x10000000] #AVX-NE-= CONVERT > + vbcstnebf162ps xmm6, WORD PTR [r9] #AVX-NE-CONVERT > + vbcstnebf162ps xmm6, WORD PTR [rcx+254] #AVX-NE-CONVERT = Disp32(fe000000) > + vbcstnebf162ps xmm6, WORD PTR [rdx-256] #AVX-NE-CONVERT = Disp32(00ffffff) > + vbcstnebf162ps ymm6, WORD PTR [rbp+r14*8+0x10000000] #AVX-NE-= CONVERT > + vbcstnebf162ps ymm6, WORD PTR [r9] #AVX-NE-CONVERT > + vbcstnebf162ps ymm6, WORD PTR [rcx+254] #AVX-NE-CONVERT = Disp32(fe000000) > + vbcstnebf162ps ymm6, WORD PTR [rdx-256] #AVX-NE-CONVERT = Disp32(00ffffff) > + vbcstnesh2ps xmm6, WORD PTR [rbp+r14*8+0x10000000] #AVX-NE-= CONVERT > + vbcstnesh2ps xmm6, WORD PTR [r9] #AVX-NE-CONVERT > + vbcstnesh2ps xmm6, WORD PTR [rcx+254] #AVX-NE-CONVERT = Disp32(fe000000) > + vbcstnesh2ps xmm6, WORD PTR [rdx-256] #AVX-NE-CONVERT = Disp32(00ffffff) > + vbcstnesh2ps ymm6, WORD PTR [rbp+r14*8+0x10000000] #AVX-NE-= CONVERT > + vbcstnesh2ps ymm6, WORD PTR [r9] #AVX-NE-CONVERT > + vbcstnesh2ps ymm6, WORD PTR [rcx+254] #AVX-NE-CONVERT = Disp32(fe000000) > + vbcstnesh2ps ymm6, WORD PTR [rdx-256] #AVX-NE-CONVERT = Disp32(00ffffff) > + vcvtneebf162ps xmm6, XMMWORD PTR [rbp+r14*8+0x10000000] = #AVX-NE-CONVERT > + vcvtneebf162ps xmm6, XMMWORD PTR [r9] #AVX-NE-CONVERT > + vcvtneebf162ps xmm6, XMMWORD PTR [rcx+2032] #AVX-NE-CONVERT = Disp32(f0070000) > + vcvtneebf162ps xmm6, XMMWORD PTR [rdx-2048] #AVX-NE-CONVERT = Disp32(00f8ffff) > + vcvtneebf162ps ymm6, YMMWORD PTR [rbp+r14*8+0x10000000] = #AVX-NE-CONVERT > + vcvtneebf162ps ymm6, YMMWORD PTR [r9] #AVX-NE-CONVERT > + vcvtneebf162ps ymm6, YMMWORD PTR [rcx+4064] #AVX-NE-CONVERT = Disp32(e00f0000) > + vcvtneebf162ps ymm6, YMMWORD PTR [rdx-4096] #AVX-NE-CONVERT = Disp32(00f0ffff) > + vcvtneeph2ps xmm6, XMMWORD PTR [rbp+r14*8+0x10000000] = #AVX-NE-CONVERT > + vcvtneeph2ps xmm6, XMMWORD PTR [r9] #AVX-NE-CONVERT > + vcvtneeph2ps xmm6, XMMWORD PTR [rcx+2032] #AVX-NE-CONVERT = Disp32(f0070000) > + vcvtneeph2ps xmm6, XMMWORD PTR [rdx-2048] #AVX-NE-CONVERT = Disp32(00f8ffff) > + vcvtneeph2ps ymm6, YMMWORD PTR [rbp+r14*8+0x10000000] = #AVX-NE-CONVERT > + vcvtneeph2ps ymm6, YMMWORD PTR [r9] #AVX-NE-CONVERT > + vcvtneeph2ps ymm6, YMMWORD PTR [rcx+4064] #AVX-NE-CONVERT = Disp32(e00f0000) > + vcvtneeph2ps ymm6, YMMWORD PTR [rdx-4096] #AVX-NE-CONVERT = Disp32(00f0ffff) > + vcvtneobf162ps xmm6, XMMWORD PTR [rbp+r14*8+0x10000000] = #AVX-NE-CONVERT > + vcvtneobf162ps xmm6, XMMWORD PTR [r9] #AVX-NE-CONVERT > + vcvtneobf162ps xmm6, XMMWORD PTR [rcx+2032] #AVX-NE-CONVERT = Disp32(f0070000) > + vcvtneobf162ps xmm6, XMMWORD PTR [rdx-2048] #AVX-NE-CONVERT = Disp32(00f8ffff) > + vcvtneobf162ps ymm6, YMMWORD PTR [rbp+r14*8+0x10000000] = #AVX-NE-CONVERT > + vcvtneobf162ps ymm6, YMMWORD PTR [r9] #AVX-NE-CONVERT > + vcvtneobf162ps ymm6, YMMWORD PTR [rcx+4064] #AVX-NE-CONVERT = Disp32(e00f0000) > + vcvtneobf162ps ymm6, YMMWORD PTR [rdx-4096] #AVX-NE-CONVERT = Disp32(00f0ffff) > + vcvtneoph2ps xmm6, XMMWORD PTR [rbp+r14*8+0x10000000] = #AVX-NE-CONVERT > + vcvtneoph2ps xmm6, XMMWORD PTR [r9] #AVX-NE-CONVERT > + vcvtneoph2ps xmm6, XMMWORD PTR [rcx+2032] #AVX-NE-CONVERT = Disp32(f0070000) > + vcvtneoph2ps xmm6, XMMWORD PTR [rdx-2048] #AVX-NE-CONVERT = Disp32(00f8ffff) > + vcvtneoph2ps ymm6, YMMWORD PTR [rbp+r14*8+0x10000000] = #AVX-NE-CONVERT > + vcvtneoph2ps ymm6, YMMWORD PTR [r9] #AVX-NE-CONVERT > + vcvtneoph2ps ymm6, YMMWORD PTR [rcx+4064] #AVX-NE-CONVERT = Disp32(e00f0000) > + vcvtneoph2ps ymm6, YMMWORD PTR [rdx-4096] #AVX-NE-CONVERT = Disp32(00f0ffff) > + vcvtneps2bf16 xmm6, xmm5 #AVX-NE-CONVERT > + {evex} vcvtneps2bf16 xmm6, xmm5 #AVX-NE-CONVERT > + {vex} vcvtneps2bf16 xmm6, xmm5 #AVX-NE-CONVERT > + {vex3} vcvtneps2bf16 xmm6, xmm5 #AVX-NE-CONVERT > + vcvtneps2bf16 xmm6, ymm5 #AVX-NE-CONVERT > + {evex} vcvtneps2bf16 xmm6, ymm5 #AVX-NE-CONVERT > + {vex} vcvtneps2bf16 xmm6, ymm5 #AVX-NE-CONVERT > + {vex3} vcvtneps2bf16 xmm6, ymm5 #AVX-NE-CONVERT > + vcvtneps2bf16 xmm6, XMMWORD PTR [rbp+r14*8+0x10000000] = #AVX-NE-CONVERT > + {evex} vcvtneps2bf16 xmm6, XMMWORD PTR [rbp+r14*8+0x10000000] = #AVX-NE-CONVERT > + {vex} vcvtneps2bf16 xmm6, XMMWORD PTR [rbp+r14*8+0x10000000] = #AVX-NE-CONVERT > + {vex3} vcvtneps2bf16 xmm6, XMMWORD PTR [rbp+r14*8+0x10000000] = #AVX-NE-CONVERT > + vcvtneps2bf16 xmm6, XMMWORD PTR [r9] #AVX-NE-CONVERT > + {evex} vcvtneps2bf16 xmm6, XMMWORD PTR [r9] #AVX-NE-CONVERT > + {vex} vcvtneps2bf16 xmm6, XMMWORD PTR [r9] #AVX-NE-CONVERT > + {vex3} vcvtneps2bf16 xmm6, XMMWORD PTR [r9] #AVX-NE-CONVERT > + vcvtneps2bf16 xmm6, XMMWORD PTR [rcx+2032] #AVX-NE-CONVERT = Disp32(f0070000) > + {evex} vcvtneps2bf16 xmm6, XMMWORD PTR [rcx+2032] #AVX-NE-= CONVERT Disp32(f0070000) > + {vex} vcvtneps2bf16 xmm6, XMMWORD PTR [rcx+2032] #AVX-NE-= CONVERT Disp32(f0070000) > + {vex3} vcvtneps2bf16 xmm6, XMMWORD PTR [rcx+2032] #AVX-NE-= CONVERT Disp32(f0070000) > + vcvtneps2bf16 xmm6, XMMWORD PTR [rdx-2048] #AVX-NE-CONVERT = Disp32(00f8ffff) > + {evex} vcvtneps2bf16 xmm6, XMMWORD PTR [rdx-2048] #AVX-NE-= CONVERT Disp32(00f8ffff) > + {vex} vcvtneps2bf16 xmm6, XMMWORD PTR [rdx-2048] #AVX-NE-= CONVERT Disp32(00f8ffff) > + {vex3} vcvtneps2bf16 xmm6, XMMWORD PTR [rdx-2048] #AVX-NE-= CONVERT Disp32(00f8ffff) > + vcvtneps2bf16 xmm6, YMMWORD PTR [rcx+4064] #AVX-NE-CONVERT = Disp32(e00f0000) > + {evex} vcvtneps2bf16 xmm6, YMMWORD PTR [rcx+4064] #AVX-NE-= CONVERT Disp32(e00f0000) > + {vex} vcvtneps2bf16 xmm6, YMMWORD PTR [rcx+4064] #AVX-NE-= CONVERT Disp32(e00f0000) > + {vex3} vcvtneps2bf16 xmm6, YMMWORD PTR [rcx+4064] #AVX-NE-= CONVERT Disp32(e00f0000) > + vcvtneps2bf16 xmm6, YMMWORD PTR [rdx-4096] #AVX-NE-CONVERT = Disp32(00f0ffff) > + {evex} vcvtneps2bf16 xmm6, YMMWORD PTR [rdx-4096] #AVX-NE-= CONVERT Disp32(00f0ffff) > + {vex} vcvtneps2bf16 xmm6, YMMWORD PTR [rdx-4096] #AVX-NE-= CONVERT Disp32(00f0ffff) > + {vex3} vcvtneps2bf16 xmm6, YMMWORD PTR [rdx-4096] #AVX-NE-= CONVERT Disp32(00f0ffff) > diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c > index 61cef0c86a..f0638a3193 100644 > --- a/opcodes/i386-dis.c > +++ b/opcodes/i386-dis.c > @@ -373,6 +373,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *= addr) > #define Mq { OP_M, q_mode } > #define Mv { OP_M, v_mode } > #define Mv_bnd { OP_M, v_bndmk_mode } > +#define Mw { OP_M, w_mode } > #define Mx { OP_M, x_mode } > #define Mxmm { OP_M, xmm_mode } > #define Gb { OP_G, b_mode } > @@ -1140,6 +1141,9 @@ enum > PREFIX_VEX_0F3851_W_0, > PREFIX_VEX_0F385C_X86_64, > PREFIX_VEX_0F385E_X86_64, > + PREFIX_VEX_0F3872, > + PREFIX_VEX_0F38B0_W_0, > + PREFIX_VEX_0F38B1_W_0, > PREFIX_VEX_0F38F5_L_0, > PREFIX_VEX_0F38F6_L_0, > PREFIX_VEX_0F38F7_L_0, > @@ -1556,8 +1560,11 @@ enum > VEX_W_0F385E_X86_64_P_1, > VEX_W_0F385E_X86_64_P_2, > VEX_W_0F385E_X86_64_P_3, > + VEX_W_0F3872_P_1, > VEX_W_0F3878, > VEX_W_0F3879, > + VEX_W_0F38B0, > + VEX_W_0F38B1, > VEX_W_0F38B4, > VEX_W_0F38B5, > VEX_W_0F38CF, > @@ -4093,6 +4100,27 @@ static const struct dis386 prefix_table[][4] =3D { > { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3) }, > }, > > + /* PREFIX_VEX_0F3872 */ > + { > + { Bad_Opcode }, > + { VEX_W_TABLE (VEX_W_0F3872_P_1) }, > + }, > + > + /* PREFIX_VEX_0F38B0_W_0 */ > + { > + { "vcvtneoph2ps", { XM, Mx }, 0 }, > + { "vcvtneebf162ps", { XM, Mx }, 0 }, > + { "vcvtneeph2ps", { XM, Mx }, 0 }, > + { "vcvtneobf162ps", { XM, Mx }, 0 }, > + }, > + > + /* PREFIX_VEX_0F38B1_W_0 */ > + { > + { Bad_Opcode }, > + { "vbcstnebf162ps", { XM, Mw }, 0 }, > + { "vbcstnesh2ps", { XM, Mw }, 0 }, > + }, > + > /* PREFIX_VEX_0F38F5_L_0 */ > { > { "bzhiS", { Gdq, Edq, VexGdq }, 0 }, > @@ -6415,7 +6443,7 @@ static const struct dis386 vex_table[][256] =3D { > /* 70 */ > { Bad_Opcode }, > { Bad_Opcode }, > - { Bad_Opcode }, > + { PREFIX_TABLE (PREFIX_VEX_0F3872) }, > { Bad_Opcode }, > { Bad_Opcode }, > { Bad_Opcode }, > @@ -6485,8 +6513,8 @@ static const struct dis386 vex_table[][256] =3D { > { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA }, > { "vfnmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA }, > /* b0 */ > - { Bad_Opcode }, > - { Bad_Opcode }, > + { VEX_W_TABLE (VEX_W_0F38B0) }, > + { VEX_W_TABLE (VEX_W_0F38B1) }, > { Bad_Opcode }, > { Bad_Opcode }, > { VEX_W_TABLE (VEX_W_0F38B4) }, > @@ -7796,6 +7824,10 @@ static const struct dis386 vex_w_table[][2] =3D { > /* VEX_W_0F385E_X86_64_P_3 */ > { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0) }, > }, > + { > + /* VEX_W_0F3872_P_1 */ > + { "%XVvcvtneps2bf16%XY", { XMM, EXx }, 0 }, > + }, > { > /* VEX_W_0F3878 */ > { "%XEvpbroadcastb", { XM, EXb }, PREFIX_DATA }, > @@ -7804,6 +7836,14 @@ static const struct dis386 vex_w_table[][2] =3D { > /* VEX_W_0F3879 */ > { "%XEvpbroadcastw", { XM, EXw }, PREFIX_DATA }, > }, > + { > + /* VEX_W_0F38B0 */ > + { PREFIX_TABLE (PREFIX_VEX_0F38B0_W_0) }, > + }, > + { > + /* VEX_W_0F38B1 */ > + { PREFIX_TABLE (PREFIX_VEX_0F38B1_W_0) }, > + }, > { > /* VEX_W_0F38B4 */ > { Bad_Opcode }, > diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c > index e9b5ba078f..6e723681df 100644 > --- a/opcodes/i386-gen.c > +++ b/opcodes/i386-gen.c > @@ -257,6 +257,8 @@ static initializer cpu_flag_init[] =3D > "CpuWRMSRNS" }, > { "CPU_MSRLIST_FLAGS", > "CpuMSRLIST" }, > + { "CPU_AVX_NE_CONVERT_FLAGS", > + "CPU_AVX2_FLAGS|CpuAVX_NE_CONVERT" }, > { "CPU_IAMCU_FLAGS", > "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" }, > { "CPU_ADX_FLAGS", > @@ -384,7 +386,7 @@ static initializer cpu_flag_init[] =3D > { "CPU_ANY_AVX_FLAGS", > "CPU_ANY_AVX2_FLAGS|CpuF16C|CpuFMA|CpuFMA4|CpuXOP|CpuAVX" }, > { "CPU_ANY_AVX2_FLAGS", > - "CPU_ANY_AVX512F_FLAGS|CpuAVX2|CpuAVX_VNNI|CpuAVX_IFMA|CpuAVX_VNNI_I= NT8" }, > + "CPU_ANY_AVX512F_FLAGS|CpuAVX2|CpuAVX_VNNI|CpuAVX_IFMA|CpuAVX_VNNI_I= NT8|CpuAVX_NE_CONVERT" }, > { "CPU_ANY_AVX512F_FLAGS", > "CpuAVX512F|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF|CpuAVX512DQ|CPU_ANY_= AVX512BW_FLAGS|CpuAVX512VL|CpuAVX512IFMA|CpuAVX512VBMI|CpuAVX512_4FMAPS|Cpu= AVX512_4VNNIW|CpuAVX512_VPOPCNTDQ|CpuAVX512_VBMI2|CpuAVX512_VNNI|CpuAVX512_= BITALG|CpuAVX512_BF16|CpuAVX512_VP2INTERSECT" }, > { "CPU_ANY_AVX512CD_FLAGS", > @@ -463,6 +465,8 @@ static initializer cpu_flag_init[] =3D > "CpuWRMSRNS" }, > { "CPU_ANY_MSRLIST_FLAGS", > "CpuMSRLIST" }, > + { "CPU_ANY_AVX_NE_CONVERT_FLAGS", > + "CpuAVX_NE_CONVERT" }, > }; > > static initializer operand_type_init[] =3D > @@ -668,6 +672,7 @@ static bitfield cpu_flags[] =3D > BITFIELD (CpuCMPCCXADD), > BITFIELD (CpuWRMSRNS), > BITFIELD (CpuMSRLIST), > + BITFIELD (CpuAVX_NE_CONVERT), > BITFIELD (CpuMWAITX), > BITFIELD (CpuCLZERO), > BITFIELD (CpuOSPKE), > diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h > index a409b10ca1..78fc019c3c 100644 > --- a/opcodes/i386-opc.h > +++ b/opcodes/i386-opc.h > @@ -221,6 +221,8 @@ enum > CpuWRMSRNS, > /* Intel MSRLIST Instructions support required. */ > CpuMSRLIST, > + /* Intel AVX NE CONVERT Instructions support required. */ > + CpuAVX_NE_CONVERT, > /* mwaitx instruction required */ > CpuMWAITX, > /* Clzero instruction required */ > @@ -408,6 +410,7 @@ typedef union i386_cpu_flags > unsigned int cpucmpccxadd:1; > unsigned int cpuwrmsrns:1; > unsigned int cpumsrlist:1; > + unsigned int cpuavx_ne_convert:1; > unsigned int cpumwaitx:1; > unsigned int cpuclzero:1; > unsigned int cpuospke:1; > diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl > index 3238c4fc2e..00a6d42b8e 100644 > --- a/opcodes/i386-opc.tbl > +++ b/opcodes/i386-opc.tbl > @@ -3056,6 +3056,18 @@ vdpbf16ps, 0xf352, None, CpuAVX512_BF16, Modrm|Spa= ce0F38|VexVVVV|Masking=3D3|VexW0 > > // AVX512_BF16 instructions end. > > +// AVX-NE-CONVERT instructions. > + > +vbcstnebf162ps, 0xf3b1, None, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|Vex= W0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|Bas= eIndex, RegXMM|RegYMM } > +vbcstnesh2ps, 0x66b1, None, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0= |No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseI= ndex, RegXMM|RegYMM } > +vcvtneebf162ps, 0xf3b0, None, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|Vex= W0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword= |Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM } > +vcvtneeph2ps, 0x66b0, None, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0= |CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Y= mmword|Unspecified|BaseIndex, RegXMM|RegYMM } > +vcvtneobf162ps, 0xf2b0, None, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|Vex= W0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword= |Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM } > +vcvtneoph2ps, 0xb0, None, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|C= heckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Ymm= word|Unspecified|BaseIndex, RegXMM|RegYMM } > +vcvtneps2bf16, 0xf372, None, CpuAVX_NE_CONVERT, Modrm||Spa= ce0F38|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|,= { , RegXMM } > + > +// AVX-NE-CONVERT instructions end. > + > // ENQCMD instructions. > > enqcmd, 0xf20f38f8, None, CpuENQCMD, Modrm|AddrPrefixOpReg, { Unspecifie= d|BaseIndex, Reg16|Reg32|Reg64 } > -- > 2.27.0 > > Thanks, > Lingling OK. Thanks. --=20 H.J.