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From: "H.J. Lu" <hjl.tools@gmail.com>
Date: Mon, 13 Feb 2023 09:40:30 -0800
Message-ID: <CAMe9rOqKDPKW-cwpCqq6iqSSivoYzfXnSnKyf82bTPWCqouzpQ@mail.gmail.com>
Subject: Re: [PATCH 4/4] x86: MONITOR/MWAIT are not SSE3 insns
To: Jan Beulich <jbeulich@suse.com>
Cc: Binutils <binutils@sourceware.org>
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On Mon, Feb 13, 2023 at 12:08 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 10.02.2023 18:02, H.J. Lu wrote:
> > Since they used to be in SSE3, should they be also allowed with SSE3?
>
> In order to answer the question, can you please clarify what you mean
> by "used to be in SSE3"? I'm not aware of a spec ever marking them as
> SSE3 insns. And not allowing their use in e.g. generic32+sse3 is one
> of the purposes of this change, because that was simply wrong.
>

I checked 2005 Intel SDM which has a separate CPUID bit for MONITOR/MWAIT.
No need for SSE3 then.

Thanks.

-- 
H.J.