From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by sourceware.org (Postfix) with ESMTPS id 543D8385115B for ; Fri, 28 Oct 2022 15:54:45 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 543D8385115B Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-lf1-x12e.google.com with SMTP id j16so8951447lfe.12 for ; Fri, 28 Oct 2022 08:54:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=TAShhThM5M5vjRtHNpYiey4a49QmpvfudwgX8CKKvYc=; b=YUBD2lyEaIq2+p2mHNWhH1/vptTrcWi42vHM6Fq12fz1KiI0xU4owg1BQ4HNWwZ63x oYlghD8hRY+dNT++ikY5bUyQ2Bl/bI+DSOs276ibuHwwyWpIf+pD8a1z4q7sOXRKcWqT 5KGQdO8D3+aDjS3kODEK56NccNpQyPiiwD9nMqyR7XN91dp1jPuRTaEp6Cx4SKhGkvvh McWsSSw3XadU5BqBfr8NEAov6nNDBNuOoVNqpHSemiK+kS2XaaiexZuysbZF+GQkuJa5 Io5f2RC59Eq2rgUGkWUbmKUvMPhKj+vjDF87tulAZiIDvkTVVd72nb71YeB+UIKVWW5U Rrqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=TAShhThM5M5vjRtHNpYiey4a49QmpvfudwgX8CKKvYc=; b=KhuvaWxx2cEIxWd2Ue0cIWhWoIurtj92drtZ3QJNRFUsm4bTyRMfQbIPhALCLT4Uix sWhYQmc5CWprbmN+hOCUgn3OtLhvsfWdTMToRelIV37ZW0EbKFkl1zpQ42R2y9x/WFYy zfapI+NZ912vEG5okfDnc+N0pWc+iHutfJq/tqURRVUkWG8gc8UP40m0zzXANx3BDIwO Kow25EYCTrkTR1PzMxCmcBiZ43Wwg+zdnJN+5FfsH7kd7kqvtm5LFSfrl4uPRatW5h5H fU9q8xUPH2KJ9kWIj/l9EcOGXiJ8C7XFihGYzRy+xzIcor8D14/+7FUerVKERlAyf9kq W68A== X-Gm-Message-State: ACrzQf2uwy4O1gwqbeuzlqlbGItdp9F54kPWpuqsQh6ZK4hhII/jW4Se GNKtR9PhiGbtZIe9lwBnRhs2yEh25pQVkWfQ2Q8= X-Google-Smtp-Source: AMsMyM4+TkPrF8sCEmqvHUZPwbFd9uUeN/FDYJGyY5tK+ijiNd+W2/o9lPofpa7O+D3UR1SMgSPw/vXBmwUGUPuAuOs= X-Received: by 2002:ac2:490e:0:b0:4af:e549:26b with SMTP id n14-20020ac2490e000000b004afe549026bmr10138lfi.250.1666972483651; Fri, 28 Oct 2022 08:54:43 -0700 (PDT) MIME-Version: 1.0 References: <20221014091248.4920-1-haochen.jiang@intel.com> <20221014091248.4920-11-haochen.jiang@intel.com> <0aa4d551-e9ab-5e09-4f94-c672b7724915@suse.com> <9f7cfcd0-36aa-91d0-dfd6-462b69c41ac7@suse.com> In-Reply-To: From: "H.J. Lu" Date: Fri, 28 Oct 2022 08:54:07 -0700 Message-ID: Subject: Re: [PATCH 10/10] Support Intel PREFETCHI To: "Cui, Lili" Cc: "Beulich, Jan" , "binutils@sourceware.org" , "Jiang, Haochen" Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-3022.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Thu, Oct 27, 2022 at 12:01 AM Cui, Lili wrote: > > > > - /* Update operand types and check extended states. */ > > > + /* 1. Update operand types and check extended states. > > > + 2. Check IP-relative addressing for prefetchi. */ > > > for (j = 0; j < i.operands; j++) > > > { > > > + /* Check if IP-relative addressing requirements can be satisfied. */ > > > + if (i.tm.cpu_flags.bitfield.cpuprefetchi > > > + && !(i.base_reg && i.base_reg->reg_num == RegIP)) > > > + as_warn (_("only support RIP-relative address")); > > > > One final suggestion: > > > > as_warn (_("`%s' only supports RIP-relative address"), i.tm.name); > > > Done. > > > And maybe also keep code and comment in sync as to the sequence of > > things done. > > > Changed, thanks Jan. > > > Jan > > > gas/ChangeLog: > > * NEWS: Add support for Intel PREFETCHI instruction. > * config/tc-i386.c (load_insn_p): Use prefetch* to fold all prefetches. > (md_assemble): Add warning for illegal input of PREFETCHI. > * doc/c-i386.texi: Document .prefetchi. > * testsuite/gas/i386/i386.exp: Run PREFETCHI tests. > * testsuite/gas/i386/x86-64-lfence-load.d: Add PREFETCHI. > * testsuite/gas/i386/x86-64-lfence-load.s: Likewise. > * testsuite/gas/i386/x86-64-prefetch.d: New test. > * testsuite/gas/i386/x86-64-prefetchi-intel.d: Likewise. > * testsuite/gas/i386/x86-64-prefetchi-inval-register.d: Likewise.. > * testsuite/gas/i386/x86-64-prefetchi-inval-register.s: Likewise. > * testsuite/gas/i386/x86-64-prefetchi-warn.l: Likewise. > * testsuite/gas/i386/x86-64-prefetchi-warn.s: Likewise. > * testsuite/gas/i386/x86-64-prefetchi.d: Likewise. > * testsuite/gas/i386/x86-64-prefetchi.s: Likewise. > > opcodes/ChangeLog: > > * i386-dis.c (reg_table): Add MOD_0F18_REG_6 and MOD_0F18_REG_7 > (x86_64_table): Add X86_64_0F18_REG_6_MOD_0 and X86_64_0F18_REG_7_MOD_0. > (mod_table): Add MOD_0F18_REG_6 and MOD_0F18_REG_7. > (prefix_table): Add PREFIX_0F18_REG_6_MOD_0_X86_64 and > PREFIX_0F18_REG_7_MOD_0_X86_64. > (PREFETCHI_Fixup): New. > * i386-gen.c (cpu_flag_init): Add CPU_PREFETCHI_FLAGS. > (cpu_flags): Add CpuPREFETCHI. > * i386-opc.h (CpuPREFETCHI): New. > (i386_cpu_flags): Add cpuprefetchi. > * i386-opc.tbl: Add Intel PREFETCHI instructions. > * i386-init.h: Regenerated. > * i386-tbl.h: Likewise. > --- > gas/NEWS | 2 + > gas/config/tc-i386.c | 14 +++- > gas/doc/c-i386.texi | 3 +- > gas/testsuite/gas/i386/i386.exp | 4 + > gas/testsuite/gas/i386/x86-64-lfence-load.d | 2 + > gas/testsuite/gas/i386/x86-64-lfence-load.s | 2 + > .../gas/i386/x86-64-prefetchi-intel.d | 16 ++++ > .../i386/x86-64-prefetchi-inval-register.d | 13 ++++ > .../i386/x86-64-prefetchi-inval-register.s | 9 +++ > .../gas/i386/x86-64-prefetchi-warn.l | 5 ++ > .../gas/i386/x86-64-prefetchi-warn.s | 11 +++ > gas/testsuite/gas/i386/x86-64-prefetchi.d | 15 ++++ > gas/testsuite/gas/i386/x86-64-prefetchi.s | 14 ++++ > opcodes/i386-dis.c | 78 ++++++++++++++++++- > opcodes/i386-gen.c | 3 + > opcodes/i386-opc.h | 3 + > opcodes/i386-opc.tbl | 7 ++ > 17 files changed, 194 insertions(+), 7 deletions(-) > create mode 100644 gas/testsuite/gas/i386/x86-64-prefetchi-intel.d > create mode 100644 gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.d > create mode 100644 gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.s > create mode 100644 gas/testsuite/gas/i386/x86-64-prefetchi-warn.l > create mode 100644 gas/testsuite/gas/i386/x86-64-prefetchi-warn.s > create mode 100644 gas/testsuite/gas/i386/x86-64-prefetchi.d > create mode 100644 gas/testsuite/gas/i386/x86-64-prefetchi.s > > diff --git a/gas/NEWS b/gas/NEWS > index 961449545d..5eb479f5a1 100644 > --- a/gas/NEWS > +++ b/gas/NEWS > @@ -1,5 +1,7 @@ > -*- text -*- > > +* Add support for Intel PREFETCHI instructions. > + > * Add support for Intel AMX-FP16 instructions. > > * Add support for Intel MSRLIST instructions. > diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c > index c1623f216e..52993dfbd9 100644 > --- a/gas/config/tc-i386.c > +++ b/gas/config/tc-i386.c > @@ -1102,6 +1102,7 @@ static const arch_entry cpu_arch[] = > SUBARCH (rao_int, RAO_INT, RAO_INT, false), > SUBARCH (wrmsrns, WRMSRNS, WRMSRNS, false), > SUBARCH (msrlist, MSRLIST, MSRLIST, false), > + SUBARCH (prefetchi, PREFETCHI, PREFETCHI, false), > }; > > #undef SUBARCH > @@ -4520,9 +4521,8 @@ load_insn_p (void) > > if (!any_vex_p) > { > - /* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0, > - prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn, > - bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote. */ > + /* Anysize insns: lea, invlpg, clflush, prefetch*, bndmk, bndcl, bndcu, > + bndcn, bndstx, bndldx, clflushopt, clwb, cldemote. */ > if (i.tm.opcode_modifier.anysize) > return 0; > > @@ -5057,9 +5057,15 @@ md_assemble (char *line) > if (!process_suffix ()) > return; > > - /* Update operand types and check extended states. */ > + /* 1. Check IP-relative addressing for prefetchi. > + 2. Update operand types and check extended states. */ > for (j = 0; j < i.operands; j++) > { > + /* Check if IP-relative addressing requirements can be satisfied. */ > + if (i.tm.cpu_flags.bitfield.cpuprefetchi > + && !(i.base_reg && i.base_reg->reg_num == RegIP)) > + as_warn (_("only support RIP-relative address"), i.tm.name); Please move this check before the loop. OK with this change. > i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]); > switch (i.tm.operand_types[j].bitfield.class) > { > diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi > index b33f17c698..fae902c034 100644 > --- a/gas/doc/c-i386.texi > +++ b/gas/doc/c-i386.texi > @@ -201,6 +201,7 @@ accept various extension mnemonics. For example, > @code{rao_int}, > @code{wrmsrns}, > @code{msrlist}, > +@code{prefetchi}, > @code{amx_int8}, > @code{amx_bf16}, > @code{amx_fp16}, > @@ -1496,7 +1497,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are: > @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt} > @item @samp{.avx_ifma} @tab @samp{.avx_vnni_int8} @tab @samp{.avx_ne_convert} > @item @samp{.cmpccxadd} @tab @samp{.rao_int} @tab @samp{.wrmsrns} > -@item @samp{.msrlist} > +@item @samp{.msrlist} @tab @samp{.prefetchi} > @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote} > @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq} > @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk} > diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp > index 9f5fa7f612..2081339dc9 100644 > --- a/gas/testsuite/gas/i386/i386.exp > +++ b/gas/testsuite/gas/i386/i386.exp > @@ -1209,6 +1209,10 @@ if [gas_64_check] then { > run_dump_test "x86-64-tdx" > run_dump_test "x86-64-tsxldtrk" > run_dump_test "x86-64-hreset" > + run_dump_test "x86-64-prefetchi" > + run_dump_test "x86-64-prefetchi-intel" > + run_dump_test "x86-64-prefetchi-inval-register" > + run_list_test "x86-64-prefetchi-warn" > run_dump_test "x86-64-vp2intersect" > run_dump_test "x86-64-vp2intersect-intel" > run_list_test "x86-64-vp2intersect-inval-bcast" > diff --git a/gas/testsuite/gas/i386/x86-64-lfence-load.d b/gas/testsuite/gas/i386/x86-64-lfence-load.d > index 2af86fc93f..17c3b9f286 100644 > --- a/gas/testsuite/gas/i386/x86-64-lfence-load.d > +++ b/gas/testsuite/gas/i386/x86-64-lfence-load.d > @@ -33,6 +33,8 @@ Disassembly of section .text: > +[a-f0-9]+: 0f 18 55 00 prefetcht1 0x0\(%rbp\) > +[a-f0-9]+: 0f 18 5d 00 prefetcht2 0x0\(%rbp\) > +[a-f0-9]+: 0f 0d 4d 00 prefetchw 0x0\(%rbp\) > + +[a-f0-9]+: 0f 18 3d 78 56 34 12 prefetchit0 0x12345678\(%rip\) # [0-9a-f]+ <_start\+0x[0-9a-f]+> > + +[a-f0-9]+: 0f 18 35 78 56 34 12 prefetchit1 0x12345678\(%rip\) # [0-9a-f]+ <_start\+0x[0-9a-f]+> > +[a-f0-9]+: 0f a1 pop %fs > +[a-f0-9]+: 0f ae e8 lfence > +[a-f0-9]+: 9d popf > diff --git a/gas/testsuite/gas/i386/x86-64-lfence-load.s b/gas/testsuite/gas/i386/x86-64-lfence-load.s > index 2a3ac6b7d2..c478082416 100644 > --- a/gas/testsuite/gas/i386/x86-64-lfence-load.s > +++ b/gas/testsuite/gas/i386/x86-64-lfence-load.s > @@ -20,6 +20,8 @@ _start: > prefetcht1 (%rbp) > prefetcht2 (%rbp) > prefetchw (%rbp) > + prefetchit0 0x12345678(%rip) > + prefetchit1 0x12345678(%rip) > pop %fs > popf > xlatb (%rbx) > diff --git a/gas/testsuite/gas/i386/x86-64-prefetchi-intel.d b/gas/testsuite/gas/i386/x86-64-prefetchi-intel.d > new file mode 100644 > index 0000000000..7f72f0a1eb > --- /dev/null > +++ b/gas/testsuite/gas/i386/x86-64-prefetchi-intel.d > @@ -0,0 +1,16 @@ > +#as: > +#objdump: -dwMintel > +#name: x86-64 PREFETCHI insns (Intel disassembly) > +#source: x86-64-prefetchi.s > + > +.*: +file format .* > + > + > +Disassembly of section .text: > + > +0+ <_start>: > +[ ]*[a-f0-9]+: 0f 18 3d 78 56 34 12 prefetchit0 BYTE PTR \[rip\+0x12345678\] # [0-9a-f]+ <_start\+0x[0-9a-f]+> > +[ ]*[a-f0-9]+: 0f 18 35 78 56 34 12 prefetchit1 BYTE PTR \[rip\+0x12345678\] # [0-9a-f]+ <_start\+0x[0-9a-f]+> > +[ ]*[a-f0-9]+: 0f 18 3d 78 56 34 12 prefetchit0 BYTE PTR \[rip\+0x12345678\] # [0-9a-f]+ <_start\+0x[0-9a-f]+> > +[ ]*[a-f0-9]+: 0f 18 35 78 56 34 12 prefetchit1 BYTE PTR \[rip\+0x12345678\] # [0-9a-f]+ <_start\+0x[0-9a-f]+> > +#pass > diff --git a/gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.d b/gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.d > new file mode 100644 > index 0000000000..b29b1ae237 > --- /dev/null > +++ b/gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.d > @@ -0,0 +1,13 @@ > +#as: > +#objdump: -dw > +#name: x86-64 PREFETCHI INVAL REGISTER insns > + > +.*: +file format .* > + > + > +Disassembly of section .text: > + > +0+ <\.text>: > +[ ]*[a-f0-9]+:[ ]0f 18 39[ ]*nopl \(%rcx\) > +[ ]*[a-f0-9]+:[ ]0f 18 31[ ]*nopl \(%rcx\) > +#pass > diff --git a/gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.s b/gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.s > new file mode 100644 > index 0000000000..550449a0c9 > --- /dev/null > +++ b/gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.s > @@ -0,0 +1,9 @@ > +.text > + #prefetchit0 (%rcx) PREFETCHIT0/1 apply without RIP-relative addressing, should stay NOPs. > + .byte 0x0f > + .byte 0x18 > + .byte 0x39 > + #prefetchit1 (%rcx) PREFETCHIT1/1 apply without RIP-relative addressing, should stay NOPs. > + .byte 0x0f > + .byte 0x18 > + .byte 0x31 > diff --git a/gas/testsuite/gas/i386/x86-64-prefetchi-warn.l b/gas/testsuite/gas/i386/x86-64-prefetchi-warn.l > new file mode 100644 > index 0000000000..4e15389463 > --- /dev/null > +++ b/gas/testsuite/gas/i386/x86-64-prefetchi-warn.l > @@ -0,0 +1,5 @@ > +.*: Assembler messages: > +.*:[0-9]*: Warning: only support RIP-relative address > +.*:[0-9]*: Warning: only support RIP-relative address > +.*:[0-9]*: Warning: only support RIP-relative address > +.*:[0-9]*: Warning: only support RIP-relative address > diff --git a/gas/testsuite/gas/i386/x86-64-prefetchi-warn.s b/gas/testsuite/gas/i386/x86-64-prefetchi-warn.s > new file mode 100644 > index 0000000000..330ff31c75 > --- /dev/null > +++ b/gas/testsuite/gas/i386/x86-64-prefetchi-warn.s > @@ -0,0 +1,11 @@ > +# Check error for ICACHE-PREFETCH 64-bit instruction > + > + .allow_index_reg > + .text > +_start: > + prefetchit0 0x12345678(%rax) > + prefetchit1 0x12345678(%rax) > + > + .intel_syntax noprefix > + prefetchit0 BYTE PTR [rax+0x12345678] > + prefetchit1 BYTE PTR [rax+0x12345678] > diff --git a/gas/testsuite/gas/i386/x86-64-prefetchi.d b/gas/testsuite/gas/i386/x86-64-prefetchi.d > new file mode 100644 > index 0000000000..c8ab92d147 > --- /dev/null > +++ b/gas/testsuite/gas/i386/x86-64-prefetchi.d > @@ -0,0 +1,15 @@ > +#as: > +#objdump: -dw > +#name: x86-64 PREFETCHI insns > + > +.*: +file format .* > + > + > +Disassembly of section .text: > + > +0+ <_start>: > +[ ]*[a-f0-9]+: 0f 18 3d 78 56 34 12 prefetchit0 0x12345678\(%rip\) # [0-9a-f]+ <_start\+0x[0-9a-f]+> > +[ ]*[a-f0-9]+: 0f 18 35 78 56 34 12 prefetchit1 0x12345678\(%rip\) # [0-9a-f]+ <_start\+0x[0-9a-f]+> > +[ ]*[a-f0-9]+: 0f 18 3d 78 56 34 12 prefetchit0 0x12345678\(%rip\) # [0-9a-f]+ <_start\+0x[0-9a-f]+> > +[ ]*[a-f0-9]+: 0f 18 35 78 56 34 12 prefetchit1 0x12345678\(%rip\) # [0-9a-f]+ <_start\+0x[0-9a-f]+> > +#pass > diff --git a/gas/testsuite/gas/i386/x86-64-prefetchi.s b/gas/testsuite/gas/i386/x86-64-prefetchi.s > new file mode 100644 > index 0000000000..cc7c61e9a9 > --- /dev/null > +++ b/gas/testsuite/gas/i386/x86-64-prefetchi.s > @@ -0,0 +1,14 @@ > +# Check 64bit PREFETCHI instructions > + > + .allow_index_reg > + .text > +_start: > + > + prefetchit0 0x12345678(%rip) > + prefetchit1 0x12345678(%rip) > + > + .intel_syntax noprefix > + > + prefetchit0 BYTE PTR [rip+0x12345678] > + prefetchit1 BYTE PTR [rip+0x12345678] > + > diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c > index 27ae8eaf46..9ef3d7a6ae 100644 > --- a/opcodes/i386-dis.c > +++ b/opcodes/i386-dis.c > @@ -114,6 +114,7 @@ static void FXSAVE_Fixup (instr_info *, int, int); > > static void MOVSXD_Fixup (instr_info *, int, int); > static void DistinctDest_Fixup (instr_info *, int, int); > +static void PREFETCHI_Fixup (instr_info *, int, int); > > /* This character is used to encode style information within the output > buffers. See oappend_insert_style for more details. */ > @@ -841,6 +842,8 @@ enum > MOD_0F18_REG_1, > MOD_0F18_REG_2, > MOD_0F18_REG_3, > + MOD_0F18_REG_6, > + MOD_0F18_REG_7, > MOD_0F1A_PREFIX_0, > MOD_0F1B_PREFIX_0, > MOD_0F1B_PREFIX_1, > @@ -1006,6 +1009,8 @@ enum > PREFIX_0F11, > PREFIX_0F12, > PREFIX_0F16, > + PREFIX_0F18_REG_6_MOD_0_X86_64, > + PREFIX_0F18_REG_7_MOD_0_X86_64, > PREFIX_0F1A, > PREFIX_0F1B, > PREFIX_0F1C, > @@ -1280,6 +1285,8 @@ enum > X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1, > X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3, > X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1, > + X86_64_0F18_REG_6_MOD_0, > + X86_64_0F18_REG_7_MOD_0, > X86_64_0F24, > X86_64_0F26, > X86_64_0FC7_REG_6_MOD_3_PREFIX_1, > @@ -2751,8 +2758,8 @@ static const struct dis386 reg_table[][8] = { > { MOD_TABLE (MOD_0F18_REG_3) }, > { "nopQ", { Ev }, 0 }, > { "nopQ", { Ev }, 0 }, > - { "nopQ", { Ev }, 0 }, > - { "nopQ", { Ev }, 0 }, > + { MOD_TABLE (MOD_0F18_REG_6) }, > + { MOD_TABLE (MOD_0F18_REG_7) }, > }, > /* REG_0F1C_P_0_MOD_0 */ > { > @@ -3118,6 +3125,22 @@ static const struct dis386 prefix_table[][4] = { > { MOD_TABLE (MOD_0F16_PREFIX_2) }, > }, > > + /* PREFIX_0F18_REG_6_MOD_0_X86_64 */ > + { > + { "prefetchit1", { { PREFETCHI_Fixup, b_mode } }, 0 }, > + { "nopQ", { Ev }, 0 }, > + { "nopQ", { Ev }, 0 }, > + { "nopQ", { Ev }, 0 }, > + }, > + > + /* PREFIX_0F18_REG_7_MOD_0_X86_64 */ > + { > + { "prefetchit0", { { PREFETCHI_Fixup, b_mode } }, 0 }, > + { "nopQ", { Ev }, 0 }, > + { "nopQ", { Ev }, 0 }, > + { "nopQ", { Ev }, 0 }, > + }, > + > /* PREFIX_0F1A */ > { > { MOD_TABLE (MOD_0F1A_PREFIX_0) }, > @@ -4394,6 +4417,18 @@ static const struct dis386 x86_64_table[][2] = { > { "psmash", { Skip_MODRM }, 0 }, > }, > > + /* X86_64_0F18_REG_6_MOD_0 */ > + { > + { "nopQ", { Ev }, 0 }, > + { PREFIX_TABLE (PREFIX_0F18_REG_6_MOD_0_X86_64) }, > + }, > + > + /* X86_64_0F18_REG_7_MOD_0 */ > + { > + { "nopQ", { Ev }, 0 }, > + { PREFIX_TABLE (PREFIX_0F18_REG_7_MOD_0_X86_64) }, > + }, > + > { > /* X86_64_0F24 */ > { "movZ", { Em, Td }, 0 }, > @@ -8193,6 +8228,16 @@ static const struct dis386 mod_table[][2] = { > { "prefetcht2", { Mb }, 0 }, > { "nopQ", { Ev }, 0 }, > }, > + { > + /* MOD_0F18_REG_6 */ > + { X86_64_TABLE (X86_64_0F18_REG_6_MOD_0) }, > + { "nopQ", { Ev }, 0 }, > + }, > + { > + /* MOD_0F18_REG_7 */ > + { X86_64_TABLE (X86_64_0F18_REG_7_MOD_0) }, > + { "nopQ", { Ev }, 0 }, > + }, > { > /* MOD_0F1A_PREFIX_0 */ > { "bndldx", { Gbnd, Mv_bnd }, 0 }, > @@ -13940,3 +13985,32 @@ OP_Rounding (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED) > } > oappend (ins, "sae}"); > } > + > +static void > +PREFETCHI_Fixup (instr_info *ins, int bytemode, int sizeflag) > +{ > + if (ins->modrm.mod != 0 || ins->modrm.rm != 5) > + { > + if (ins->intel_syntax) > + { > + ins->mnemonicendp = stpcpy (ins->obuf, "nop "); > + } > + else > + { > + USED_REX (REX_W); > + if (ins->rex & REX_W) > + ins->mnemonicendp = stpcpy (ins->obuf, "nopq "); > + else > + { > + if (sizeflag & DFLAG) > + ins->mnemonicendp = stpcpy (ins->obuf, "nopl "); > + else > + ins->mnemonicendp = stpcpy (ins->obuf, "nopw "); > + ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); > + } > + } > + bytemode = v_mode; > + } > + > + OP_M (ins, bytemode, sizeflag); > +} > diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c > index 237f147ad4..33339ba840 100644 > --- a/opcodes/i386-gen.c > +++ b/opcodes/i386-gen.c > @@ -259,6 +259,8 @@ static initializer cpu_flag_init[] = > "CpuWRMSRNS" }, > { "CPU_MSRLIST_FLAGS", > "CpuMSRLIST" }, > + { "CPU_PREFETCHI_FLAGS", > + "CpuPREFETCHI"}, > { "CPU_IAMCU_FLAGS", > "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" }, > { "CPU_ADX_FLAGS", > @@ -677,6 +679,7 @@ static bitfield cpu_flags[] = > BITFIELD (CpuRAO_INT), > BITFIELD (CpuWRMSRNS), > BITFIELD (CpuMSRLIST), > + BITFIELD (CpuPREFETCHI), > BITFIELD (CpuMWAITX), > BITFIELD (CpuCLZERO), > BITFIELD (CpuOSPKE), > diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h > index 645abe7f34..1ed319c20b 100644 > --- a/opcodes/i386-opc.h > +++ b/opcodes/i386-opc.h > @@ -223,6 +223,8 @@ enum > CpuWRMSRNS, > /* Intel MSRLIST Instructions support required. */ > CpuMSRLIST, > + /* PREFETCHI instruction required */ > + CpuPREFETCHI, > /* mwaitx instruction required */ > CpuMWAITX, > /* Clzero instruction required */ > @@ -411,6 +413,7 @@ typedef union i386_cpu_flags > unsigned int cpurao_int:1; > unsigned int cpuwrmsrns:1; > unsigned int cpumsrlist:1; > + unsigned int cpuprefetchi:1; > unsigned int cpumwaitx:1; > unsigned int cpuclzero:1; > unsigned int cpuospke:1; > diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl > index bb5dc6799d..d63aa1dfb2 100644 > --- a/opcodes/i386-opc.tbl > +++ b/opcodes/i386-opc.tbl > @@ -3323,3 +3323,10 @@ rdmsrlist, 0xf20f01c6, None, CpuMSRLIST|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|N > wrmsrlist, 0xf30f01c6, None, CpuMSRLIST|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {} > > // MSRLIST instructions end. > + > +// PREFETCHI instructions. > + > +prefetchit0, 0xf18, 0x7, CpuPREFETCHI|Cpu64, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { BaseIndex } > +prefetchit1, 0xf18, 0x6, CpuPREFETCHI|Cpu64, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { BaseIndex } > + > +// PREFETCHI instructions end. > -- > 2.17.1 > Thanks, > Lili. > > Thanks. -- H.J.