From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qv1-xf31.google.com (mail-qv1-xf31.google.com [IPv6:2607:f8b0:4864:20::f31]) by sourceware.org (Postfix) with ESMTPS id BDA233858D37 for ; Wed, 17 Aug 2022 19:19:51 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org BDA233858D37 Received: by mail-qv1-xf31.google.com with SMTP id d1so10808405qvs.0 for ; Wed, 17 Aug 2022 12:19:51 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc; bh=teitf0UdOCAM2g2OQWZZqdTTo7Xk1VcsKeI0WavAhr0=; b=PGOnfPGhWdw0b0Li3+HDtjrLpp0WJsatoKhOS7jtmNx8ANH4VrM1a81/IgnFemW0EU KYO7hjZNzqgl5RfDlMmYgcUVqYF+zukF3HIYe9A9n0xzRkE5mEoW8OhceMiRhjipCq4I RSv4VlfiofqE17t14nDC442GFatxASGkNIOyNToSCrejin5a/FwLUHhi45lORMHuHmEP kPVTjsBYEVoiyyHX36Pg56tsEbtXFFiofyVuCn4EMbZ9cUmNes0dP9Bm1/zh8CZZgl4q KBUK6wEcvj63+L4xsja6A+0ATcNOSe6uXnWi5MFQqrG2bLuh29Telo6bxDXx6Z+6IVQ9 OBPw== X-Gm-Message-State: ACgBeo1vBwAUH3I52V8G8lV9ZFBo3Ya6p1kt+Ihvu8xTN2PmmXORBhzu ynG5eyhQ5oeFFKr9nzoIf5jCSwvBlvwAJVjkvmU= X-Google-Smtp-Source: AA6agR54UQOHJ0DiBh0gnB7PHqq0i7yJ0asidIBrHEdk/soEUaLMsGXo5BgPZ1k+3dqZ9m5vSTmFd6j7K/0DX2M67CM= X-Received: by 2002:ad4:5c88:0:b0:476:7fc7:a24 with SMTP id o8-20020ad45c88000000b004767fc70a24mr23960997qvh.28.1660763990298; Wed, 17 Aug 2022 12:19:50 -0700 (PDT) MIME-Version: 1.0 References: <32216291-fd1f-4579-87de-d24cb7190894@suse.com> In-Reply-To: From: "H.J. Lu" Date: Wed, 17 Aug 2022 12:19:14 -0700 Message-ID: Subject: Re: [PATCH 1/7] x86/Intel: restrict suffix derivation To: Jan Beulich Cc: Binutils Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-3018.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 17 Aug 2022 19:19:57 -0000 On Tue, Aug 16, 2022 at 12:30 AM Jan Beulich wrote: > > While in some cases deriving an AT&T-style suffix from an Intel syntax > memory operand size specifier is necessary, in many cases this is not > only pointless, but has led to the introduction of various workarounds: > Excessive use of IgnoreSize and NoRex64 as well as the ToDword and > ToQword attributes. Suppress suffix derivation when we can clearly tell > that the memory operand's size isn't going to be needed to infer the > possible need for the low byte/word opcode bit or an operand size prefix > (0x66 or REX.W). > > As a result ToDword and ToQword can be dropped entirely, plus a fair > number of IgnoreSize and NoRex64 can also be got rid of. Note that > IgnoreSize needs to remain on legacy encoded SIMD insns with GPR > operand, to avoid emitting an operand size prefix in 16-bit mode. (Since > 16-bit code using SIMD insns isn't well tested, clone an existing > testcase just enough to cover a few insns which are potentially > problematic but are being touched here.) > > As a side effect of folding the VCVT{,T}S{S,D,H}2SI templates, > VCVT{,T}SH2SI will now allow L and Q suffixes, consistent with > VCVT{,T}S{S,D}2SI. All of these remain inconsistent with their 2USI > counterparts (which I think should also be corrected, but perhaps better > in a separate change). I don't think allowing more unnecessary L and Q suffixes for AVX instructions is desirable. I prefer not to allow unnecessary L and Q suffixes in folded entries. We can add special entries to allow the existing instructions with suffixes. > --- > Long term suffix derivation should be dropped altogether, not the least > such that bogus error messages like "incorrect register `...' used with > `...' suffix" don't misguid people anymore when no suffix was used at > all. > > --- a/gas/config/tc-i386.c > +++ b/gas/config/tc-i386.c > @@ -7071,42 +7071,22 @@ process_suffix (void) > } > else if (i.suffix =3D=3D BYTE_MNEM_SUFFIX) > { > - if (intel_syntax > - && i.tm.opcode_modifier.mnemonicsize =3D=3D IGNORESIZE > - && i.tm.opcode_modifier.no_bsuf) > - i.suffix =3D 0; > - else if (!check_byte_reg ()) > + if (!check_byte_reg ()) > return 0; > } > else if (i.suffix =3D=3D LONG_MNEM_SUFFIX) > { > - if (intel_syntax > - && i.tm.opcode_modifier.mnemonicsize =3D=3D IGNORESIZE > - && i.tm.opcode_modifier.no_lsuf > - && !i.tm.opcode_modifier.todword > - && !i.tm.opcode_modifier.toqword) > - i.suffix =3D 0; > - else if (!check_long_reg ()) > + if (!check_long_reg ()) > return 0; > } > else if (i.suffix =3D=3D QWORD_MNEM_SUFFIX) > { > - if (intel_syntax > - && i.tm.opcode_modifier.mnemonicsize =3D=3D IGNORESIZE > - && i.tm.opcode_modifier.no_qsuf > - && !i.tm.opcode_modifier.todword > - && !i.tm.opcode_modifier.toqword) > - i.suffix =3D 0; > - else if (!check_qword_reg ()) > + if (!check_qword_reg ()) > return 0; > } > else if (i.suffix =3D=3D WORD_MNEM_SUFFIX) > { > - if (intel_syntax > - && i.tm.opcode_modifier.mnemonicsize =3D=3D IGNORESIZE > - && i.tm.opcode_modifier.no_wsuf) > - i.suffix =3D 0; > - else if (!check_word_reg ()) > + if (!check_word_reg ()) > return 0; > } > else if (intel_syntax > @@ -7566,20 +7546,9 @@ check_long_reg (void) > || i.tm.operand_types[op].bitfield.instance =3D=3D Accum= ) > && i.tm.operand_types[op].bitfield.dword) > { > - if (intel_syntax > - && i.tm.opcode_modifier.toqword > - && i.types[0].bitfield.class !=3D RegSIMD) > - { > - /* Convert to QWORD. We want REX byte. */ > - i.suffix =3D QWORD_MNEM_SUFFIX; > - } > - else > - { > - as_bad (_("incorrect register `%s%s' used with `%c' suffix"), > - register_prefix, i.op[op].regs->reg_name, > - i.suffix); > - return 0; > - } > + as_bad (_("incorrect register `%s%s' used with `%c' suffix"), > + register_prefix, i.op[op].regs->reg_name, i.suffix); > + return 0; > } > return 1; > } > @@ -7617,20 +7586,9 @@ check_qword_reg (void) > { > /* Prohibit these changes in the 64bit mode, since the > lowering is more complicated. */ > - if (intel_syntax > - && i.tm.opcode_modifier.todword > - && i.types[0].bitfield.class !=3D RegSIMD) > - { > - /* Convert to DWORD. We don't want REX byte. */ > - i.suffix =3D LONG_MNEM_SUFFIX; > - } > - else > - { > - as_bad (_("incorrect register `%s%s' used with `%c' suffix"), > - register_prefix, i.op[op].regs->reg_name, > - i.suffix); > - return 0; > - } > + as_bad (_("incorrect register `%s%s' used with `%c' suffix"), > + register_prefix, i.op[op].regs->reg_name, i.suffix); > + return 0; > } > return 1; > } > @@ -7670,14 +7628,6 @@ check_word_reg (void) > i.suffix); > return 0; > } > - /* For some instructions need encode as EVEX.W=3D1 without explicit = VexW1. */ > - else if (i.types[op].bitfield.qword > - && intel_syntax > - && i.tm.opcode_modifier.toqword) > - { > - /* Convert to QWORD. We want EVEX.W byte. */ > - i.suffix =3D QWORD_MNEM_SUFFIX; > - } > return 1; > } > > --- a/gas/config/tc-i386-intel.c > +++ b/gas/config/tc-i386-intel.c > @@ -790,9 +790,83 @@ i386_intel_operand (char *operand_string > break; > } > > + /* Now check whether we actually want to infer an AT&T-like suffix= . > + We really only need to do this when operand size determination (= incl. > + REX.W) is going to be derived from it. For this we check whethe= r the > + given suffix is valid for any of the candidate templates. */ > + if (suffix && suffix !=3D i.suffix > + && (current_templates->start->opcode_modifier.opcodespace !=3D = SPACE_BASE > + || current_templates->start->base_opcode !=3D 0x62 /* bound= */)) > + { > + const insn_template *t; > + > + for (t =3D current_templates->start; t < current_templates->end= ; ++t) > + { > + /* Operands haven't been swapped yet. */ > + unsigned int op =3D t->operands - 1 - this_operand; > + > + /* Easy checks to skip templates which won't match anyway. = */ > + if (this_operand >=3D t->operands || t->opcode_modifier.att= syntax) > + continue; > + > + switch (suffix) > + { > + case BYTE_MNEM_SUFFIX: > + if (t->opcode_modifier.no_bsuf) > + continue; > + break; > + case WORD_MNEM_SUFFIX: > + if (t->opcode_modifier.no_wsuf) > + continue; > + break; > + case LONG_MNEM_SUFFIX: > + if (t->opcode_modifier.no_lsuf) > + continue; > + break; > + case QWORD_MNEM_SUFFIX: > + if (t->opcode_modifier.no_qsuf) > + continue; > + break; > + case SHORT_MNEM_SUFFIX: > + if (t->opcode_modifier.no_ssuf) > + continue; > + break; > + case LONG_DOUBLE_MNEM_SUFFIX: > + if (t->opcode_modifier.no_ldsuf) > + continue; > + break; > + default: > + abort (); > + } > + > + /* In a few cases suffixes are permitted, but we can nevert= heless > + derive that these aren't going to be needed. This is on= ly of > + interest for insns using ModR/M, plus we can skip templa= tes with > + swappable operands here (simplifying subsequent logic). = */ > + if (!t->opcode_modifier.modrm || t->opcode_modifier.d) > + break; > + > + if (!t->operand_types[op].bitfield.baseindex) > + continue; > + > + switch (t->operand_types[op].bitfield.class) > + { > + case RegMMX: > + case RegSIMD: > + case RegMask: > + continue; > + } > + > + break; > + } > + > + if (t =3D=3D current_templates->end) > + suffix =3D 0; > + } > + > if (!i.suffix) > i.suffix =3D suffix; > - else if (i.suffix !=3D suffix) > + else if (suffix && i.suffix !=3D suffix) > { > as_bad (_("conflicting operand size modifiers")); > return 0; > --- a/gas/testsuite/gas/i386/i386.exp > +++ b/gas/testsuite/gas/i386/i386.exp > @@ -169,6 +169,7 @@ if [gas_32_check] then { > run_dump_test "simd" > run_dump_test "simd-intel" > run_dump_test "simd-suffix" > + run_dump_test "simd16" > run_dump_test "mem" > run_dump_test "mem-intel" > run_dump_test "reg" > --- a/gas/testsuite/gas/i386/simd.s > +++ b/gas/testsuite/gas/i386/simd.s > @@ -1,5 +1,6 @@ > .text > _start: > + .ifndef use16 > addsubps 0x12345678,%xmm1 > comisd 0x12345678,%xmm1 > comiss 0x12345678,%xmm1 > @@ -31,6 +32,7 @@ _start: > punpcklqdq 0x12345678,%xmm1 > ucomisd 0x12345678,%xmm1 > ucomiss 0x12345678,%xmm1 > + .endif > > cmpeqsd (%eax),%xmm0 > cmpeqss (%eax),%xmm0 > @@ -101,6 +103,7 @@ cmpsd $0x10,(%eax),%xmm7 > > .intel_syntax noprefix > > + .ifndef use16 > addsubps xmm1,XMMWORD PTR ds:0x12345678 > comisd xmm1,QWORD PTR ds:0x12345678 > comiss xmm1,DWORD PTR ds:0x12345678 > @@ -132,6 +135,8 @@ punpcklwd xmm1,XMMWORD PTR ds:0x12345678 > punpcklqdq xmm1,XMMWORD PTR ds:0x12345678 > ucomisd xmm1,QWORD PTR ds:0x12345678 > ucomiss xmm1,DWORD PTR ds:0x12345678 > + .endif > + > cmpeqsd xmm0,QWORD PTR [eax] > cmpeqss xmm0,DWORD PTR [eax] > cvtpi2pd xmm0,QWORD PTR [eax] > --- /dev/null > +++ b/gas/testsuite/gas/i386/simd16.d > @@ -0,0 +1,137 @@ > +#as: --defsym use16=3D1 -I${srcdir}/$subdir > +#objdump: -dw -Mi8086 > +#name: i386 SIMD (16-bit) > + > +.*: +file format .* > + > +Disassembly of section .text: > + > +0+ <_start>: > +[ ]*[a-f0-9]+: 67 f2 0f c2 00 00 cmpeqsd \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 f3 0f c2 00 00 cmpeqss \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 66 0f 2a 00 cvtpi2pd \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 0f 2a 00 cvtpi2ps \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 0f 2d 00 cvtps2pi \(%eax\),%mm0 > +[ ]*[a-f0-9]+: 67 f2 0f 2d 00 cvtsd2si \(%eax\),%eax > +[ ]*[a-f0-9]+: 67 f2 0f 2c 00 cvttsd2si \(%eax\),%eax > +[ ]*[a-f0-9]+: 67 f2 0f 5a 00 cvtsd2ss \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 f3 0f 5a 00 cvtss2sd \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 f3 0f 2d 00 cvtss2si \(%eax\),%eax > +[ ]*[a-f0-9]+: 67 f3 0f 2c 00 cvttss2si \(%eax\),%eax > +[ ]*[a-f0-9]+: 67 f2 0f 5e 00 divsd \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 f3 0f 5e 00 divss \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 f2 0f 5f 00 maxsd \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 f3 0f 5f 00 maxss \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 f3 0f 5d 00 minss \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 f3 0f 5d 00 minss \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 f2 0f 2b 00 movntsd %xmm0,\(%eax\) > +[ ]*[a-f0-9]+: 67 f3 0f 2b 00 movntss %xmm0,\(%eax\) > +[ ]*[a-f0-9]+: 67 f2 0f 10 00 movsd \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 f2 0f 11 00 movsd %xmm0,\(%eax\) > +[ ]*[a-f0-9]+: 67 f3 0f 10 00 movss \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 f3 0f 11 00 movss %xmm0,\(%eax\) > +[ ]*[a-f0-9]+: 67 f2 0f 59 00 mulsd \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 f3 0f 59 00 mulss \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 f3 0f 53 00 rcpss \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 66 0f 3a 0b 00 00 roundsd \$0x0,\(%eax\),%x= mm0 > +[ ]*[a-f0-9]+: 67 66 0f 3a 0a 00 00 roundss \$0x0,\(%eax\),%x= mm0 > +[ ]*[a-f0-9]+: 67 f3 0f 52 00 rsqrtss \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 f2 0f 51 00 sqrtsd \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 f3 0f 51 00 sqrtss \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 f2 0f 5c 00 subsd \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 f3 0f 5c 00 subss \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 66 0f 38 20 00 pmovsxbw \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 66 0f 38 21 00 pmovsxbd \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 66 0f 38 22 00 pmovsxbq \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 66 0f 38 23 00 pmovsxwd \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 66 0f 38 24 00 pmovsxwq \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 66 0f 38 25 00 pmovsxdq \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 66 0f 38 30 00 pmovzxbw \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 66 0f 38 31 00 pmovzxbd \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 66 0f 38 32 00 pmovzxbq \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 66 0f 38 33 00 pmovzxwd \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 66 0f 38 34 00 pmovzxwq \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 66 0f 38 35 00 pmovzxdq \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 66 0f 3a 21 00 00 insertps \$0x0,\(%eax\),%= xmm0 > +[ ]*[a-f0-9]+: 67 66 0f 15 08 unpckhpd \(%eax\),%xmm1 > +[ ]*[a-f0-9]+: 67 0f 15 08 unpckhps \(%eax\),%xmm1 > +[ ]*[a-f0-9]+: 67 66 0f 14 08 unpcklpd \(%eax\),%xmm1 > +[ ]*[a-f0-9]+: 67 0f 14 08 unpcklps \(%eax\),%xmm1 > +[ ]*[a-f0-9]+: f3 0f c2 f7 10 cmpss \$0x10,%xmm7,%xmm6 > +[ ]*[a-f0-9]+: 67 f3 0f c2 38 10 cmpss \$0x10,\(%eax\),%x= mm7 > +[ ]*[a-f0-9]+: f2 0f c2 f7 10 cmpsd \$0x10,%xmm7,%xmm6 > +[ ]*[a-f0-9]+: 67 f2 0f c2 38 10 cmpsd \$0x10,\(%eax\),%x= mm7 > +[ ]*[a-f0-9]+: f3 0f 2a c8 cvtsi2ss %eax,%xmm1 > +[ ]*[a-f0-9]+: f2 0f 2a c8 cvtsi2sd %eax,%xmm1 > +[ ]*[a-f0-9]+: f3 0f 2a c8 cvtsi2ss %eax,%xmm1 > +[ ]*[a-f0-9]+: f2 0f 2a c8 cvtsi2sd %eax,%xmm1 > +[ ]*[a-f0-9]+: 67 f3 0f 2a 08 cvtsi2ss \(%eax\),%xmm1 > +[ ]*[a-f0-9]+: 67 f2 0f 2a 08 cvtsi2sd \(%eax\),%xmm1 > +[ ]*[a-f0-9]+: 67 f3 0f 2a 08 cvtsi2ss \(%eax\),%xmm1 > +[ ]*[a-f0-9]+: 67 f2 0f 2a 08 cvtsi2sd \(%eax\),%xmm1 > +[ ]*[a-f0-9]+: 67 f2 0f c2 00 00 cmpeqsd \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 f3 0f c2 00 00 cmpeqss \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 66 0f 2a 00 cvtpi2pd \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 0f 2a 00 cvtpi2ps \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 0f 2d 00 cvtps2pi \(%eax\),%mm0 > +[ ]*[a-f0-9]+: 67 f2 0f 2d 00 cvtsd2si \(%eax\),%eax > +[ ]*[a-f0-9]+: 67 f2 0f 2c 00 cvttsd2si \(%eax\),%eax > +[ ]*[a-f0-9]+: 67 f2 0f 5a 00 cvtsd2ss \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 f3 0f 5a 00 cvtss2sd \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 f3 0f 2d 00 cvtss2si \(%eax\),%eax > +[ ]*[a-f0-9]+: 67 f3 0f 2c 00 cvttss2si \(%eax\),%eax > +[ ]*[a-f0-9]+: 67 f2 0f 5e 00 divsd \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 f3 0f 5e 00 divss \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 f2 0f 5f 00 maxsd \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 f3 0f 5f 00 maxss \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 f3 0f 5d 00 minss \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 f3 0f 5d 00 minss \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 f2 0f 2b 00 movntsd %xmm0,\(%eax\) > +[ ]*[a-f0-9]+: 67 f3 0f 2b 00 movntss %xmm0,\(%eax\) > +[ ]*[a-f0-9]+: 67 f2 0f 10 00 movsd \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 f2 0f 11 00 movsd %xmm0,\(%eax\) > +[ ]*[a-f0-9]+: 67 f3 0f 10 00 movss \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 f3 0f 11 00 movss %xmm0,\(%eax\) > +[ ]*[a-f0-9]+: 67 f2 0f 59 00 mulsd \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 f3 0f 59 00 mulss \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 f3 0f 53 00 rcpss \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 66 0f 3a 0b 00 00 roundsd \$0x0,\(%eax\),%x= mm0 > +[ ]*[a-f0-9]+: 67 66 0f 3a 0a 00 00 roundss \$0x0,\(%eax\),%x= mm0 > +[ ]*[a-f0-9]+: 67 f3 0f 52 00 rsqrtss \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 f2 0f 51 00 sqrtsd \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 f3 0f 51 00 sqrtss \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 f2 0f 5c 00 subsd \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 f3 0f 5c 00 subss \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 66 0f 38 20 00 pmovsxbw \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 66 0f 38 21 00 pmovsxbd \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 66 0f 38 22 00 pmovsxbq \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 66 0f 38 23 00 pmovsxwd \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 66 0f 38 24 00 pmovsxwq \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 66 0f 38 25 00 pmovsxdq \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 66 0f 38 30 00 pmovzxbw \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 66 0f 38 31 00 pmovzxbd \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 66 0f 38 32 00 pmovzxbq \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 66 0f 38 33 00 pmovzxwd \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 66 0f 38 34 00 pmovzxwq \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 66 0f 38 35 00 pmovzxdq \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 66 0f 3a 21 00 00 insertps \$0x0,\(%eax\),%= xmm0 > +[ ]*[a-f0-9]+: 67 66 0f 15 00 unpckhpd \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 0f 15 00 unpckhps \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 66 0f 14 00 unpcklpd \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: 67 0f 14 00 unpcklps \(%eax\),%xmm0 > +[ ]*[a-f0-9]+: f3 0f c2 f7 10 cmpss \$0x10,%xmm7,%xmm6 > +[ ]*[a-f0-9]+: 67 f3 0f c2 38 10 cmpss \$0x10,\(%eax\),%x= mm7 > +[ ]*[a-f0-9]+: f2 0f c2 f7 10 cmpsd \$0x10,%xmm7,%xmm6 > +[ ]*[a-f0-9]+: 67 f2 0f c2 38 10 cmpsd \$0x10,\(%eax\),%x= mm7 > +[ ]*[a-f0-9]+: f3 0f 2a c8 cvtsi2ss %eax,%xmm1 > +[ ]*[a-f0-9]+: f2 0f 2a c8 cvtsi2sd %eax,%xmm1 > +[ ]*[a-f0-9]+: f3 0f 2a c8 cvtsi2ss %eax,%xmm1 > +[ ]*[a-f0-9]+: f2 0f 2a c8 cvtsi2sd %eax,%xmm1 > +[ ]*[a-f0-9]+: 67 f3 0f 2a 08 cvtsi2ss \(%eax\),%xmm1 > +[ ]*[a-f0-9]+: 67 f3 0f 2a 08 cvtsi2ss \(%eax\),%xmm1 > +[ ]*[a-f0-9]+: 67 f2 0f 2a 08 cvtsi2sd \(%eax\),%xmm1 > +[ ]*[a-f0-9]+: 67 f2 0f 2a 08 cvtsi2sd \(%eax\),%xmm1 > +[ ]*[a-f0-9]+: 67 f3 0f 2a 08 cvtsi2ss \(%eax\),%xmm1 > +[ ]*[a-f0-9]+: 67 f2 0f 2a 08 cvtsi2sd \(%eax\),%xmm1 > +[ ]*[a-f0-9]+: 67 0f 2c 00 cvttps2pi \(%eax\),%mm0 > +#pass > --- /dev/null > +++ b/gas/testsuite/gas/i386/simd16.s > @@ -0,0 +1,2 @@ > + .code16 > + .include "simd.s" > --- a/opcodes/i386-gen.c > +++ b/opcodes/i386-gen.c > @@ -706,8 +706,6 @@ static bitfield opcode_modifiers[] =3D > BITFIELD (RegKludge), > BITFIELD (Implicit1stXmm0), > BITFIELD (PrefixOk), > - BITFIELD (ToDword), > - BITFIELD (ToQword), > BITFIELD (AddrPrefixOpReg), > BITFIELD (IsPrefix), > BITFIELD (ImmExt), > --- a/opcodes/i386-opc.h > +++ b/opcodes/i386-opc.h > @@ -521,10 +521,6 @@ enum > #define PrefixHLELock 5 /* Okay with a LOCK prefix. */ > #define PrefixHLEAny 6 /* Okay with or without a LOCK prefix. = */ > PrefixOk, > - /* Convert to DWORD */ > - ToDword, > - /* Convert to QWORD */ > - ToQword, > /* Address prefix changes register operand */ > AddrPrefixOpReg, > /* opcode is a prefix */ > @@ -740,8 +736,6 @@ typedef struct i386_opcode_modifier > unsigned int regkludge:1; > unsigned int implicit1stxmm0:1; > unsigned int prefixok:3; > - unsigned int todword:1; > - unsigned int toqword:1; > unsigned int addrprefixopreg:1; > unsigned int isprefix:1; > unsigned int immext:1; > --- a/opcodes/i386-opc.tbl > +++ b/opcodes/i386-opc.tbl > @@ -970,18 +970,18 @@ pause, 0xf390, None, Cpu186, No_bSuf|No_ > $avx:CpuAVX:66:Vex128|VexVVVV|VexW0|SSE2AVX:Vex128|VexVVVV=3D2|VexW0= |SSE2AVX:RegXMM:Xmmword, + > $sse:CpuSSE2:66:::RegXMM:Xmmword, + > - $mmx:CpuMMX::NoRex64::RegMMX:Qword> > + $mmx:CpuMMX::::RegMMX:Qword> > > $avx:CpuAVX:Vex128|VexW0|SSE2AVX:VexLIG|VexW0|SSE2AVX:VexVVVV:Vex128= |VexVVVV=3D2|VexW0|SSE2AVX, + > - $sse:CpuSSE2::NoRex64::> > + $sse:CpuSSE2::::> > > b:0:VexW0:Byte:CpuAVX512DQ:66:CpuAVX512VBMI, + > w:1:VexW1:Word:CpuAVX512F::CpuAVX512BW> > > - d:0:VexW0:IgnoreSize:Dword::Reg32:66, + > + d:0:VexW0::Dword::Reg32:66, + > q:1:VexW1:VexW1:Qword:Cpu64:Reg64:> > > emms, 0xf77, None, CpuMMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ld= Suf, {} > @@ -989,7 +989,7 @@ emms, 0xf77, None, CpuMMX, No_bSuf|No_wS > // copying between Reg64/Mem64 and RegXMM/RegMMX, as is mandated by Inte= l's > // spec). AMD's spec, having been in existence for much longer, failed t= o > // recognize that and specified movd for 32- and 64-bit operations. > -movd, 0x666e, None, CpuAVX, D|Modrm|Vex=3D1|Space0F|VexW=3D1|IgnoreSize|= No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Reg32|Unspecifi= ed|BaseIndex, RegXMM } > +movd, 0x666e, None, CpuAVX, D|Modrm|Vex128|Space0F|VexW0|No_bSuf|No_wSuf= |No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Reg32|Unspecified|BaseIndex, R= egXMM } > movd, 0x666e, None, CpuAVX|Cpu64, D|Modrm|Vex=3D1|Space0F|VexW1|No_bSuf|= No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64|SSE2AVX, { Reg64|BaseIndex,= RegXMM } > movd, 0x660f6e, None, CpuSSE2, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSu= f|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, RegXMM } > movd, 0x660f6e, None, CpuSSE2|Cpu64, D|Modrm|No_bSuf|No_wSuf|No_lSuf|No_= sSuf|No_qSuf|No_ldSuf|Size64, { Reg64|BaseIndex, RegXMM } > @@ -998,10 +998,10 @@ movd, 0xf6e, None, CpuMMX|Cpu64, D|Modrm > movq, 0xf37e, None, CpuAVX, Load|Modrm|Vex=3D1|Space0F|VexWIG|No_bSuf|No= _wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseInd= ex|RegXMM, RegXMM } > movq, 0x66d6, None, CpuAVX, Modrm|Vex=3D1|Space0F|VexWIG|No_bSuf|No_wSuf= |No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Qword|Unspecified|Base= Index|RegXMM } > movq, 0x666e, None, CpuAVX|Cpu64, D|Modrm|Vex=3D1|Space0F|VexW1|No_bSuf|= No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64|SSE2AVX, { Reg64|Unspecifie= d|BaseIndex, RegXMM } > -movq, 0xf30f7e, None, CpuSSE2, Load|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSu= f|No_qSuf|No_ldSuf|NoRex64, { Unspecified|Qword|BaseIndex|RegXMM, RegXMM } > -movq, 0x660fd6, None, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_= qSuf|No_ldSuf|NoRex64, { RegXMM, Unspecified|Qword|BaseIndex|RegXMM } > +movq, 0xf30f7e, None, CpuSSE2, Load|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSu= f|No_qSuf|No_ldSuf, { Unspecified|Qword|BaseIndex|RegXMM, RegXMM } > +movq, 0x660fd6, None, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_= qSuf|No_ldSuf, { RegXMM, Unspecified|Qword|BaseIndex|RegXMM } > movq, 0x660f6e, None, CpuSSE2|Cpu64, D|Modrm|No_bSuf|No_wSuf|No_lSuf|No_= sSuf|No_qSuf|No_ldSuf|Size64, { Reg64|Unspecified|BaseIndex, RegXMM } > -movq, 0xf6f, None, CpuMMX, D|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS= uf|No_ldSuf|NoRex64, { Unspecified|Qword|BaseIndex|RegMMX, RegMMX } > +movq, 0xf6f, None, CpuMMX, D|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS= uf|No_ldSuf, { Unspecified|Qword|BaseIndex|RegMMX, RegMMX } > movq, 0xf6e, None, CpuMMX|Cpu64, D|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf= |No_qSuf|No_ldSuf|Size64, { Reg64|Unspecified|BaseIndex, RegMMX } > packssdw, 0x0f6b, None, , Modrm||No_bSu= f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { ||Unspecifi= ed|BaseIndex, } > packsswb, 0x0f63, None, , Modrm||No_bSu= f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { ||Unspecifi= ed|BaseIndex, } > @@ -1009,7 +1009,7 @@ packuswb, 0x0f67, None, padd, 0x0ffc | , None, , Modrm||C|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { ||Unspecified|BaseIndex, } > paddd, 0x0ffe, None, , Modrm||C|No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { ||Unspecifie= d|BaseIndex, } > paddq, 0x660fd4, None, , Modrm|||C= |No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|Bas= eIndex, RegXMM } > -paddq, 0xfd4, None, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS= uf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } > +paddq, 0xfd4, None, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS= uf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } > padds, 0x0fec | , None, , Modrm||C|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { ||Unspecified|BaseIndex, } > paddus, 0x0fdc | , None, , Modrm||C|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { ||Unspecified|BaseIndex, } > pand, 0x0fdb, None, , Modrm||C|No_bSuf|= No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { ||Unspecified= |BaseIndex, } > @@ -1037,25 +1037,25 @@ psrl, 0x0f72 | psub, 0x0ff8 | , None, , Modrm||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { ||Unspecified|BaseIndex, } > psubd, 0x0ffa, None, , Modrm||No_bSuf|N= o_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { ||Unspecified|= BaseIndex, } > psubq, 0x660ffb, None, , Modrm|||N= o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseI= ndex, RegXMM } > -psubq, 0xffb, None, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS= uf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } > +psubq, 0xffb, None, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS= uf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } > psubs, 0x0fe8 | , None, , Modrm||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { ||Unspecified|BaseIndex, } > psubus, 0x0fd8 | , None, , Modrm||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { ||Unspecified|BaseIndex, } > punpckhbw, 0x0f68, None, , Modrm||No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { ||Unspecif= ied|BaseIndex, } > punpckhwd, 0x0f69, None, , Modrm||No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { ||Unspecif= ied|BaseIndex, } > punpckhdq, 0x0f6a, None, , Modrm||No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { ||Unspecif= ied|BaseIndex, } > punpcklbw, 0x660f60, None, , Modrm|||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|B= aseIndex, RegXMM } > -punpcklbw, 0xf60, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf= |No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegMMX, RegMMX } > +punpcklbw, 0xf60, None, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegMMX, RegMMX } > punpcklwd, 0x660f61, None, , Modrm|||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|B= aseIndex, RegXMM } > -punpcklwd, 0xf61, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf= |No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegMMX, RegMMX } > +punpcklwd, 0xf61, None, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegMMX, RegMMX } > punpckldq, 0x660f62, None, , Modrm|||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|B= aseIndex, RegXMM } > -punpckldq, 0xf62, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf= |No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegMMX, RegMMX } > +punpckldq, 0xf62, None, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegMMX, RegMMX } > pxor, 0x0fef, None, , Modrm||C|No_bSuf|= No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { ||Unspecified= |BaseIndex, } > > // SSE instructions. > > $avx:CpuAVX:Vex128|VexW0|SSE2AVX:VexLIG|VexW0|SSE2AVX:VexVVVV, + > - $sse:CpuSSE::IgnoreSize:> > + $sse:CpuSSE:::> > > > addps, 0x0f58, None, , Modrm|||No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, = RegXMM } > @@ -1067,21 +1067,21 @@ cmpss, 0xf30fc2, , > cmpps, 0x0fc2, None, , Modrm|||No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseI= ndex, RegXMM } > cmpss, 0xf30fc2, None, , Modrm|||No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|Unspecified|Base= Index|RegXMM, RegXMM } > comiss, 0x0f2f, None, , Modrm||No_bSuf|No_wSuf|N= o_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegX= MM } > -cvtpi2ps, 0xf2a, None, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_= qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegXMM } > -cvtps2pi, 0xf2d, None, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_= qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegXMM, RegMMX } > +cvtpi2ps, 0xf2a, None, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_= qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegXMM } > +cvtps2pi, 0xf2d, None, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_= qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegMMX } > cvtsi2ss, 0xf30f2a, None, |CpuNo64, Modrm|||IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecif= ied|BaseIndex, RegXMM } > cvtsi2ss, 0xf32a, None, CpuAVX|Cpu64, Modrm|Vex=3D3|Space0F|VexVVVV=3D1|= IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SSE2AVX|ATTSyntax, { Reg32|Reg6= 4|Dword|Qword|Unspecified|BaseIndex, RegXMM } > cvtsi2ss, 0xf32a, None, CpuAVX|Cpu64, Modrm|Vex=3D3|Space0F|VexVVVV=3D1|= No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SSE2AVX|IntelSyntax, { Reg32|Reg64|Dword|Q= word|Unspecified|BaseIndex, RegXMM } > cvtsi2ss, 0xf30f2a, None, CpuSSE|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf= |No_sSuf|No_ldSuf|ATTSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseInde= x, RegXMM } > cvtsi2ss, 0xf30f2a, None, CpuSSE|Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No= _ldSuf|IntelSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM= } > -cvtss2si, 0xf32d, None, CpuAVX, Modrm|Vex=3D3|Space0F|No_bSuf|No_wSuf|No= _sSuf|No_ldSuf|ToQword|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, Reg32= |Reg64 } > -cvtss2si, 0xf30f2d, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sS= uf|No_ldSuf|ToQword, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } > -cvttps2pi, 0xf2c, None, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegXMM, RegMMX } > -cvttss2si, 0xf32c, None, CpuAVX, Modrm|Vex=3D3|Space0F|No_bSuf|No_wSuf|N= o_sSuf|No_ldSuf|ToQword|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, Reg3= 2|Reg64 } > -cvttss2si, 0xf30f2c, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_s= Suf|No_ldSuf|ToQword, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } > +cvtss2si, 0xf32d, None, CpuAVX, Modrm|VexLIG|Space0F|No_bSuf|No_wSuf|No_= sSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } > +cvtss2si, 0xf30f2d, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sS= uf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } > +cvttps2pi, 0xf2c, None, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegMMX } > +cvttss2si, 0xf32c, None, CpuAVX, Modrm|VexLIG|Space0F|No_bSuf|No_wSuf|No= _sSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } > +cvttss2si, 0xf30f2c, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_s= Suf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } > divps, 0x0f5e, None, , Modrm|||No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, = RegXMM } > divss, 0xf30f5e, None, , Modrm|||No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|= RegXMM, RegXMM } > -ldmxcsr, 0x0fae, 2, , Modrm||IgnoreSize|No_bSuf|= No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex } > +ldmxcsr, 0x0fae, 2, , Modrm||No_bSuf|No_wSuf|No_= lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex } > maskmovq, 0xff7, None, CpuSSE|Cpu3dnowA, Modrm|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegMMX, RegMMX } > maxps, 0x0f5f, None, , Modrm|||No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, = RegXMM } > maxss, 0xf30f5f, None, , Modrm|||No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|= RegXMM, RegXMM } > @@ -1089,51 +1089,51 @@ minps, 0x0f5d, None, , Mod > minss, 0xf30f5d, None, , Modrm|||No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|= RegXMM, RegXMM } > movaps, 0x0f28, None, , D|Modrm||No_bSuf|No_wSuf= |No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } > movhlps, 0x0f12, None, , Modrm|||No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM } > -movhps, 0x16, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexW=3D1|Ignor= eSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Uns= pecified|BaseIndex, RegXMM } > -movhps, 0x17, None, CpuAVX, Modrm|Vex|Space0F|VexW=3D1|IgnoreSize|No_bSu= f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Qword|Unspeci= fied|BaseIndex } > -movhps, 0xf16, None, CpuSSE, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|= No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM } > +movhps, 0x16, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexW0|No_bSuf|No_w= Suf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex= , RegXMM } > +movhps, 0x17, None, CpuAVX, Modrm|Vex|Space0F|VexW0|No_bSuf|No_wSuf|No_l= Suf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex= } > +movhps, 0xf16, None, CpuSSE, D|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_= qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM } > movlhps, 0x0f16, None, , Modrm|||No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM } > -movlps, 0x12, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexW=3D1|Ignor= eSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Uns= pecified|BaseIndex, RegXMM } > -movlps, 0x13, None, CpuAVX, Modrm|Vex|Space0F|VexW=3D1|IgnoreSize|No_bSu= f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Qword|Unspeci= fied|BaseIndex } > -movlps, 0xf12, None, CpuSSE, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|= No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM } > +movlps, 0x12, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexW0|No_bSuf|No_w= Suf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex= , RegXMM } > +movlps, 0x13, None, CpuAVX, Modrm|Vex|Space0F|VexW0|No_bSuf|No_wSuf|No_l= Suf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex= } > +movlps, 0xf12, None, CpuSSE, D|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_= qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM } > movmskps, 0x0f50, None, , Modrm||IgnoreSize|No_b= Suf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegXMM, Reg32|Reg64 } > movntps, 0x0f2b, None, , Modrm||No_bSuf|No_wSuf|= No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex } > -movntq, 0xfe7, None, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|= No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMMX, Qword|Unspecified|BaseIndex } > +movntq, 0xfe7, None, CpuSSE|Cpu3dnowA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_= sSuf|No_qSuf|No_ldSuf, { RegMMX, Qword|Unspecified|BaseIndex } > movntdq, 0x660fe7, None, , Modrm||No_bSuf|No_= wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIn= dex } > -movss, 0xf310, None, CpuAVX, D|Modrm|Vex=3D3|Space0F|VexW=3D1|IgnoreSize= |No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecif= ied|BaseIndex, RegXMM } > +movss, 0xf310, None, CpuAVX, D|Modrm|VexLIG|Space0F|VexW0|No_bSuf|No_wSu= f|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex, = RegXMM } > movss, 0xf310, None, CpuAVX, D|Modrm|Vex=3D3|Space0F|VexVVVV=3D1|VexW=3D= 1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXM= M } > -movss, 0xf30f10, None, CpuSSE, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSu= f|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } > +movss, 0xf30f10, None, CpuSSE, D|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N= o_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } > movups, 0x0f10, None, , D|Modrm||No_bSuf|No_wSuf= |No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } > mulps, 0x0f59, None, , Modrm|||No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, = RegXMM } > mulss, 0xf30f59, None, , Modrm|||No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|= RegXMM, RegXMM } > orps, 0x0f56, None, , Modrm|||C|No_bSu= f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex,= RegXMM } > -pavg, 0xfe0 | (3 * ), None, CpuSSE|Cpu3dnowA, Modrm|No_bSuf|= No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseI= ndex|RegMMX, RegMMX } > +pavg, 0xfe0 | (3 * ), None, CpuSSE|Cpu3dnowA, Modrm|No_bSuf|= No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Reg= MMX, RegMMX } > pavg, 0x660fe0 | (3 * ), None, , Modrm|||C|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Re= gXMM|Unspecified|BaseIndex, RegXMM } > pextrw, 0x660fc5, None, , Load|Modrm||No_bSuf= |No_wSuf|No_sSuf|No_ldSuf|IgnoreSize|NoRex64, { Imm8, RegXMM, Reg32|Reg64 } > pextrw, 0xfc5, None, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|= No_sSuf|No_ldSuf|NoRex64, { Imm8, RegMMX, Reg32|Reg64 } > pinsrw, 0x660fc4, None, , Modrm|||= No_bSuf|No_wSuf|No_sSuf|No_ldSuf|IgnoreSize|NoRex64, { Imm8, Reg32|Reg64, R= egXMM } > -pinsrw, 0x660fc4, None, , Modrm|||= No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IgnoreSize, { Imm8, Word|U= nspecified|BaseIndex, RegXMM } > +pinsrw, 0x660fc4, None, , Modrm|||= No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Word|Unspecified|= BaseIndex, RegXMM } > pinsrw, 0xfc4, None, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|= No_sSuf|No_ldSuf|NoRex64, { Imm8, Reg32|Reg64, RegMMX } > -pinsrw, 0xfc4, None, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|= No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Word|Unspecified|BaseIndex, RegMM= X } > +pinsrw, 0xfc4, None, CpuSSE|Cpu3dnowA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_= sSuf|No_qSuf|No_ldSuf, { Imm8, Word|Unspecified|BaseIndex, RegMMX } > pmaxsw, 0x660fee, None, , Modrm|||= C|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|Ba= seIndex, RegXMM } > -pmaxsw, 0xfee, None, CpuSSE|Cpu3dnowA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_= sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX= } > +pmaxsw, 0xfee, None, CpuSSE|Cpu3dnowA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_= sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } > pmaxub, 0x660fde, None, , Modrm|||= C|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|Ba= seIndex, RegXMM } > -pmaxub, 0xfde, None, CpuSSE|Cpu3dnowA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_= sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX= } > +pmaxub, 0xfde, None, CpuSSE|Cpu3dnowA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_= sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } > pminsw, 0x660fea, None, , Modrm|||= C|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|Ba= seIndex, RegXMM } > -pminsw, 0xfea, None, CpuSSE|Cpu3dnowA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_= sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX= } > +pminsw, 0xfea, None, CpuSSE|Cpu3dnowA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_= sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } > pminub, 0x660fda, None, , Modrm|||= C|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|Ba= seIndex, RegXMM } > -pminub, 0xfda, None, CpuSSE|Cpu3dnowA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_= sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX= } > +pminub, 0xfda, None, CpuSSE|Cpu3dnowA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_= sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } > pmovmskb, 0x660fd7, None, , Modrm||IgnoreSize= |No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegXMM, Reg32|Reg64 } > pmovmskb, 0xfd7, None, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSu= f|No_sSuf|No_ldSuf|NoRex64, { RegMMX, Reg32|Reg64 } > pmulhuw, 0x660fe4, None, , Modrm||= |C|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|B= aseIndex, RegXMM } > -pmulhuw, 0xfe4, None, CpuSSE|Cpu3dnowA, Modrm|No_bSuf|No_wSuf|No_lSuf|No= _sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMM= X } > +pmulhuw, 0xfe4, None, CpuSSE|Cpu3dnowA, Modrm|No_bSuf|No_wSuf|No_lSuf|No= _sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } > prefetchnta, 0xf18, 0, CpuSSE|Cpu3dnowA, Modrm|Anysize|IgnoreSize|No_bSu= f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { BaseIndex } > prefetcht0, 0xf18, 1, CpuSSE|Cpu3dnowA, Modrm|Anysize|IgnoreSize|No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { BaseIndex } > prefetcht1, 0xf18, 2, CpuSSE|Cpu3dnowA, Modrm|Anysize|IgnoreSize|No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { BaseIndex } > prefetcht2, 0xf18, 3, CpuSSE|Cpu3dnowA, Modrm|Anysize|IgnoreSize|No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { BaseIndex } > -psadbw, 0xff6, None, CpuSSE|Cpu3dnowA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_= sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX= } > +psadbw, 0xff6, None, CpuSSE|Cpu3dnowA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_= sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } > psadbw, 0x660ff6, None, , Modrm|||= C|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|Ba= seIndex, RegXMM } > -pshufw, 0xf70, None, CpuSSE|Cpu3dnowA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_= sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, Qword|Unspecified|BaseIndex|RegMMX, = RegMMX } > +pshufw, 0xf70, None, CpuSSE|Cpu3dnowA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_= sSuf|No_qSuf|No_ldSuf, { Imm8, Qword|Unspecified|BaseIndex|RegMMX, RegMMX } > rcpps, 0x0f53, None, , Modrm||No_bSuf|No_wSuf|No= _lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } > rcpss, 0xf30f53, None, , Modrm|||No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|= RegXMM, RegXMM } > rsqrtps, 0x0f52, None, , Modrm||No_bSuf|No_wSuf|= No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } > @@ -1142,7 +1142,7 @@ sfence, 0xfaef8, None, CpuSSE|Cpu3dnowA, > shufps, 0x0fc6, None, , Modrm|||No_bSu= f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|Base= Index, RegXMM } > sqrtps, 0x0f51, None, , Modrm||No_bSuf|No_wSuf|N= o_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } > sqrtss, 0xf30f51, None, , Modrm|||No_b= Suf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex= |RegXMM, RegXMM } > -stmxcsr, 0x0fae, 3, , Modrm||IgnoreSize|No_bSuf|= No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex } > +stmxcsr, 0x0fae, 3, , Modrm||No_bSuf|No_wSuf|No_= lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex } > subps, 0x0f5c, None, , Modrm|||No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, = RegXMM } > subss, 0xf30f5c, None, , Modrm|||No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|= RegXMM, RegXMM } > ucomiss, 0x0f2e, None, , Modrm||No_bSuf|No_wSuf|= No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, Reg= XMM } > @@ -1161,9 +1161,9 @@ cmpsd, 0xf20fc2, , > cmppd, 0x660fc2, None, , Modrm|||N= o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified= |BaseIndex, RegXMM } > cmpsd, 0xf20fc2, None, , Modrm|||N= o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Qword|Unspecified|= BaseIndex|RegXMM, RegXMM } > comisd, 0x660f2f, None, , Modrm||No_bSuf|No_w= Suf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM,= RegXMM } > -cvtpi2pd, 0x660f2a, None, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf= |No_qSuf|No_ldSuf|NoRex64, { RegMMX, RegXMM } > -cvtpi2pd, 0xf3e6, None, CpuAVX, Modrm|Vex|Space0F|VexW0|IgnoreSize|No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|Ba= seIndex, RegXMM } > -cvtpi2pd, 0x660f2a, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_l= Suf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex, RegXMM= } > +cvtpi2pd, 0x660f2a, None, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf= |No_qSuf|No_ldSuf, { RegMMX, RegXMM } > +cvtpi2pd, 0xf3e6, None, CpuAVX, Modrm|Vex|Space0F|VexW0|No_bSuf|No_wSuf|= No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, Re= gXMM } > +cvtpi2pd, 0x660f2a, None, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf= |No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM } > cvtsi2sd, 0xf20f2a, None, |CpuNo64, Modrm|IgnoreSize|||No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unsp= ecified|BaseIndex, RegXMM } > cvtsi2sd, 0xf22a, None, CpuAVX|Cpu64, Modrm|Vex=3D3|Space0F|VexVVVV=3D1|= IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SSE2AVX|ATTSyntax, { Reg32|Reg6= 4|Dword|Qword|Unspecified|BaseIndex, RegXMM } > cvtsi2sd, 0xf22a, None, CpuAVX|Cpu64, Modrm|Vex=3D3|Space0F|VexVVVV=3D1|= No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SSE2AVX|IntelSyntax, { Reg32|Reg64|Dword|Q= word|Unspecified|BaseIndex, RegXMM } > @@ -1176,17 +1176,17 @@ maxsd, 0xf20f5f, None, , > minpd, 0x660f5d, None, , Modrm|||N= o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseI= ndex, RegXMM } > minsd, 0xf20f5d, None, , Modrm|||N= o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIn= dex|RegXMM, RegXMM } > movapd, 0x660f28, None, , D|Modrm||No_bSuf|No= _wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, Reg= XMM } > -movhpd, 0x6616, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexW=3D1|Ign= oreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|U= nspecified|BaseIndex, RegXMM } > -movhpd, 0x6617, None, CpuAVX, Modrm|Vex|Space0F|VexW=3D1|IgnoreSize|No_b= Suf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Qword|Unspe= cified|BaseIndex } > -movhpd, 0x660f16, None, CpuSSE2, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_l= Suf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM } > -movlpd, 0x6612, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexW=3D1|Ign= oreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|U= nspecified|BaseIndex, RegXMM } > -movlpd, 0x6613, None, CpuAVX, Modrm|Vex|Space0F|VexW=3D1|IgnoreSize|No_b= Suf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Qword|Unspe= cified|BaseIndex } > -movlpd, 0x660f12, None, CpuSSE2, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_l= Suf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM } > +movhpd, 0x6616, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexW0|No_bSuf|No= _wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseInd= ex, RegXMM } > +movhpd, 0x6617, None, CpuAVX, Modrm|Vex|Space0F|VexW0|No_bSuf|No_wSuf|No= _lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseInd= ex } > +movhpd, 0x660f16, None, CpuSSE2, D|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf= |No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM } > +movlpd, 0x6612, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexW0|No_bSuf|No= _wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseInd= ex, RegXMM } > +movlpd, 0x6613, None, CpuAVX, Modrm|Vex|Space0F|VexW0|No_bSuf|No_wSuf|No= _lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseInd= ex } > +movlpd, 0x660f12, None, CpuSSE2, D|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf= |No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM } > movmskpd, 0x660f50, None, , Modrm||IgnoreSize= |No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegXMM, Reg32|Reg64 } > movntpd, 0x660f2b, None, , Modrm||No_bSuf|No_= wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIn= dex } > -movsd, 0xf210, None, CpuAVX, D|Modrm|Vex=3D3|Space0F|VexW=3D1|IgnoreSize= |No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecif= ied|BaseIndex, RegXMM } > +movsd, 0xf210, None, CpuAVX, D|Modrm|VexLIG|Space0F|VexW0|No_bSuf|No_wSu= f|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, = RegXMM } > movsd, 0xf210, None, CpuAVX, D|Modrm|Vex=3D3|Space0F|VexVVVV=3D1|VexW=3D= 1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXM= M } > -movsd, 0xf20f10, None, CpuSSE2, D|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|= No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } > +movsd, 0xf20f10, None, CpuSSE2, D|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|= No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } > movupd, 0x660f10, None, , D|Modrm||No_bSuf|No= _wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, Reg= XMM } > mulpd, 0x660f59, None, , Modrm|||N= o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseI= ndex, RegXMM } > mulsd, 0xf20f59, None, , Modrm|||N= o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIn= dex|RegXMM, RegXMM } > @@ -1200,21 +1200,21 @@ ucomisd, 0x660f2e, None, unpckhpd, 0x660f15, None, , Modrm|||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|Ba= seIndex, RegXMM } > unpcklpd, 0x660f14, None, , Modrm|||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|Ba= seIndex, RegXMM } > xorpd, 0x660f57, None, , Modrm|||C= |No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|Bas= eIndex, RegXMM } > -cvtdq2pd, 0xf30fe6, None, , Modrm||No_bSuf|No= _wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseInd= ex|RegXMM, RegXMM } > +cvtdq2pd, 0xf30fe6, None, , Modrm||No_bSuf|No= _wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXM= M, RegXMM } > cvtpd2dq, 0xf20fe6, None, , Modrm||No_bSuf|No= _wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, Reg= XMM } > cvtdq2ps, 0x0f5b, None, , Modrm||No_bSuf|No_w= Suf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXM= M } > cvtpd2pi, 0x660f2d, None, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf= |No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegMMX } > cvtpd2ps, 0x660f5a, None, , Modrm||No_bSuf|No= _wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, Reg= XMM } > -cvtps2pd, 0x0f5a, None, , Modrm||No_bSuf|No_w= Suf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex= |RegXMM, RegXMM } > +cvtps2pd, 0x0f5a, None, , Modrm||No_bSuf|No_w= Suf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM,= RegXMM } > cvtps2dq, 0x660f5b, None, , Modrm||No_bSuf|No= _wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, Reg= XMM } > -cvtsd2si, 0xf22d, None, CpuAVX, Modrm|Vex=3D3|Space0F|IgnoreSize|No_bSuf= |No_wSuf|No_sSuf|No_ldSuf|ToDword|SSE2AVX, { Qword|Unspecified|BaseIndex|Re= gXMM, Reg32|Reg64 } > -cvtsd2si, 0xf20f2d, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_s= Suf|No_ldSuf|ToDword, { Qword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } > -cvtsd2ss, 0xf20f5a, None, , Modrm|||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspeci= fied|BaseIndex|RegXMM, RegXMM } > -cvtss2sd, 0xf30f5a, None, , Modrm|||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IgnoreSize, { Dword|Unsp= ecified|BaseIndex|RegXMM, RegXMM } > +cvtsd2si, 0xf22d, None, CpuAVX, Modrm|VexLIG|Space0F|No_bSuf|No_wSuf|No_= sSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } > +cvtsd2si, 0xf20f2d, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_s= Suf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } > +cvtsd2ss, 0xf20f5a, None, , Modrm|||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|Bas= eIndex|RegXMM, RegXMM } > +cvtss2sd, 0xf30f5a, None, , Modrm|||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|Bas= eIndex|RegXMM, RegXMM } > > cvttpd2pi, 0x660f2c, None, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSu= f|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegMMX } > -cvttsd2si, 0xf22c, None, CpuAVX, Modrm|Vex=3D3|Space0F|IgnoreSize|No_bSu= f|No_wSuf|No_sSuf|No_ldSuf|ToDword|SSE2AVX, { Qword|Unspecified|BaseIndex|R= egXMM, Reg32|Reg64 } > -cvttsd2si, 0xf20f2c, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_= sSuf|No_ldSuf|ToDword, { Qword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } > +cvttsd2si, 0xf22c, None, CpuAVX, Modrm|VexLIG|Space0F|No_bSuf|No_wSuf|No= _sSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } > +cvttsd2si, 0xf20f2c, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_= sSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } > cvttpd2dq, 0x660fe6, None, , Modrm||No_bSuf|N= o_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, Re= gXMM } > cvttps2dq, 0xf30f5b, None, , Modrm||No_bSuf|N= o_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, Re= gXMM } > maskmovdqu, 0x660ff7, None, , Modrm||No_bSuf|= No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM } > @@ -1223,7 +1223,7 @@ movdqu, 0xf30f6f, None, > movdq2q, 0xf20fd6, None, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|= No_qSuf|No_ldSuf, { RegXMM, RegMMX } > movq2dq, 0xf30fd6, None, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|= No_qSuf|No_ldSuf, { RegMMX, RegXMM } > pmuludq, 0x660ff4, None, , Modrm||= |C|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|B= aseIndex, RegXMM } > -pmuludq, 0xff4, None, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_= qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } > +pmuludq, 0xff4, None, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_= qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } > pshufd, 0x660f70, None, , Modrm||No_bSuf|No_w= Suf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex,= RegXMM } > pshufhw, 0xf30f70, None, , Modrm||No_bSuf|No_= wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex= , RegXMM } > pshuflw, 0xf20f70, None, , Modrm||No_bSuf|No_= wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex= , RegXMM } > @@ -1245,7 +1245,7 @@ haddps, 0xf20f7c, None, > hsubpd, 0x660f7d, None, , Modrm|||= No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|Base= Index, RegXMM } > hsubps, 0xf20f7d, None, , Modrm|||= No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|Base= Index, RegXMM } > lddqu, 0xf20ff0, None, , Modrm||No_bSuf|No_wS= uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex, RegXM= M } > -movddup, 0xf20f12, None, , Modrm||No_bSuf|No_= wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseInde= x|RegXMM, RegXMM } > +movddup, 0xf20f12, None, , Modrm||No_bSuf|No_= wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM= , RegXMM } > movshdup, 0xf30f16, None, , Modrm||No_bSuf|No= _wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, Reg= XMM } > movsldup, 0xf30f12, None, , Modrm||No_bSuf|No= _wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, Reg= XMM } > > @@ -1276,17 +1276,17 @@ mwait, 0xf01c9, None, CpuSSE3, CheckRegS > // VMX instructions. > > vmcall, 0xf01c1, None, CpuVMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N= o_ldSuf, {} > -vmclear, 0x660fc7, 6, CpuVMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex } > +vmclear, 0x660fc7, 6, CpuVMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_q= Suf|No_ldSuf, { Qword|Unspecified|BaseIndex } > vmlaunch, 0xf01c2, None, CpuVMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf= |No_ldSuf, {} > vmresume, 0xf01c3, None, CpuVMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf= |No_ldSuf, {} > -vmptrld, 0xfc7, 6, CpuVMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_s= Suf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex } > -vmptrst, 0xfc7, 7, CpuVMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_s= Suf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex } > +vmptrld, 0xfc7, 6, CpuVMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf= |No_ldSuf, { Qword|Unspecified|BaseIndex } > +vmptrst, 0xfc7, 7, CpuVMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf= |No_ldSuf, { Qword|Unspecified|BaseIndex } > vmread, 0xf78, None, CpuVMX|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No= _sSuf|No_qSuf|No_ldSuf, { Reg32, Reg32|Unspecified|BaseIndex } > vmread, 0xf78, None, CpuVMX|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf= |No_ldSuf|NoRex64, { Reg64, Reg64|Qword|Unspecified|BaseIndex } > vmwrite, 0xf79, None, CpuVMX|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|N= o_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, Reg32 } > vmwrite, 0xf79, None, CpuVMX|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSu= f|No_ldSuf|NoRex64, { Reg64|Qword|Unspecified|BaseIndex, Reg64 } > vmxoff, 0xf01c4, None, CpuVMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N= o_ldSuf, {} > -vmxon, 0xf30fc7, 6, CpuVMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_= sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex } > +vmxon, 0xf30fc7, 6, CpuVMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu= f|No_ldSuf, { Qword|Unspecified|BaseIndex } > > // VMFUNC instruction > > @@ -1313,7 +1313,7 @@ invpcid, 0x660f3882, None, CpuINVPCID|Cp > $avx:CpuAVX:66:Vex128|VexW0|SSE2AVX:VexVVVV:RegXMM:Xmmword, + > $sse:CpuSSSE3:66:::RegXMM:Xmmword, + > - $mmx:CpuSSSE3::NoRex64::RegMMX:Qword> > + $mmx:CpuSSSE3::::RegMMX:Qword> > > phaddw, 0x0f3801, None, , Modrm|||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { ||Unspecified|BaseIndex, } > phaddd, 0x0f3802, None, , Modrm|||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { ||Unspecified|BaseIndex, } > @@ -1333,7 +1333,7 @@ pabsd, 0x0f381e, None, > // SSE4.1 instructions. > > > - > + > > blendp, 0x660f3a0c | , None, , Modrm|||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Im= m8, RegXMM|Unspecified|BaseIndex, RegXMM } > blendvp, 0x664a | , None, CpuAVX, Modrm|Vex|Space0F3A|VexVVV= V=3D1|VexW=3D1|VexSources=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ld= Suf|SSE2AVX, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } > @@ -1341,11 +1341,11 @@ blendvp, 0x664a | , None, Cp > blendvp, 0x660f3814 | , None, CpuSSE4_1, Modrm|No_bSuf|No_wS= uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Acc|Xmmword, RegXMM|Unspecified|Base= Index, RegXMM } > blendvp, 0x660f3814 | , None, CpuSSE4_1, Modrm|No_bSuf|No_wS= uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM= } > dpp, 0x660f3a40 | , None, , Modrm|||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8,= RegXMM|Unspecified|BaseIndex, RegXMM } > -extractps, 0x6617, None, CpuAVX, Modrm|Vex|Space0F3A|VexWIG|IgnoreSize|N= o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM, Re= g32|Dword|Unspecified|BaseIndex } > +extractps, 0x6617, None, CpuAVX, Modrm|Vex|Space0F3A|VexWIG|No_bSuf|No_w= Suf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM, Reg32|Dword|U= nspecified|BaseIndex } > extractps, 0x6617, None, CpuAVX|Cpu64, RegMem|Vex|Space0F3A|VexWIG|No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM, Reg64 = } > extractps, 0x660f3a17, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf= |No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|= BaseIndex } > extractps, 0x660f3a17, None, CpuSSE4_1|Cpu64, RegMem|No_bSuf|No_wSuf|No_= lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg64 } > -insertps, 0x660f3a21, None, , Modrm|IgnoreSize|||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8= , Dword|Unspecified|BaseIndex|RegXMM, RegXMM } > +insertps, 0x660f3a21, None, , Modrm|||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|Uns= pecified|BaseIndex|RegXMM, RegXMM } > movntdqa, 0x660f382a, None, , Modrm||No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseInde= x, RegXMM } > mpsadbw, 0x660f3a42, None, , Modrm|||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Uns= pecified|BaseIndex, RegXMM } > packusdw, 0x660f382b, None, , Modrm|||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecif= ied|BaseIndex, RegXMM } > @@ -1356,7 +1356,7 @@ pblendvb, 0x660f3810, None, CpuSSE4_1, M > pblendw, 0x660f3a0e, None, , Modrm|||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Uns= pecified|BaseIndex, RegXMM } > pcmpeqq, 0x660f3829, None, , Modrm|||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecifi= ed|BaseIndex, RegXMM } > pextr, 0x660f3a14 | , None, , RegMem||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IgnoreSize|NoRex64= , { Imm8, RegXMM, Reg32|Reg64 } > -pextr, 0x660f3a14 | , None, , Modrm||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IgnoreSize, { Imm8,= RegXMM, |Unspecified|BaseIndex } > +pextr, 0x660f3a14 | , None, , Modrm||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, |Unspecified|BaseIndex } > pextrd, 0x660f3a16, None, , Modrm||No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IgnoreSize, { Imm8, RegXMM, Reg32= |Unspecified|BaseIndex } > pextrq, 0x6616, None, CpuAVX|Cpu64, Modrm|Vex|Space0F3A|VexW1|No_bSuf|No= _wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM, Reg64|Unspe= cified|BaseIndex } > pextrq, 0x660f3a16, None, CpuSSE4_1|Cpu64, Modrm|Size64|No_bSuf|No_wSuf|= No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg64|Unspecified|BaseInd= ex } > @@ -1374,23 +1374,23 @@ pminsb, 0x660f3838, None, pminsd, 0x660f3839, None, , Modrm|||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecifie= d|BaseIndex, RegXMM } > pminud, 0x660f383b, None, , Modrm|||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecifie= d|BaseIndex, RegXMM } > pminuw, 0x660f383a, None, , Modrm|||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecifie= d|BaseIndex, RegXMM } > -pmovsxbw, 0x660f3820, None, , Modrm||No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|Ba= seIndex|RegXMM, RegXMM } > -pmovsxbd, 0x660f3821, None, , Modrm||No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IgnoreSize, { Dword|Unspecified= |BaseIndex|RegXMM, RegXMM } > -pmovsxbq, 0x660f3822, None, , Modrm||No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IgnoreSize, { Word|Unspecified|= BaseIndex|RegXMM, RegXMM } > -pmovsxwd, 0x660f3823, None, , Modrm||No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|Ba= seIndex|RegXMM, RegXMM } > -pmovsxwq, 0x660f3824, None, , Modrm||No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IgnoreSize, { Dword|Unspecified= |BaseIndex|RegXMM, RegXMM } > -pmovsxdq, 0x660f3825, None, , Modrm||No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|Ba= seIndex|RegXMM, RegXMM } > -pmovzxbw, 0x660f3830, None, , Modrm||No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|Ba= seIndex|RegXMM, RegXMM } > -pmovzxbd, 0x660f3831, None, , Modrm||No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IgnoreSize, { Dword|Unspecified= |BaseIndex|RegXMM, RegXMM } > -pmovzxbq, 0x660f3832, None, , Modrm||No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IgnoreSize, { Word|Unspecified|= BaseIndex|RegXMM, RegXMM } > -pmovzxwd, 0x660f3833, None, , Modrm||No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|Ba= seIndex|RegXMM, RegXMM } > -pmovzxwq, 0x660f3834, None, , Modrm||No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IgnoreSize, { Dword|Unspecified= |BaseIndex|RegXMM, RegXMM } > -pmovzxdq, 0x660f3835, None, , Modrm||No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|Ba= seIndex|RegXMM, RegXMM } > +pmovsxbw, 0x660f3820, None, , Modrm||No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|= RegXMM, RegXMM } > +pmovsxbd, 0x660f3821, None, , Modrm||No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|= RegXMM, RegXMM } > +pmovsxbq, 0x660f3822, None, , Modrm||No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex|R= egXMM, RegXMM } > +pmovsxwd, 0x660f3823, None, , Modrm||No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|= RegXMM, RegXMM } > +pmovsxwq, 0x660f3824, None, , Modrm||No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|= RegXMM, RegXMM } > +pmovsxdq, 0x660f3825, None, , Modrm||No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|= RegXMM, RegXMM } > +pmovzxbw, 0x660f3830, None, , Modrm||No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|= RegXMM, RegXMM } > +pmovzxbd, 0x660f3831, None, , Modrm||No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|= RegXMM, RegXMM } > +pmovzxbq, 0x660f3832, None, , Modrm||No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex|R= egXMM, RegXMM } > +pmovzxwd, 0x660f3833, None, , Modrm||No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|= RegXMM, RegXMM } > +pmovzxwq, 0x660f3834, None, , Modrm||No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|= RegXMM, RegXMM } > +pmovzxdq, 0x660f3835, None, , Modrm||No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|= RegXMM, RegXMM } > pmuldq, 0x660f3828, None, , Modrm|||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecifie= d|BaseIndex, RegXMM } > pmulld, 0x660f3840, None, , Modrm|||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecifie= d|BaseIndex, RegXMM } > ptest, 0x660f3817, None, , Modrm||No_bSuf|= No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, R= egXMM } > roundp, 0x660f3a08 | , None, , Modrm||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Un= specified|BaseIndex, RegXMM } > -rounds, 0x660f3a0a | , None, , Modrm|||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|, { Imm8, |Unspecified|BaseIndex|RegXMM, RegXMM } > +rounds, 0x660f3a0a | , None, , Modrm|||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Im= m8, |Unspecified|BaseIndex|RegXMM, RegXMM } > > // SSE4.2 instructions. > > @@ -1484,8 +1484,8 @@ vandp, 0x54, None, CpuAVX, > vblendp, 0x660c | , None, CpuAVX, Modrm|Vex|Space0F3A|VexVVV= V|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { I= mm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } > vblendvp, 0x664a | , None, CpuAVX, Modrm|Vex|Space0F3A|VexVV= VV|VexW0|VexSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu= f|No_ldSuf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|Re= gYMM, RegXMM|RegYMM } > vbroadcastf128, 0x661a, None, CpuAVX, Modrm|Vex=3D2|Space0F38|VexW=3D1|N= o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|Base= Index, RegYMM } > -vbroadcastsd, 0x6619, None, CpuAVX, Modrm|Vex=3D2|Space0F38|VexW=3D1|Ign= oreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecifi= ed|BaseIndex, RegYMM } > -vbroadcastss, 0x6618, None, CpuAVX, Modrm|Vex|Space0F38|VexW=3D1|IgnoreS= ize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|B= aseIndex, RegXMM|RegYMM } > +vbroadcastsd, 0x6619, None, CpuAVX, Modrm|Vex256|Space0F38|VexW0|No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, R= egYMM } > +vbroadcastss, 0x6618, None, CpuAVX, Modrm|Vex128|Space0F38|VexW0|No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, R= egXMM|RegYMM } > vcmpp, 0xc2, 0x, CpuAVX, Modrm||= Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_= qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM,= RegXMM|RegYMM } > vcmps, 0xc2, 0x, CpuAVX, Modrm||= VexLIG|Space0F|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ld= Suf|ImmExt, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } > vcmpp, 0xc2, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG= |CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Uns= pecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } > @@ -1499,22 +1499,20 @@ vcvtpd2ps, 0x665a, None, CpuAVX, Mod > vcvtps2dq, 0x665b, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|N= o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|Re= gXMM|RegYMM, RegXMM|RegYMM } > vcvtps2pd, 0x5a, None, CpuAVX, Modrm|Vex128|Space0F|VexWIG|No_bSuf|No_wS= uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, = RegXMM } > vcvtps2pd, 0x5a, None, CpuAVX, Modrm|Vex256|Space0F|VexWIG|No_bSuf|No_wS= uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegYMM= } > -vcvtsd2si, 0xf22d, None, CpuAVX, Modrm|Vex=3D3|Space0F|IgnoreSize|No_bSu= f|No_wSuf|No_sSuf|No_ldSuf|ToDword, { Qword|Unspecified|BaseIndex|RegXMM, R= eg32|Reg64 } > +vcvts2si, 0x2d, None, CpuAVX, Modrm|VexLIG|Space0F|No_bSuf|= No_wSuf|No_sSuf|No_ldSuf, { |Unspecified|BaseIndex|RegXMM, Reg32|R= eg64 } > vcvtsd2ss, 0xf25a, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexVVVV|VexWIG|No= _bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseInd= ex|RegXMM, RegXMM, RegXMM } > vcvtsi2s, 0x2a, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|= IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ATTSyntax, { Reg32|Reg64|Unspec= ified|BaseIndex, RegXMM, RegXMM } > vcvtsi2s, 0x2a, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|= No_bSuf|No_wSuf|No_sSuf|No_ldSuf|IntelSyntax, { Reg32|Reg64|Unspecified|Bas= eIndex, RegXMM, RegXMM } > vcvtss2sd, 0xf35a, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexVVVV|VexWIG|No= _bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseInd= ex|RegXMM, RegXMM, RegXMM } > -vcvtss2si, 0xf32d, None, CpuAVX, Modrm|Vex=3D3|Space0F|No_bSuf|No_wSuf|N= o_sSuf|No_ldSuf|ToQword, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 = } > vcvttpd2dq, 0x66e6, None, CpuAVX, Modrm||Space0F|VexWIG|No_b= Suf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|, { , RegXM= M } > vcvttps2dq, 0xf35b, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|No_bSuf|No_wS= uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM,= RegXMM|RegYMM } > -vcvttsd2si, 0xf22c, None, CpuAVX, Modrm|Vex=3D3|Space0F|IgnoreSize|No_bS= uf|No_wSuf|No_sSuf|No_ldSuf|ToDword, { Qword|Unspecified|BaseIndex|RegXMM, = Reg32|Reg64 } > -vcvttss2si, 0xf32c, None, CpuAVX, Modrm|Vex=3D3|Space0F|No_bSuf|No_wSuf|= No_sSuf|No_ldSuf|ToQword, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64= } > +vcvtts2si, 0x2c, None, CpuAVX, Modrm|VexLIG|Space0F|No_bSuf= |No_wSuf|No_sSuf|No_ldSuf, { |Unspecified|BaseIndex|RegXMM, Reg32|= Reg64 } > vdivp, 0x5e, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG= |CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecifi= ed|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } > vdivs, 0x5e, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|Vex= WIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { |Unspecifi= ed|BaseIndex|RegXMM, RegXMM, RegXMM } > vdppd, 0x6641, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=3D1|VexWIG|No_b= Suf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex= |RegXMM, RegXMM, RegXMM } > vdpps, 0x6640, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=3D1|VexWIG|Chec= kRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecif= ied|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } > vextractf128, 0x6619, None, CpuAVX, Modrm|Vex=3D2|Space0F3A|VexW=3D1|No_= bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, Unspecified|= BaseIndex|RegXMM } > -vextractps, 0x6617, None, CpuAVX, Modrm|Vex|Space0F3A|VexWIG|IgnoreSize|= No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Dwo= rd|Unspecified|BaseIndex } > +vextractps, 0x6617, None, CpuAVX, Modrm|Vex|Space0F3A|VexWIG|No_bSuf|No_= wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Dword|Unspecif= ied|BaseIndex } > vextractps, 0x6617, None, CpuAVX|Cpu64, RegMem|Vex|Space0F3A|VexWIG|No_b= Suf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg64 } > vhaddpd, 0x667c, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|Chec= kRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|Ba= seIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } > vhaddps, 0xf27c, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|Chec= kRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|Ba= seIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } > @@ -1523,7 +1521,7 @@ vhsubps, 0xf27d, None, CpuAVX, Modrm|Vex > vinsertf128, 0x6618, None, CpuAVX, Modrm|Vex=3D2|Space0F3A|VexVVVV=3D1|V= exW=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecifi= ed|BaseIndex|RegXMM, RegYMM, RegYMM } > vinsertps, 0x6621, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|No_b= Suf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|Unspecified|Bas= eIndex|RegXMM, RegXMM, RegXMM } > vlddqu, 0xf2f0, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|No_b= Suf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Ymmword|Unspecified= |BaseIndex, RegXMM|RegYMM } > -vldmxcsr, 0xae, 2, CpuAVX, Modrm|Vex128|Space0F|VexWIG|IgnoreSize|No_bSu= f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex } > +vldmxcsr, 0xae, 2, CpuAVX, Modrm|Vex128|Space0F|VexWIG|No_bSuf|No_wSuf|N= o_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex } > vmaskmovdqu, 0x66f7, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|No_bSuf|No_w= Suf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM } > vmaskmovp, 0x662e | , None, CpuAVX, Modrm|Vex|Space0F38|VexV= VVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { = RegXMM|RegYMM, RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex } > vmaskmovp, 0x662c | , None, CpuAVX, Modrm|Vex|Space0F38|VexV= VVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { = Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } > @@ -1537,26 +1535,26 @@ vmovap, 0x28, None, CpuAVX, > // by Intel AVX spec). To avoid extra template in gcc x86 backend and > // support assembler for AMD64, we accept 64bit operand on vmovd so > // that we can use one template for both SSE and AVX instructions. > -vmovd, 0x666e, None, CpuAVX, D|Modrm|Vex=3D1|Space0F|IgnoreSize|No_bSuf|= No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, Re= gXMM } > +vmovd, 0x666e, None, CpuAVX, D|Modrm|Vex=3D1|Space0F|No_bSuf|No_wSuf|No_= lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, RegXMM } > vmovd, 0x667e, None, CpuAVX|Cpu64, D|RegMem|Vex=3D1|Space0F|VexW=3D2|No_= bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { RegXMM, Reg64 } > vmovddup, 0xf212, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|No_bSuf|No_wSuf= |No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, Re= gXMM } > vmovddup, 0xf212, None, CpuAVX, Modrm|Vex=3D2|Space0F|VexWIG|No_bSuf|No_= wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegY= MM } > vmovdqa, 0x666f, None, CpuAVX, D|Modrm|Vex|Space0F|VexWIG|CheckRegSize|N= o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|Re= gXMM|RegYMM, RegXMM|RegYMM } > vmovdqu, 0xf36f, None, CpuAVX, D|Modrm|Vex|Space0F|VexWIG|CheckRegSize|N= o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|Re= gXMM|RegYMM, RegXMM|RegYMM } > vmovhlps, 0x12, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM } > -vmovhp, 0x16, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWI= G|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unsp= ecified|BaseIndex, RegXMM, RegXMM } > -vmovhp, 0x17, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|Ignore= Size|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unsp= ecified|BaseIndex } > +vmovhp, 0x16, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWI= G|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|Bas= eIndex, RegXMM, RegXMM } > +vmovhp, 0x17, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|No_bSu= f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|Bas= eIndex } > vmovlhps, 0x16, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM } > -vmovlp, 0x12, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWI= G|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unsp= ecified|BaseIndex, RegXMM, RegXMM } > -vmovlp, 0x13, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|Ignore= Size|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unsp= ecified|BaseIndex } > +vmovlp, 0x12, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWI= G|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|Bas= eIndex, RegXMM, RegXMM } > +vmovlp, 0x13, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|No_bSu= f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|Bas= eIndex } > vmovmskp, 0x50, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|No_b= Suf|No_wSuf|No_sSuf|No_ldSuf, { RegXMM|RegYMM, Reg32|Reg64 } > vmovntdq, 0x66e7, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|No= _bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Xmmword|Ym= mword|Unspecified|BaseIndex } > vmovntdqa, 0x662a, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexWIG|Chec= kRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Ymmwor= d|Unspecified|BaseIndex, RegXMM|RegYMM } > vmovntp, 0x2b, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|Check= RegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, = Xmmword|Ymmword|Unspecified|BaseIndex } > vmovq, 0xf37e, None, CpuAVX, Load|Modrm|Vex=3D1|Space0F|VexWIG|No_bSuf|N= o_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegX= MM, RegXMM } > vmovq, 0x66d6, None, CpuAVX, Modrm|Vex=3D1|Space0F|VexWIG|No_bSuf|No_wSu= f|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|R= egXMM } > -vmovq, 0x666e, None, CpuAVX|Cpu64, D|Modrm|Vex=3D1|Space0F|VexW=3D2|Igno= reSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64|Uns= pecified|BaseIndex, RegXMM } > -vmovs, 0x10, None, CpuAVX, D|Modrm|VexLIG|Space0F|VexWIG|Ig= noreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { |Unsp= ecified|BaseIndex, RegXMM } > +vmovq, 0x666e, None, CpuAVX|Cpu64, D|Modrm|Vex=3D1|Space0F|VexW=3D2|No_b= Suf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64|Unspecified|Ba= seIndex, RegXMM } > +vmovs, 0x10, None, CpuAVX, D|Modrm|VexLIG|Space0F|VexWIG|No= _bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { |Unspecified|Bas= eIndex, RegXMM } > vmovs, 0x10, None, CpuAVX, D|Modrm|VexLIG|Space0F|VexVVVV|V= exWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, R= egXMM } > vmovshdup, 0xf316, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|N= o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|Re= gXMM|RegYMM, RegXMM|RegYMM } > vmovsldup, 0xf312, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|N= o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|Re= gXMM|RegYMM, RegXMM|RegYMM } > @@ -1692,7 +1690,7 @@ vrsqrtss, 0xf352, None, CpuAVX, Modrm|Ve > vshufp, 0xc6, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWI= G|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Un= specified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } > vsqrtp, 0x51, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckR= egSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|Base= Index|RegXMM|RegYMM, RegXMM|RegYMM } > vsqrts, 0x51, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|Ve= xWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { |Unspecif= ied|BaseIndex|RegXMM, RegXMM, RegXMM } > -vstmxcsr, 0xae, 3, CpuAVX, Modrm|Vex128|Space0F|VexWIG|IgnoreSize|No_bSu= f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex } > +vstmxcsr, 0xae, 3, CpuAVX, Modrm|Vex128|Space0F|VexWIG|No_bSuf|No_wSuf|N= o_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex } > vsubp, 0x5c, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG= |CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecifi= ed|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } > vsubs, 0x5c, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|Vex= WIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { |Unspecifi= ed|BaseIndex|RegXMM, RegXMM, RegXMM } > vtestp, 0x660e | , None, CpuAVX, Modrm|Vex|Space0F38|VexW0|C= heckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified= |BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } > @@ -1889,8 +1887,8 @@ vpshl, 0x94 | , None, CpuX > > llwpcb, 0x12, 0, CpuLWP, Modrm|SpaceXOP09|No_bSuf|No_wSuf|No_lSuf|No_sSu= f|No_qSuf|No_ldSuf|Vex, { Reg32|Reg64 } > slwpcb, 0x12, 1, CpuLWP, Modrm|SpaceXOP09|No_bSuf|No_wSuf|No_lSuf|No_sSu= f|No_qSuf|No_ldSuf|Vex, { Reg32|Reg64 } > -lwpval, 0x12, 1, CpuLWP, Modrm|SpaceXOP0A|IgnoreSize|No_bSuf|No_wSuf|No_= lSuf|No_sSuf|No_qSuf|No_ldSuf|VexVVVV=3D3|Vex, { Imm32|Imm32S, Reg32|Unspec= ified|BaseIndex, Reg32|Reg64 } > -lwpins, 0x12, 0, CpuLWP, Modrm|SpaceXOP0A|IgnoreSize|No_bSuf|No_wSuf|No_= lSuf|No_sSuf|No_qSuf|No_ldSuf|VexVVVV=3D3|Vex, { Imm32|Imm32S, Reg32|Unspec= ified|BaseIndex, Reg32|Reg64 } > +lwpval, 0x12, 1, CpuLWP, Modrm|SpaceXOP0A|No_bSuf|No_wSuf|No_lSuf|No_sSu= f|No_qSuf|No_ldSuf|VexVVVV=3D3|Vex, { Imm32|Imm32S, Reg32|Unspecified|BaseI= ndex, Reg32|Reg64 } > +lwpins, 0x12, 0, CpuLWP, Modrm|SpaceXOP0A|No_bSuf|No_wSuf|No_lSuf|No_sSu= f|No_qSuf|No_ldSuf|VexVVVV=3D3|Vex, { Imm32|Imm32S, Reg32|Unspecified|BaseI= ndex, Reg32|Reg64 } > > // BMI instructions > > @@ -1918,30 +1916,30 @@ tzmsk, 0x01, 4, CpuTBM, Modrm|CheckRegSi > prefetch, 0xf0d, 0, Cpu3dnow|CpuPRFCHW, Modrm|Anysize|IgnoreSize|No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { BaseIndex } > prefetchw, 0xf0d, 1, Cpu3dnow|CpuPRFCHW, Modrm|Anysize|IgnoreSize|No_bSu= f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { BaseIndex } > femms, 0xf0e, None, Cpu3dnow, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No= _ldSuf, {} > -pavgusb, 0xf0f, 0xbf, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf|NoRex64|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX= } > -pf2id, 0xf0f, 0x1d, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_q= Suf|No_ldSuf|NoRex64|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } > -pf2iw, 0xf0f, 0x1c, Cpu3dnowA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_= qSuf|No_ldSuf|NoRex64|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX = } > -pfacc, 0xf0f, 0xae, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_q= Suf|No_ldSuf|NoRex64|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } > -pfadd, 0xf0f, 0x9e, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_q= Suf|No_ldSuf|NoRex64|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } > -pfcmpeq, 0xf0f, 0xb0, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf|NoRex64|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX= } > -pfcmpge, 0xf0f, 0x90, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf|NoRex64|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX= } > -pfcmpgt, 0xf0f, 0xa0, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf|NoRex64|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX= } > -pfmax, 0xf0f, 0xa4, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_q= Suf|No_ldSuf|NoRex64|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } > -pfmin, 0xf0f, 0x94, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_q= Suf|No_ldSuf|NoRex64|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } > -pfmul, 0xf0f, 0xb4, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_q= Suf|No_ldSuf|NoRex64|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } > -pfnacc, 0xf0f, 0x8a, Cpu3dnowA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf|NoRex64|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX= } > -pfpnacc, 0xf0f, 0x8e, Cpu3dnowA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N= o_qSuf|No_ldSuf|NoRex64|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMM= X } > -pfrcp, 0xf0f, 0x96, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_q= Suf|No_ldSuf|NoRex64|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } > -pfrcpit1, 0xf0f, 0xa6, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N= o_qSuf|No_ldSuf|NoRex64|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMM= X } > -pfrcpit2, 0xf0f, 0xb6, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N= o_qSuf|No_ldSuf|NoRex64|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMM= X } > -pfrsqit1, 0xf0f, 0xa7, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N= o_qSuf|No_ldSuf|NoRex64|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMM= X } > -pfrsqrt, 0xf0f, 0x97, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf|NoRex64|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX= } > -pfsub, 0xf0f, 0x9a, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_q= Suf|No_ldSuf|NoRex64|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } > -pfsubr, 0xf0f, 0xaa, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_= qSuf|No_ldSuf|NoRex64|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX = } > -pi2fd, 0xf0f, 0x0d, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_q= Suf|No_ldSuf|NoRex64|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } > -pi2fw, 0xf0f, 0x0c, Cpu3dnowA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_= qSuf|No_ldSuf|NoRex64|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX = } > -pmulhrw, 0xf0f, 0xb7, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf|NoRex64|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX= } > -pswapd, 0xf0f, 0xbb, Cpu3dnowA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf|NoRex64|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX= } > +pavgusb, 0xf0f, 0xbf, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } > +pf2id, 0xf0f, 0x1d, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_q= Suf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } > +pf2iw, 0xf0f, 0x1c, Cpu3dnowA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_= qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } > +pfacc, 0xf0f, 0xae, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_q= Suf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } > +pfadd, 0xf0f, 0x9e, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_q= Suf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } > +pfcmpeq, 0xf0f, 0xb0, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } > +pfcmpge, 0xf0f, 0x90, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } > +pfcmpgt, 0xf0f, 0xa0, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } > +pfmax, 0xf0f, 0xa4, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_q= Suf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } > +pfmin, 0xf0f, 0x94, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_q= Suf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } > +pfmul, 0xf0f, 0xb4, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_q= Suf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } > +pfnacc, 0xf0f, 0x8a, Cpu3dnowA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } > +pfpnacc, 0xf0f, 0x8e, Cpu3dnowA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N= o_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } > +pfrcp, 0xf0f, 0x96, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_q= Suf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } > +pfrcpit1, 0xf0f, 0xa6, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N= o_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } > +pfrcpit2, 0xf0f, 0xb6, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N= o_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } > +pfrsqit1, 0xf0f, 0xa7, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N= o_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } > +pfrsqrt, 0xf0f, 0x97, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } > +pfsub, 0xf0f, 0x9a, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_q= Suf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } > +pfsubr, 0xf0f, 0xaa, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_= qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } > +pi2fd, 0xf0f, 0x0d, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_q= Suf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } > +pi2fw, 0xf0f, 0x0c, Cpu3dnowA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_= qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } > +pmulhrw, 0xf0f, 0xb7, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } > +pswapd, 0xf0f, 0xbb, Cpu3dnowA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } > > // AMD extensions. > syscall, 0xf05, None, CpuSYSCALL, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu= f|No_ldSuf, {} > @@ -1967,8 +1965,8 @@ vmsave, 0xf01db, None, CpuSVME, AddrPref > > > // SSE4a instructions > -movntsd, 0xf20f2b, None, CpuSSE4a, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_l= Suf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex } > -movntss, 0xf30f2b, None, CpuSSE4a, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_l= Suf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex } > +movntsd, 0xf20f2b, None, CpuSSE4a, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf= |No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex } > +movntss, 0xf30f2b, None, CpuSSE4a, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf= |No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex } > extrq, 0x660f78, 0, CpuSSE4a, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_q= Suf|No_ldSuf, { Imm8, Imm8, RegXMM } > extrq, 0x660f79, None, CpuSSE4a, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N= o_qSuf|No_ldSuf, { RegXMM, RegXMM } > insertq, 0xf20f79, None, CpuSSE4a, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf= |No_qSuf|No_ldSuf, { RegXMM, RegXMM } > @@ -2166,8 +2164,8 @@ vcvtps2pd, 0x5A, None, CpuAVX512F, Modrm > > vcvtps2ph, 0x661D, None, CpuAVX512F, Modrm|EVex512|MaskingMorZ|Space0F3A= |VexW0|Disp8MemShift=3D5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|S= AE, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } > > -vcvtsd2si, 0xF22D, None, CpuAVX512F, Modrm|EVexLIG|Space0F|Disp8MemShift= =3D3|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToDword|StaticRounding|SAE= , { RegXMM|Qword|Unspecified|BaseIndex, Reg32|Reg64 } > -vcvtsd2usi, 0xF279, None, CpuAVX512F, Modrm|EVexLIG|Space0F|Disp8MemShif= t=3D3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ToDword|S= taticRounding|SAE, { RegXMM|Qword|Unspecified|BaseIndex, Reg32|Reg64 } > +vcvts2si, 0x2d, None, , Modrm|EVexLIG|= |Disp8MemShift|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|StaticRounding|SAE, { RegXM= M||Unspecified|BaseIndex, Reg32|Reg64 } > +vcvts2usi, 0x79, None, , Modrm|EVexLIG||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRoun= ding|SAE, { RegXMM||Unspecified|BaseIndex, Reg32|Reg64 } > > vcvtsd2ss, 0xF25A, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0F|V= exVVVV|VexW1|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_l= dSuf|StaticRounding|SAE, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegX= MM } > > @@ -2187,20 +2185,14 @@ vcvtusi2ss, 0xF37B, None, CpuAVX512F, Mo > > vcvtss2sd, 0xF35A, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0F|V= exVVVV|VexW0|Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_l= dSuf|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } > > -vcvtss2si, 0xF32D, None, CpuAVX512F, Modrm|EVexLIG|Space0F|Disp8MemShift= =3D2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToQword|StaticRounding|SAE, { RegXMM|= Dword|Unspecified|BaseIndex, Reg32|Reg64 } > -vcvtss2usi, 0xF379, None, CpuAVX512F, Modrm|EVexLIG|Space0F|Disp8MemShif= t=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ToQword|StaticRoundi= ng|SAE, { RegXMM|Dword|Unspecified|BaseIndex, Reg32|Reg64 } > - > vcvttpd2dq, 0x66e6, None, CpuAVX512F|, Modrm||Maskin= g=3D3|Space0F|VexW1|Broadcast|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ld= Suf|, { |Qword, } > vcvttpd2udq, 0x78, None, CpuAVX512F|, Modrm||Masking= =3D3|Space0F|VexW1|Broadcast|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS= uf|, { |Qword, } > > vcvttps2dq, 0xF35B, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexW0|Br= oadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N= o_ldSuf|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|Reg= YMM|RegZMM } > vcvttps2udq, 0x78, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexW0|Bro= adcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No= _ldSuf|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegY= MM|RegZMM } > > -vcvttsd2si, 0xF22C, None, CpuAVX512F, Modrm|EVexLIG|Space0F|Disp8MemShif= t=3D3|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToDword|SAE, { RegXMM|Qwo= rd|Unspecified|BaseIndex, Reg32|Reg64 } > -vcvttsd2usi, 0xF278, None, CpuAVX512F, Modrm|EVexLIG|Space0F|Disp8MemShi= ft=3D3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ToDword|= SAE, { RegXMM|Qword|Unspecified|BaseIndex, Reg32|Reg64 } > - > -vcvttss2si, 0xF32C, None, CpuAVX512F, Modrm|EVexLIG|Space0F|Disp8MemShif= t=3D2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToQword|SAE, { RegXMM|Dword|Unspecif= ied|BaseIndex, Reg32|Reg64 } > -vcvttss2usi, 0xF378, None, CpuAVX512F, Modrm|EVexLIG|Space0F|Disp8MemShi= ft=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ToQword|SAE, { RegX= MM|Dword|Unspecified|BaseIndex, Reg32|Reg64 } > +vcvtts2si, 0x2c, None, , Modrm|EVexLIG||Disp8MemShift|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SAE, { RegXMM||U= nspecified|BaseIndex, Reg32|Reg64 } > +vcvtts2usi, 0x78, None, , Modrm|EVexLIG||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Re= gXMM||Unspecified|BaseIndex, Reg32|Reg64 } > > vcvtudq2ps, 0xF27A, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexW0|Br= oadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N= o_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIn= dex, RegXMM|RegYMM|RegZMM } > > @@ -2216,7 +2208,7 @@ vextracti32x4, 0x6639, None, CpuAVX512F, > vextractf64x4, 0x661B, None, CpuAVX512F, Modrm|EVex=3D1|MaskingMorZ|Spac= e0F3A|VexW=3D2|Disp8MemShift=3D5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No= _ldSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } > vextracti64x4, 0x663B, None, CpuAVX512F, Modrm|EVex=3D1|MaskingMorZ|Spac= e0F3A|VexW=3D2|Disp8MemShift=3D5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No= _ldSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } > > -vextractps, 0x6617, None, CpuAVX512F, Modrm|EVex128|Space0F3A|VexWIG|Dis= p8MemShift=3D2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,= { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex } > +vextractps, 0x6617, None, CpuAVX512F, Modrm|EVex128|Space0F3A|VexWIG|Dis= p8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Re= gXMM, Reg32|Dword|Unspecified|BaseIndex } > vextractps, 0x6617, None, CpuAVX512F|Cpu64, RegMem|EVex128|Space0F3A|Vex= WIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg64= } > > vfixupimmp, 0x6654, None, CpuAVX512F, Modrm|Masking=3D3|Space0F3A|Ve= xVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf= |No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM||Unspe= cified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > @@ -2274,7 +2266,7 @@ vmovap, 0x28, None, CpuAVX5 > vmovntp, 0x2B, None, CpuAVX512F, Modrm|Space0F||Di= sp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {= RegXMM|RegYMM|RegZMM, XMMword|YMMword|ZMMword|Unspecified|BaseIndex } > vmovup, 0x10, None, CpuAVX512F, D|Modrm|MaskingMorZ|Space0F= ||Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu= f|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|Reg= ZMM } > > -vmovd, 0x666E, None, CpuAVX512F, D|Modrm|EVex=3D2|Space0F|Disp8MemShift= =3D2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|U= nspecified|BaseIndex, RegXMM } > +vmovd, 0x666E, None, CpuAVX512F, D|Modrm|EVex=3D2|Space0F|Disp8MemShift= =3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|= BaseIndex, RegXMM } > > vmovddup, 0xF212, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexW=3D2|D= isp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, = { RegYMM|RegZMM|Unspecified|BaseIndex, RegYMM|RegZMM } > > @@ -2287,16 +2279,16 @@ vmovdqu64, 0xF36F, None, CpuAVX512F, D|M > vmovhlps, 0x12, None, CpuAVX512F, Modrm|EVex=3D4|Space0F|VexVVVV=3D1|Vex= W=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, R= egXMM } > vmovlhps, 0x16, None, CpuAVX512F, Modrm|EVex=3D4|Space0F|VexVVVV=3D1|Vex= W=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, R= egXMM } > > -vmovhp, 0x16, None, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVV= VV||Disp8MemShift=3D3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N= o_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM, RegXMM } > -vmovhp, 0x17, None, CpuAVX512F, Modrm|EVexLIG|Space0F||Disp8MemShift=3D3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N= o_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex } > -vmovlp, 0x12, None, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVV= VV||Disp8MemShift=3D3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N= o_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM, RegXMM } > -vmovlp, 0x13, None, CpuAVX512F, Modrm|EVexLIG|Space0F||Disp8MemShift=3D3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N= o_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex } > +vmovhp, 0x16, None, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVV= VV||Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_l= dSuf, { Qword|Unspecified|BaseIndex, RegXMM, RegXMM } > +vmovhp, 0x17, None, CpuAVX512F, Modrm|EVexLIG|Space0F||Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { = RegXMM, Qword|Unspecified|BaseIndex } > +vmovlp, 0x12, None, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVV= VV||Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_l= dSuf, { Qword|Unspecified|BaseIndex, RegXMM, RegXMM } > +vmovlp, 0x13, None, CpuAVX512F, Modrm|EVexLIG|Space0F||Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { = RegXMM, Qword|Unspecified|BaseIndex } > > -vmovq, 0x666E, None, CpuAVX512F|Cpu64, D|Modrm|EVex=3D2|Space0F|VexW=3D2= |Disp8MemShift=3D3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ld= Suf, { Reg64|Unspecified|BaseIndex, RegXMM } > +vmovq, 0x666E, None, CpuAVX512F|Cpu64, D|Modrm|EVex128|Space0F|VexW1|Dis= p8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg64|Un= specified|BaseIndex, RegXMM } > vmovq, 0xF37E, None, CpuAVX512F, Load|Modrm|EVex=3D2|Space0F|VexW1|Disp8= MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unsp= ecified|BaseIndex|RegXMM, RegXMM } > vmovq, 0x66D6, None, CpuAVX512F, Modrm|EVex=3D2|Space0F|VexW1|Disp8MemSh= ift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|U= nspecified|BaseIndex|RegXMM } > > -vmovs, 0x10, None, , D|Modrm|EVexLIG|MaskingMorZ= |||Disp8MemShift|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_= sSuf|No_qSuf|No_ldSuf, { |Unspecified|BaseIndex, RegXMM } > +vmovs, 0x10, None, , D|Modrm|EVexLIG|MaskingMorZ= |||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu= f|No_ldSuf, { |Unspecified|BaseIndex, RegXMM } > vmovs, 0x10, None, , D|Modrm|EVexLIG|Masking=3D3= ||VexVVVV||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_l= dSuf, { RegXMM, RegXMM, RegXMM } > > vmovshdup, 0xF316, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexW=3D1|= Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,= { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } > @@ -2596,7 +2588,7 @@ kadd, 0x4a, None, CpuAVX512 > kand, 0x41, None, CpuAVX512BW, Modrm|Vex256|Space0F|VexVVVV= |VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask= , RegMask } > kandn, 0x42, None, CpuAVX512BW, Modrm|Vex256|Space0F|VexVVV= V|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegMas= k, RegMask, RegMask } > kmov, 0x90, None, CpuAVX512BW, Modrm|Vex128|Space0F|VexW1|N= o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask||Unspec= ified|BaseIndex, RegMask } > -kmov, 0x91, None, CpuAVX512BW, Modrm|Vex128|Space0F|VexW1|I= gnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, |Unspecified|BaseIndex } > +kmov, 0x91, None, CpuAVX512BW, Modrm|Vex128|Space0F|VexW1|N= o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, |Unspe= cified|BaseIndex } > kmov, 0xf292, None, CpuAVX512BW, D|Modrm|Vex128|Space0F||= No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { , RegMask } > knot, 0x44, None, CpuAVX512BW, Modrm|Vex128|Space0F|VexW1|N= o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask } > kor, 0x45, None, CpuAVX512BW, Modrm|Vex256|Space0F|VexVVVV|= VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask,= RegMask } > @@ -2985,13 +2977,13 @@ incsspq, 0xf30fae, 5, CpuSHSTK|Cpu64, Mo > rdsspd, 0xf30f1e, 1, CpuSHSTK, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|= No_sSuf|No_qSuf|No_ldSuf, { Reg32 } > rdsspq, 0xf30f1e, 1, CpuSHSTK|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf, { Reg64 } > saveprevssp, 0xf30f01ea, None, CpuSHSTK, No_bSuf|No_wSuf|No_lSuf|No_sSuf= |No_qSuf|No_ldSuf, {} > -rstorssp, 0xf30f01, 5, CpuSHSTK, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSu= f|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex } > +rstorssp, 0xf30f01, 5, CpuSHSTK, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N= o_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex } > wrssd, 0x0f38f6, None, CpuSHSTK, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSu= f|No_sSuf|No_qSuf|No_ldSuf, { Reg32, Dword|Unspecified|BaseIndex } > -wrssq, 0x0f38f6, None, CpuSHSTK|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|= No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64, Qword|Unspecified|BaseInd= ex } > +wrssq, 0x0f38f6, None, CpuSHSTK|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_= sSuf|No_qSuf|No_ldSuf|Size64, { Reg64, Qword|Unspecified|BaseIndex } > wrussd, 0x660f38f5, None, CpuSHSTK, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_= lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, Dword|Unspecified|BaseIndex } > -wrussq, 0x660f38f5, None, CpuSHSTK|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wS= uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64, Qword|Unspecified|Base= Index } > +wrussq, 0x660f38f5, None, CpuSHSTK|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|= No_sSuf|No_qSuf|No_ldSuf, { Reg64, Qword|Unspecified|BaseIndex } > setssbsy, 0xf30f01e8, None, CpuSHSTK, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf, {} > -clrssbsy, 0xf30fae, 6, CpuSHSTK, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSu= f|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex } > +clrssbsy, 0xf30fae, 6, CpuSHSTK, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N= o_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex } > endbr64, 0xf30f1efa, None, CpuIBT, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS= uf|No_ldSuf, {} > endbr32, 0xf30f1efb, None, CpuIBT, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS= uf|No_ldSuf, {} > > @@ -3230,9 +3222,6 @@ vcvtusi2sh, 0xf37b, None, CpuAVX512_FP16 > vcvtsh2sd, 0xf35a, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3D3|EVexM= ap5|VexVVVV|VexW0|Disp8MemShift=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf= |No_ldSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM } > vcvtsh2ss, 0x13, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3D3|EVexMap= 6|VexVVVV|VexW0|Disp8MemShift=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N= o_ldSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM } > > -vcvtsh2si, 0xf32d, None, CpuAVX512_FP16, Modrm|EVexLIG|EVexMap5|Disp8Mem= Shift=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ToQword|StaticRo= unding|SAE, { RegXMM|Word|Unspecified|BaseIndex, Reg32|Reg64 } > -vcvtsh2usi, 0xf379, None, CpuAVX512_FP16, Modrm|EVexLIG|EVexMap5|Disp8Me= mShift=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ToQword|StaticR= ounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, Reg32|Reg64 } > - > vcvttph2dq, 0xf35b, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Mask= ing=3D3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|= No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM= } > vcvttph2dq, 0xf35b, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Mask= ing=3D3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3D4|No_bSuf|No_wSuf|No_lSuf|= No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } > vcvttph2dq, 0xf35b, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3D3|EVex= Map5|VexW0|Broadcast|Disp8MemShift=3D5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_q= Suf|No_ldSuf|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } > @@ -3256,9 +3245,6 @@ vcvtph2psx, 0x6613, None, CpuAVX512_FP16 > vcvttph2w, 0x667c, None, CpuAVX512_FP16, Modrm|Masking=3D3|EVexMap5|VexW= 0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS= uf|No_ldSuf|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|= RegYMM|RegZMM } > vcvttph2uw, 0x7c, None, CpuAVX512_FP16, Modrm|Masking=3D3|EVexMap5|VexW0= |Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu= f|No_ldSuf|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|R= egYMM|RegZMM } > > -vcvttsh2si, 0xf32c, None, CpuAVX512_FP16, Modrm|EVexLIG|EVexMap5|Disp8Me= mShift=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ToQword|SAE, { = RegXMM|Word|Unspecified|BaseIndex, Reg32|Reg64 } > -vcvttsh2usi, 0xf378, None, CpuAVX512_FP16, Modrm|EVexLIG|EVexMap5|Disp8M= emShift=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ToQword|SAE, {= RegXMM|Word|Unspecified|BaseIndex, Reg32|Reg64 } > - > vfpclassph, 0x66, None, CpuAVX512_FP16|, Modrm||M= asking=3D2|Space0F3A|VexW0|Broadcast|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu= f|No_ldSuf|, { Imm8, |Word, RegMask } > > vmovw, 0x666e, None, CpuAVX512_FP16, D|Modrm|EVex128|VexWIG|EVexMap5|Dis= p8MemShift=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Uns= pecified|BaseIndex, RegXMM } > --=20 H.J.