From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qv1-xf2b.google.com (mail-qv1-xf2b.google.com [IPv6:2607:f8b0:4864:20::f2b]) by sourceware.org (Postfix) with ESMTPS id 9C5FA3858D39 for ; Tue, 18 Oct 2022 21:29:34 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 9C5FA3858D39 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-qv1-xf2b.google.com with SMTP id i12so10190008qvs.2 for ; Tue, 18 Oct 2022 14:29:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=7QneFrbjIwozY3zxdp+KgI8IezrFTMWrzwLqPGpUa64=; b=EzP/sp4i3uHbajr6QInBZuj1OSAJWOBUo7ZcitADUIZhatZBfsKtNErSO2464uOaAO 5Mdp13l7YZp7OhicmfDgRoUxiMWrwkXGOmGcC9c5/lKWrK/xBePic246mD/sSos7PTDN IHDmgD+w4FWgS44w4uVM1RfCA3Ui/uzavJDuTv5EtTAvobBri+2VLScwRwUWjwAP0cJp D94AaeZoEM0aAkpShmsA0XkvjwGV1ftNjXgA6VUdFTrhJ8wdIjtYVqOsVdwKtLAL1v2f DWRkU/JH2Q7UABhbMUT+9V6Iig/CDvFQim7wddqBMKiiQU//RnKLMj2q8pewkSfQPbOZ HL+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=7QneFrbjIwozY3zxdp+KgI8IezrFTMWrzwLqPGpUa64=; b=mzw+fFyysI3v0yRPsjBjwxsNqXHBZ/yBP6QAfbUSxTQq99aZJV4BSQ6dF6BUy3nVPk VyrHw3w5Rz35bhYesIoNvPTiaM9Mgik30Gc1/5aHaz8cQ4mEVU3TzqHp7F+/vCxwn6zo 8KhNKfchA0AfHhpSqn42irb5BJsq3zrVsmnFlfg5bXMJ+8OJrTER3IhstvgJNIBOWNTS I5Nt1mHy/PQH8W7R7LDKStr+qOC0vG5y/FlU164/VchlowYeAcudePdcU9IGsNodPu/N H0Dl0irCthUl1NFyoL7v0yOs8KQ1077ywVeQ+0AjTjbkR+KpvG1kpIlzTZOwI3v/8HRk 2znw== X-Gm-Message-State: ACrzQf3fCfLQDoxvr11/MknVv93NAVowzIJ11Jf507P52kzUClZS1RrI 18f05oxgTAEYsl65cXnQZjfhvAVVQfpsrh/jwYQ= X-Google-Smtp-Source: AMsMyM7RILctS5VJ1w6owL2ZyOw2n9Qtug1svKMEBBcF9l/svgmSSqKa1uq1DA+VDUGTWMFC/lT97LJIA9f8gEasGco= X-Received: by 2002:a05:6214:4101:b0:4af:8cdc:20c4 with SMTP id kc1-20020a056214410100b004af8cdc20c4mr3980889qvb.6.1666128573859; Tue, 18 Oct 2022 14:29:33 -0700 (PDT) MIME-Version: 1.0 References: <20221014091248.4920-1-haochen.jiang@intel.com> <20221014091248.4920-2-haochen.jiang@intel.com> <863655db-f202-477f-c638-00773c25886c@suse.com> <6d3a01b1-2576-f329-0a36-486526c0b03b@suse.com> In-Reply-To: <6d3a01b1-2576-f329-0a36-486526c0b03b@suse.com> From: "H.J. Lu" Date: Tue, 18 Oct 2022 14:28:57 -0700 Message-ID: Subject: Re: [PATCH 01/10] Support Intel AVX-IFMA To: Jan Beulich Cc: Haochen Jiang , wwwhhhyyy , binutils@sourceware.org Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-3017.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Mon, Oct 17, 2022 at 10:33 PM Jan Beulich wrote: > > On 18.10.2022 00:23, H.J. Lu wrote: > > On Sat, Oct 15, 2022 at 11:39 PM Jan Beulich wrote: > >> > >> On 14.10.2022 20:10, H.J. Lu wrote: > >>> On Fri, Oct 14, 2022 at 2:52 AM Jan Beulich wrote: > >>>> > >>>> On 14.10.2022 11:12, Haochen Jiang wrote: > >>>>> From: wwwhhhyyy > >>>>> > >>>>> x86: Support Intel AVX-IFMA > >>>>> > >>>>> Intel AVX IFMA instructions are marked with CpuVEX_PREFIX, which is > >>>>> cleared by default. Without {vex} pseudo prefix, Intel IFMA instructions > >>>>> are encoded with EVEX prefix. {vex} pseudo prefix will turn on VEX > >>>>> encoding for Intel IFMA instructions. > >>>> > >>>> I firmly object to the proliferation of this mis-feature. As expressed > >>>> before for AVX-VNNI, as long as the user has disabled AVX512 (or > >>>> respective sub-features thereof), there should be no need to use {vex} in > >>>> the source code. There's also no reason at all to make the disassembler > >>>> print {vex} prefixes - we don't do so for any other insns (apart from > >>>> AVX-VNNI) where an ambiguity exists between their VEX and EVEX encodings > >>>> (when none of the EVEX-specific features is used). > >>> > >>> The {vex} prefix is used with AVX-IFMA instructions so that IFMA instructions > >>> without a prefix, which are generated by compilers or handwritten, will be > >>> always encoded with EVEX. > >> > >> So again: Why is this necessary when a programmer disabled AVX512? I fully > >> agree we need to pick the EVEX encoding by default if available, but I see > >> no reason whatsoever to insist on a {vex} prefix when the EVEX variant is > >> unavailable anyway. As you said back at the time for AVX-VNNI - this was a > >> design decision taken at Intel. Which is fine for a draft implementation. > >> But decisions for an open source project should be taken in the open, and > >> opinions of others should not simply be put off. > >> > > > > We can discuss how to initialize i.vec_encoding. But it is orthogonal to > > this patch. > > One can view it as orthogonal, yes, but if we change the model then doing > so before more code and testcases need changing is imo preferable. > We can skip the pseudo VEX prefix check when AVX512F is disabled. There should be no testcase changes. -- H.J.