From: "H.J. Lu" <hjl.tools@gmail.com>
To: Jan Beulich <jbeulich@suse.com>
Cc: Binutils <binutils@sourceware.org>
Subject: Re: [PATCH 5/6] x86: simplify .dispNN setting
Date: Thu, 17 Jun 2021 07:47:34 -0700 [thread overview]
Message-ID: <CAMe9rOr5-vJwX8sfQDVJ=YbXBTRcnLv4X-t0F-u_hbKMbxYx1g@mail.gmail.com> (raw)
In-Reply-To: <9ef1346c-5827-acaf-7b1d-1051950e364c@suse.com>
On Mon, Jun 14, 2021 at 3:26 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> First of all eliminate the disp{16,32,32s} static variables, which are
> used solely for setting a temporary variable in build_modrm_byte(). The
> effect there can be had without use of such a temporary and without
> operand_type_or(), by just setting the single bit each that needs
> setting.
>
> Then use operand_type_and_not(..., anydisp) when all dispNN bits want
> clearing together.
>
> gas/
> 2021-06-XX Jan Beulich <jbeulich@suse.com>
>
> * config/tc-i386.c (disp16, disp32, disp32s): Delete.
> (optimize_disp, i386_finalize_displacement): Use
> operand_type_and_not.
> (build_modrm_byte): Likewise. Eliminate local variable newdisp.
>
> --- a/gas/config/tc-i386.c
> +++ b/gas/config/tc-i386.c
> @@ -2089,9 +2089,6 @@ operand_type_xor (i386_operand_type x, i
> return x;
> }
>
> -static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
> -static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
> -static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
> static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
> static const i386_operand_type anydisp = OPERAND_TYPE_ANYDISP;
> static const i386_operand_type anyimm = OPERAND_TYPE_ANYIMM;
> @@ -5884,12 +5881,8 @@ optimize_disp (void)
>
> if (!op_disp && i.types[op].bitfield.baseindex)
> {
> - i.types[op].bitfield.disp8 = 0;
> - i.types[op].bitfield.disp16 = 0;
> - i.types[op].bitfield.disp32 = 0;
> - i.types[op].bitfield.disp32s = 0;
> - i.types[op].bitfield.disp64 = 0;
> - i.op[op].disps = 0;
> + i.types[op] = operand_type_and_not (i.types[op], anydisp);
> + i.op[op].disps = NULL;
> i.disp_operands--;
> continue;
> }
> @@ -5938,11 +5931,7 @@ optimize_disp (void)
> {
> fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
> i.op[op].disps, 0, i.reloc[op]);
> - i.types[op].bitfield.disp8 = 0;
> - i.types[op].bitfield.disp16 = 0;
> - i.types[op].bitfield.disp32 = 0;
> - i.types[op].bitfield.disp32s = 0;
> - i.types[op].bitfield.disp64 = 0;
> + i.types[op] = operand_type_and_not (i.types[op], anydisp);
> }
> else
> /* We only support 64bit displacement on constants. */
> @@ -8261,20 +8250,11 @@ build_modrm_byte (void)
> {
> i.sib.base = NO_BASE_REGISTER;
> i.sib.scale = i.log2_scale_factor;
> - i.types[op].bitfield.disp8 = 0;
> - i.types[op].bitfield.disp16 = 0;
> - i.types[op].bitfield.disp64 = 0;
> + i.types[op] = operand_type_and_not (i.types[op], anydisp);
> if (want_disp32 (&i.tm))
> - {
> - /* Must be 32 bit */
> - i.types[op].bitfield.disp32 = 1;
> - i.types[op].bitfield.disp32s = 0;
> - }
> + i.types[op].bitfield.disp32 = 1;
> else
> - {
> - i.types[op].bitfield.disp32 = 0;
> - i.types[op].bitfield.disp32s = 1;
> - }
> + i.types[op].bitfield.disp32s = 1;
> }
>
> /* Since the mandatory SIB always has index register, so
> @@ -8300,12 +8280,11 @@ build_modrm_byte (void)
> fake_zero_displacement = 1;
> if (i.index_reg == 0)
> {
> - i386_operand_type newdisp;
> -
> /* Both check for VSIB and mandatory non-vector SIB. */
> gas_assert (!i.tm.opcode_modifier.sib
> || i.tm.opcode_modifier.sib == SIBMEM);
> /* Operand is just <disp> */
> + i.types[op] = operand_type_and_not (i.types[op], anydisp);
> if (flag_code == CODE_64BIT)
> {
> /* 64bit mode overwrites the 32bit absolute
> @@ -8315,21 +8294,22 @@ build_modrm_byte (void)
> i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
> i.sib.base = NO_BASE_REGISTER;
> i.sib.index = NO_INDEX_REGISTER;
> - newdisp = (want_disp32(&i.tm) ? disp32 : disp32s);
> + if (want_disp32 (&i.tm))
> + i.types[op].bitfield.disp32 = 1;
> + else
> + i.types[op].bitfield.disp32s = 1;
> }
> else if ((flag_code == CODE_16BIT)
> ^ (i.prefix[ADDR_PREFIX] != 0))
> {
> i.rm.regmem = NO_BASE_REGISTER_16;
> - newdisp = disp16;
> + i.types[op].bitfield.disp16 = 1;
> }
> else
> {
> i.rm.regmem = NO_BASE_REGISTER;
> - newdisp = disp32;
> + i.types[op].bitfield.disp32 = 1;
> }
> - i.types[op] = operand_type_and_not (i.types[op], anydisp);
> - i.types[op] = operand_type_or (i.types[op], newdisp);
> }
> else if (!i.tm.opcode_modifier.sib)
> {
> @@ -8341,20 +8321,11 @@ build_modrm_byte (void)
> i.sib.base = NO_BASE_REGISTER;
> i.sib.scale = i.log2_scale_factor;
> i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
> - i.types[op].bitfield.disp8 = 0;
> - i.types[op].bitfield.disp16 = 0;
> - i.types[op].bitfield.disp64 = 0;
> + i.types[op] = operand_type_and_not (i.types[op], anydisp);
> if (want_disp32 (&i.tm))
> - {
> - /* Must be 32 bit */
> - i.types[op].bitfield.disp32 = 1;
> - i.types[op].bitfield.disp32s = 0;
> - }
> + i.types[op].bitfield.disp32 = 1;
> else
> - {
> - i.types[op].bitfield.disp32 = 0;
> - i.types[op].bitfield.disp32s = 1;
> - }
> + i.types[op].bitfield.disp32s = 1;
> if ((i.index_reg->reg_flags & RegRex) != 0)
> i.rex |= REX_X;
> }
> @@ -11045,12 +11016,7 @@ i386_finalize_displacement (segT exp_seg
> i.types[this_operand].bitfield.disp8 = 1;
>
> /* Check if this is a displacement only operand. */
> - bigdisp = i.types[this_operand];
> - bigdisp.bitfield.disp8 = 0;
> - bigdisp.bitfield.disp16 = 0;
> - bigdisp.bitfield.disp32 = 0;
> - bigdisp.bitfield.disp32s = 0;
> - bigdisp.bitfield.disp64 = 0;
> + bigdisp = operand_type_and_not (i.types[this_operand], anydisp);
> if (operand_type_all_zero (&bigdisp))
> i.types[this_operand] = operand_type_and (i.types[this_operand],
> types);
>
OK.
Thanks.
--
H.J.
next prev parent reply other threads:[~2021-06-17 14:48 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-14 10:23 [PATCH 0/6] x86: further value overflow diagnostic adjustments Jan Beulich
2021-06-14 10:24 ` [PATCH 1/6] x86: off-by-1 in offset_in_range() Jan Beulich
2021-06-17 14:40 ` H.J. Lu
2021-06-18 10:48 ` Jan Beulich
2021-06-14 10:25 ` [PATCH 2/6] x86: make offset_in_range()'s warning contents useful (again) Jan Beulich
2021-06-17 14:40 ` H.J. Lu
2021-06-14 10:25 ` [PATCH 3/6] x86: harmonize disp with imm handling Jan Beulich
2021-06-17 14:46 ` H.J. Lu
2021-06-17 14:57 ` Jan Beulich
2021-06-17 16:00 ` H.J. Lu
2021-06-17 16:05 ` Jan Beulich
2021-06-17 16:12 ` H.J. Lu
2021-06-18 9:03 ` Jan Beulich
2021-06-18 14:12 ` H.J. Lu
2021-06-18 14:52 ` Jan Beulich
2021-06-18 15:41 ` H.J. Lu
2021-06-21 6:36 ` Jan Beulich
2021-06-21 13:26 ` H.J. Lu
2021-06-21 15:05 ` Jan Beulich
2021-06-22 13:22 ` Michael Matz
2021-06-22 14:01 ` H.J. Lu
2021-06-22 14:32 ` Jan Beulich
2021-06-22 14:35 ` Michael Matz
2021-06-14 10:26 ` [PATCH 4/6] x86: slightly simplify offset_in_range() Jan Beulich
2021-06-17 14:46 ` H.J. Lu
2021-06-14 10:26 ` [PATCH 5/6] x86: simplify .dispNN setting Jan Beulich
2021-06-17 14:47 ` H.J. Lu [this message]
2021-06-14 10:26 ` [PATCH 6/6] x86: bring "gas --help" output for --32 etc in sync with reality Jan Beulich
2021-06-17 14:48 ` H.J. Lu
2021-06-14 14:41 ` [PATCH 0/6] x86: further value overflow diagnostic adjustments H.J. Lu
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