From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pj1-x102c.google.com (mail-pj1-x102c.google.com [IPv6:2607:f8b0:4864:20::102c]) by sourceware.org (Postfix) with ESMTPS id 7FFEB3989012 for ; Thu, 17 Jun 2021 14:48:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 7FFEB3989012 Received: by mail-pj1-x102c.google.com with SMTP id 13-20020a17090a08cdb029016eed209ca4so3988682pjn.1 for ; Thu, 17 Jun 2021 07:48:11 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=ZwQXGt8HMuKg+TS+YGCWTbAVcm8u9i/roLLc2IaDtSc=; b=f3lbiKw1M+f3XasHif748dvV1ajRhW6IHeJ+E867SzQ5NR8bl5/1/t2vl/1pQ6a8vl 1UZ2g+76bRS01+Srv0A9bYunPFym64wUGEYf/YMX2bjugfmkiXrbnPwPGM7nb3DxcyN3 IfBbeMTTB6QgLB/bsSMFJzJELMJSrSxhPcF1oGoodQTnwFSqmaH9g/01lg5c8lIujkZ1 I5xWa96lga8+8XIlmY0/Wha3g7eWZAbcs56gwMxJ1TIX9LFM4GGYMNJqU5Jmgg4C3MiU RiVHmUwEy8Z/3EuPrjX4LrXfmQ2IfEN2BXByNt+v7V0ovXoBlG80Tf8ofONenACIRGlM /zog== X-Gm-Message-State: AOAM531ZETmlInoRZBtitGZDGFoO4eP1KVg6+qgNoDP5G2kpVSH4q94n XKGzJHxW2a7NXIpWl7CmzBMrzjrMFCiS/LsG30w= X-Google-Smtp-Source: ABdhPJzo0jfIVsSpcT0I37SGd3Cz8iwdc/6Im5g5q0tOBneFozdiDJMNkxcyN4kgU4d20ZQuvqk+7rWiz38hiiH512k= X-Received: by 2002:a17:902:aa4a:b029:10e:f98c:2b83 with SMTP id c10-20020a170902aa4ab029010ef98c2b83mr267455plr.62.1623941290698; Thu, 17 Jun 2021 07:48:10 -0700 (PDT) MIME-Version: 1.0 References: <0babbec4-06ae-f980-18a9-20608046891b@suse.com> <9ef1346c-5827-acaf-7b1d-1051950e364c@suse.com> In-Reply-To: <9ef1346c-5827-acaf-7b1d-1051950e364c@suse.com> From: "H.J. Lu" Date: Thu, 17 Jun 2021 07:47:34 -0700 Message-ID: Subject: Re: [PATCH 5/6] x86: simplify .dispNN setting To: Jan Beulich Cc: Binutils Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-3025.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Jun 2021 14:48:13 -0000 On Mon, Jun 14, 2021 at 3:26 AM Jan Beulich wrote: > > First of all eliminate the disp{16,32,32s} static variables, which are > used solely for setting a temporary variable in build_modrm_byte(). The > effect there can be had without use of such a temporary and without > operand_type_or(), by just setting the single bit each that needs > setting. > > Then use operand_type_and_not(..., anydisp) when all dispNN bits want > clearing together. > > gas/ > 2021-06-XX Jan Beulich > > * config/tc-i386.c (disp16, disp32, disp32s): Delete. > (optimize_disp, i386_finalize_displacement): Use > operand_type_and_not. > (build_modrm_byte): Likewise. Eliminate local variable newdisp. > > --- a/gas/config/tc-i386.c > +++ b/gas/config/tc-i386.c > @@ -2089,9 +2089,6 @@ operand_type_xor (i386_operand_type x, i > return x; > } > > -static const i386_operand_type disp16 = OPERAND_TYPE_DISP16; > -static const i386_operand_type disp32 = OPERAND_TYPE_DISP32; > -static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S; > static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32; > static const i386_operand_type anydisp = OPERAND_TYPE_ANYDISP; > static const i386_operand_type anyimm = OPERAND_TYPE_ANYIMM; > @@ -5884,12 +5881,8 @@ optimize_disp (void) > > if (!op_disp && i.types[op].bitfield.baseindex) > { > - i.types[op].bitfield.disp8 = 0; > - i.types[op].bitfield.disp16 = 0; > - i.types[op].bitfield.disp32 = 0; > - i.types[op].bitfield.disp32s = 0; > - i.types[op].bitfield.disp64 = 0; > - i.op[op].disps = 0; > + i.types[op] = operand_type_and_not (i.types[op], anydisp); > + i.op[op].disps = NULL; > i.disp_operands--; > continue; > } > @@ -5938,11 +5931,7 @@ optimize_disp (void) > { > fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, > i.op[op].disps, 0, i.reloc[op]); > - i.types[op].bitfield.disp8 = 0; > - i.types[op].bitfield.disp16 = 0; > - i.types[op].bitfield.disp32 = 0; > - i.types[op].bitfield.disp32s = 0; > - i.types[op].bitfield.disp64 = 0; > + i.types[op] = operand_type_and_not (i.types[op], anydisp); > } > else > /* We only support 64bit displacement on constants. */ > @@ -8261,20 +8250,11 @@ build_modrm_byte (void) > { > i.sib.base = NO_BASE_REGISTER; > i.sib.scale = i.log2_scale_factor; > - i.types[op].bitfield.disp8 = 0; > - i.types[op].bitfield.disp16 = 0; > - i.types[op].bitfield.disp64 = 0; > + i.types[op] = operand_type_and_not (i.types[op], anydisp); > if (want_disp32 (&i.tm)) > - { > - /* Must be 32 bit */ > - i.types[op].bitfield.disp32 = 1; > - i.types[op].bitfield.disp32s = 0; > - } > + i.types[op].bitfield.disp32 = 1; > else > - { > - i.types[op].bitfield.disp32 = 0; > - i.types[op].bitfield.disp32s = 1; > - } > + i.types[op].bitfield.disp32s = 1; > } > > /* Since the mandatory SIB always has index register, so > @@ -8300,12 +8280,11 @@ build_modrm_byte (void) > fake_zero_displacement = 1; > if (i.index_reg == 0) > { > - i386_operand_type newdisp; > - > /* Both check for VSIB and mandatory non-vector SIB. */ > gas_assert (!i.tm.opcode_modifier.sib > || i.tm.opcode_modifier.sib == SIBMEM); > /* Operand is just */ > + i.types[op] = operand_type_and_not (i.types[op], anydisp); > if (flag_code == CODE_64BIT) > { > /* 64bit mode overwrites the 32bit absolute > @@ -8315,21 +8294,22 @@ build_modrm_byte (void) > i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; > i.sib.base = NO_BASE_REGISTER; > i.sib.index = NO_INDEX_REGISTER; > - newdisp = (want_disp32(&i.tm) ? disp32 : disp32s); > + if (want_disp32 (&i.tm)) > + i.types[op].bitfield.disp32 = 1; > + else > + i.types[op].bitfield.disp32s = 1; > } > else if ((flag_code == CODE_16BIT) > ^ (i.prefix[ADDR_PREFIX] != 0)) > { > i.rm.regmem = NO_BASE_REGISTER_16; > - newdisp = disp16; > + i.types[op].bitfield.disp16 = 1; > } > else > { > i.rm.regmem = NO_BASE_REGISTER; > - newdisp = disp32; > + i.types[op].bitfield.disp32 = 1; > } > - i.types[op] = operand_type_and_not (i.types[op], anydisp); > - i.types[op] = operand_type_or (i.types[op], newdisp); > } > else if (!i.tm.opcode_modifier.sib) > { > @@ -8341,20 +8321,11 @@ build_modrm_byte (void) > i.sib.base = NO_BASE_REGISTER; > i.sib.scale = i.log2_scale_factor; > i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; > - i.types[op].bitfield.disp8 = 0; > - i.types[op].bitfield.disp16 = 0; > - i.types[op].bitfield.disp64 = 0; > + i.types[op] = operand_type_and_not (i.types[op], anydisp); > if (want_disp32 (&i.tm)) > - { > - /* Must be 32 bit */ > - i.types[op].bitfield.disp32 = 1; > - i.types[op].bitfield.disp32s = 0; > - } > + i.types[op].bitfield.disp32 = 1; > else > - { > - i.types[op].bitfield.disp32 = 0; > - i.types[op].bitfield.disp32s = 1; > - } > + i.types[op].bitfield.disp32s = 1; > if ((i.index_reg->reg_flags & RegRex) != 0) > i.rex |= REX_X; > } > @@ -11045,12 +11016,7 @@ i386_finalize_displacement (segT exp_seg > i.types[this_operand].bitfield.disp8 = 1; > > /* Check if this is a displacement only operand. */ > - bigdisp = i.types[this_operand]; > - bigdisp.bitfield.disp8 = 0; > - bigdisp.bitfield.disp16 = 0; > - bigdisp.bitfield.disp32 = 0; > - bigdisp.bitfield.disp32s = 0; > - bigdisp.bitfield.disp64 = 0; > + bigdisp = operand_type_and_not (i.types[this_operand], anydisp); > if (operand_type_all_zero (&bigdisp)) > i.types[this_operand] = operand_type_and (i.types[this_operand], > types); > OK. Thanks. -- H.J.