From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pg1-x530.google.com (mail-pg1-x530.google.com [IPv6:2607:f8b0:4864:20::530]) by sourceware.org (Postfix) with ESMTPS id EB9583858C2F for ; Fri, 5 Aug 2022 23:01:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org EB9583858C2F Received: by mail-pg1-x530.google.com with SMTP id 73so3801116pgb.9 for ; Fri, 05 Aug 2022 16:01:15 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc; bh=ncZ9+gGXYt+16qk0DpgTTzs/gLe8xk9HPDygzpsVTdk=; b=6tDktf4HI3vzmlke/sh0P3lVm5Gy+9+HPwj/BK+zAomF/QBiYew2MHlAJ2mrw/TdmD UDA1n+9u08pKBjvclawQuNEqTko8wEq1qj7M+/hUKVYVLxo2ej4zUGMLZy9in/AB7m6F gpbFJmyM3fGEr3wceD483f2FH0760tCetNiRjfRsPwUY91Sx0IUIJahADcAkt0swVtm+ j1tTCfRwpd3270DLeKZnl9nIYXPtJe6u1UiK6yRqYuFDMp5uZTpA00Y2/b1fuMuEzLnQ 1Apa8IZYYeHzbX7BsJvBl2WfTn5a7ShuRHu2NpkTE+zIytzjNLs2Ak47Q5W1Qj0/m/dA +mOA== X-Gm-Message-State: ACgBeo2Og0VXaoTfZ3VXUw66ipC2XUy9wImv5Fgt/GGaNGUP8S1W+Oyk MpeuSkkN16sh4r7rvLoUfnvqT9QIpl5zBZhvjQNAslt3 X-Google-Smtp-Source: AA6agR4ZBNvxHdxHHbSHNKTbBBpPL9KnBEldQf9UDvSRglYG45JFEL2wuSZ3VwTHRuHRBwpYNWcj1LzfE6s7ccPN594= X-Received: by 2002:a63:82c2:0:b0:41b:c0f3:39b3 with SMTP id w185-20020a6382c2000000b0041bc0f339b3mr7375707pgd.86.1659740474885; Fri, 05 Aug 2022 16:01:14 -0700 (PDT) MIME-Version: 1.0 References: <03949571-5dbb-f6c1-e2fb-9fbbd8c4b54c@suse.com> In-Reply-To: <03949571-5dbb-f6c1-e2fb-9fbbd8c4b54c@suse.com> From: "H.J. Lu" Date: Fri, 5 Aug 2022 16:00:39 -0700 Message-ID: Subject: Re: [PATCH 05/12] x86-64: adjust MOVQ to/from SReg attributes To: Jan Beulich Cc: Binutils Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-3018.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 05 Aug 2022 23:01:18 -0000 On Fri, Aug 5, 2022 at 5:22 AM Jan Beulich wrote: > > It is unclear to me why the corresponding MOV (no Q suffix) can be > issued without REX.W, but MOVQ has to have that prefix (bit). Add > NoRex64 and in exchange drop Size64. > > --- a/gas/testsuite/gas/i386/x86-64-segment.l > +++ b/gas/testsuite/gas/i386/x86-64-segment.l > @@ -5,8 +5,15 @@ > 5 0002 8C18 mov %ds,\(%rax\) > 6 0004 8E18 movw \(%rax\),%ds > 7 0006 8E18 mov \(%rax\),%ds > - 8 # test segment reg insns with REX > - 9 0008 488CD8 movq %ds,%rax > - 10 000b 488ED8 movq %rax,%ds > - 11 # Force a good alignment. > - 12 000e 0000 .p2align 4,0 > + 8 # test segment reg insns with avoided REX > + 9 0008 8CD8 mov %ds,%rax > + 10 000a 8CD8 movq %ds,%rax > + 11 000c 8ED8 mov %rax,%ds > + 12 000e 8ED8 movq %rax,%ds > + 13 # test segment reg insns with REX > + 14 0010 418CD8 mov %ds,%r8 > + 15 0013 418CD8 movq %ds,%r8 > + 16 0016 418ED8 mov %r8,%ds > + 17 0019 418ED8 movq %r8,%ds > + 18 # Force a good alignment. > + 19 001c 0+ + *\.p2align 4,0 > --- a/gas/testsuite/gas/i386/x86-64-segment.s > +++ b/gas/testsuite/gas/i386/x86-64-segment.s > @@ -5,8 +5,15 @@ > mov %ds,(%rax) > movw (%rax),%ds > mov (%rax),%ds > -# test segment reg insns with REX > +# test segment reg insns with avoided REX > + mov %ds,%rax > movq %ds,%rax > + mov %rax,%ds > movq %rax,%ds > +# test segment reg insns with REX > + mov %ds,%r8 > + movq %ds,%r8 > + mov %r8,%ds > + movq %r8,%ds > # Force a good alignment. > .p2align 4,0 > --- a/opcodes/i386-opc.tbl > +++ b/opcodes/i386-opc.tbl > @@ -148,7 +148,7 @@ movq, 0xb8, None, Cpu64, Size64|No_bSuf| > // implementation defined value is zero). > mov, 0x8c, None, 0, RegMem|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { SReg, Reg16|Reg32|Reg64 } > mov, 0x8c, None, 0, D|Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg, Word|Unspecified|BaseIndex } > -movq, 0x8c, None, Cpu64, D|RegMem|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg, Reg64 } > +movq, 0x8c, None, Cpu64, D|RegMem|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { SReg, Reg64 } > mov, 0x8e, None, 0, Modrm|IgnoreSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg16|Reg32|Reg64, SReg } > // Move to/from control debug registers. In the 16 or 32bit modes > // they are 32bit. In the 64bit mode they are 64bit. > OK. Thanks. -- H.J.