From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl1-x62f.google.com (mail-pl1-x62f.google.com [IPv6:2607:f8b0:4864:20::62f]) by sourceware.org (Postfix) with ESMTPS id C651538582A7 for ; Tue, 2 Aug 2022 15:56:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org C651538582A7 Received: by mail-pl1-x62f.google.com with SMTP id t2so13859688ply.2 for ; Tue, 02 Aug 2022 08:56:28 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=+gTti8DHA2re8Wl9XU6s1J4hyPwf58JyiyI69fYnnWM=; b=Cv8jI3v1AVOnTCHnoicQr0X31InCkGf1l9w+9e6mbTBJRZxSnjn+U6KNvdFDPVNlYi Elov1j8l2M5bQqyseuBWzak6jKuWRjEFGkIUsMRHE8Fnownwx1HW0+YK/1xPEJZKu/+0 i5qiUMvrskx2ywJbCoiIKgkYnHXJE+35thu6XUlWXVf42n983AKMFbS64ObDCaO4qt/5 xN2l+tbDnEdxXVqe5PDbG2YNTN/wCt/nwcepe7ZnaBdCj+KcsV/Fz0K10rmh0D0KWQ0s dgireJML6wOrDffT4i5Nyoex8CYkwBR7dU/esjthycVTaAQx54lRF6KV6NOHKU4ZGaK9 r0cQ== X-Gm-Message-State: ACgBeo1VImHZ+lGC2j5qeg4UChJu40BYcStXLr5hxPpT/kLDEbmGp8+5 3D7tfJqxzdkoyX8PYi3GDhAFLCZZKl8RxHgXDxA= X-Google-Smtp-Source: AA6agR4wfrfwRk/FJzkvJhwsYpWDuys1Ro3vPyD9RX/LgOoG3y3EGxiwQZPTU0OWuBMAfOgTfa3qGdT0uz3+PK2hh3Q= X-Received: by 2002:a17:902:b215:b0:168:da4b:c925 with SMTP id t21-20020a170902b21500b00168da4bc925mr21467063plr.155.1659455787747; Tue, 02 Aug 2022 08:56:27 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: "H.J. Lu" Date: Tue, 2 Aug 2022 08:55:52 -0700 Message-ID: Subject: Re: [PATCH v2] x86: also use D for MOVBE To: Jan Beulich Cc: Binutils Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-3018.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 02 Aug 2022 15:56:30 -0000 On Tue, Aug 2, 2022 at 6:38 AM Jan Beulich wrote: > > First of all rename the meanwhile misleading Opcode_SIMD_FloatD, as it > has also been used for KMOV* and BNDMOV. Then simplify the condition > selecting which form if "reversing" to use - except for the MOV to/from > control/debug/test registers all extended opcode space insns use bit 0 > (rather than bit 1) to indicate the direction (from/to memory) of an > operation. With that, D can simply be set on the first of the two > templates, while the other can be dropped. > --- > v2: Add comment. > > --- a/gas/config/tc-i386.c > +++ b/gas/config/tc-i386.c > @@ -3572,7 +3572,7 @@ build_vex_prefix (const insn_template *t > > if (i.tm.opcode_modifier.d) > i.tm.base_opcode ^= (i.tm.base_opcode & 0xee) != 0x6e > - ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD; > + ? Opcode_ExtD : Opcode_SIMD_IntD; > else /* Use the next insn. */ > install_template (&t[1]); > } > @@ -6757,13 +6757,13 @@ match_template (char mnem_suffix) > found_reverse_match = Opcode_VexW; > goto check_operands_345; > } > - else if (operand_types[0].bitfield.xmmword > - || operand_types[i.operands - 1].bitfield.xmmword > - || operand_types[0].bitfield.class == RegMMX > - || operand_types[i.operands - 1].bitfield.class == RegMMX > - || is_any_vex_encoding(t)) > + else if (t->opcode_modifier.opcodespace != SPACE_BASE > + && (t->opcode_modifier.opcodespace != SPACE_0F > + /* MOV to/from CR/DR/TR, as an exception, follow > + the base opcode space encoding model. */ > + || (t->base_opcode | 7) != 0x27)) > found_reverse_match = (t->base_opcode & 0xee) != 0x6e > - ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD; > + ? Opcode_ExtD : Opcode_SIMD_IntD; > else > found_reverse_match = Opcode_D; > if (t->opcode_modifier.floatr) > --- a/opcodes/i386-opc.h > +++ b/opcodes/i386-opc.h > @@ -928,7 +928,7 @@ typedef struct insn_template > unset if Regmem --> Reg. */ > #define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */ > #define Opcode_FloatD 0x400 /* Direction bit for float insns. */ > -#define Opcode_SIMD_FloatD 0x1 /* Direction bit for SIMD fp insns. */ > +#define Opcode_ExtD 0x1 /* Direction bit for extended opcode space insns. */ > #define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */ > /* The next value is arbitrary, as long as it's non-zero and distinct > from all other values above. */ > --- a/opcodes/i386-opc.tbl > +++ b/opcodes/i386-opc.tbl > @@ -161,8 +161,7 @@ movq, 0xf21, None, Cpu64, D|RegMem|Size6 > mov, 0xf24, None, Cpu386|CpuNo64, D|RegMem|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Test, Reg32 } > > // Move after swapping the bytes > -movbe, 0x0f38f0, None, CpuMovbe, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } > -movbe, 0x0f38f1, None, CpuMovbe, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64, Word|Dword|Qword|Unspecified|BaseIndex } > +movbe, 0x0f38f0, None, CpuMovbe, D|Modrm|No_bSuf|No_sSuf|No_ldSuf, { Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } > > // Move with sign extend. > // "movsbl" & "movsbw" must not be unified into "movsb" to avoid OK. Thanks. -- H.J.