From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oa1-x34.google.com (mail-oa1-x34.google.com [IPv6:2001:4860:4864:20::34]) by sourceware.org (Postfix) with ESMTPS id 06DE93858401 for ; Mon, 28 Nov 2022 23:22:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 06DE93858401 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-oa1-x34.google.com with SMTP id 586e51a60fabf-141ca09c2fbso15014647fac.6 for ; Mon, 28 Nov 2022 15:22:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=Psv4fKGRc9NeVyU2RDiWef9Oku9eGULNyQh8/PSZxm0=; b=B3JAMPzbTSEqSMeEz8msqmxOXjEeL1TMzJCW7jmrOo9tIHj5FcEjICaqPpPiXSGckb wW8zHthlheENCbxjRbCmsDs05dR1DynyYbW6tn7bMoU53cDGUfg/xdUtBRdwqcXRLm6h SPHndxDC1CQno8RYihPDRv6N+bOn5Dm9gwK+LhoqbT3dgiBprHwrqZVKycVD7bJcFobt t+xqeMVXSYdbjWBfRZxLyG/B+YvnxHuKKkJieMhJeUjk3bcIecOTxk6PZldSkj9DO/W5 aQif1f6NoNxGEokqkjfKMWhAYfG/R7XiDdz03C86Rjc8hbKxZGGpUMxj8uwNKL1g3zRr SYlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=Psv4fKGRc9NeVyU2RDiWef9Oku9eGULNyQh8/PSZxm0=; b=q4mzbBHi5ApLoWP7wXXk4sJMVJQAaQFpeLErkVTO98YICZ+yCR49ciBJ9/G2k0ltDl THKYzOhLZ5d1lHPuF2I94Y2lX94tzbEenikRFXShpx+n1ZRalcHR3HJNaCbCdUIRJGKz 0CdPJL/hCsYBsI+0WWXKE4GCwQKXYyVkbF1fzULFj+MgrbpOnzRjskZMX6h0+j4g4ci5 qUyry7vDNX8J3QWjSBinUUMrNZei631wZ6yGo9Sq07g2HnGszXnh6sk1LYqybyNKKOjW jDpNquPVGLig2lNHUh6tFaloWXcUnrxyNxYFUNwe9ff31YwQKNH2MUlDuSadHvERWFZn aQjQ== X-Gm-Message-State: ANoB5pkTrYaPHJk0RRND+czT6U1uL+u462n/S50kEzS2WNkplXfHHOwY pQM+398m+UxDjE7QQsl+SpFPxuHk2TWX/jwL7VXMGT7U X-Google-Smtp-Source: AA0mqf7vPg8ASv/WAgYKuruGSswcnKv/4axHBi9NUZOMmt9b8Bo+agc8a2WW2Wf0knf31EYmZdJYa8tbbScp+aWz43I= X-Received: by 2002:a05:6871:4501:b0:13c:5da4:7229 with SMTP id nj1-20020a056871450100b0013c5da47229mr23962119oab.266.1669677751034; Mon, 28 Nov 2022 15:22:31 -0800 (PST) MIME-Version: 1.0 References: <5dd8b2df-62f2-a551-4b35-f3df66d57e04@suse.com> In-Reply-To: <5dd8b2df-62f2-a551-4b35-f3df66d57e04@suse.com> From: "H.J. Lu" Date: Mon, 28 Nov 2022 15:21:55 -0800 Message-ID: Subject: Re: [PATCH 3/3] x86: clean up after removal of support for gcc <= 2.8.1 To: Jan Beulich Cc: Binutils Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-3016.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,KAM_NUMSUBJECT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Thu, Nov 24, 2022 at 12:58 AM Jan Beulich wrote: > > At the very least a comment in process_operands() is stale. Beyond that > there are effectively two options: > 1) It is possible that FADDP and FMULP were mistakenly not marked as > being in need of dealing with the compiler anomaly, and hence the > respective templates weren't removed at the time when they should > have been. > 2) It is also possible that there are indeed uses known beyond compiler > generated output for these two commutative opcodes, and hence the > templates need to stay. > To be on the safe side assume 2: Update the comment and fold the > templates into their "normal" ones (utilizing D), adjusting consuming > code accordingly. > > For FMULP also add a comment paralleling a similar one FADDP has. Please mention dropping GCC 2.8.1 support in gas/NEWS. > --- a/gas/config/tc-i386.c > +++ b/gas/config/tc-i386.c > @@ -6806,7 +6806,8 @@ match_template (char mnem_suffix) > found_reverse_match = 0; > else if (operand_types[0].bitfield.tbyte) > { > - found_reverse_match = Opcode_FloatD; > + if (t->opcode_modifier.operandconstraint != UGH) > + found_reverse_match = Opcode_FloatD; > /* FSUB{,R} and FDIV{,R} may need a 2nd bit flipped. */ > if ((t->base_opcode & 0x20) > && (intel_syntax || intel_mnemonic)) > @@ -7997,29 +7998,31 @@ process_operands (void) > { > /* The register or float register operand is in operand > 0 or 1. */ > - unsigned int op = i.tm.operand_types[0].bitfield.class != Reg; > + const reg_entry *r = i.op[0].regs; > > + if (i.imm_operands > + || (r->reg_type.bitfield.instance == Accum && i.op[1].regs)) > + r = i.op[1].regs; > /* Register goes in low 3 bits of opcode. */ > - i.tm.base_opcode |= i.op[op].regs->reg_num; > - if ((i.op[op].regs->reg_flags & RegRex) != 0) > + i.tm.base_opcode |= r->reg_num; > + if ((r->reg_flags & RegRex) != 0) > i.rex |= REX_B; > if (!quiet_warnings && i.tm.opcode_modifier.operandconstraint == UGH) > { > - /* Warn about some common errors, but press on regardless. > - The first case can be generated by gcc (<= 2.8.1). */ > - if (i.operands == 2) > - { > - /* Reversed arguments on faddp, fsubp, etc. */ > - as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name, > - register_prefix, i.op[!intel_syntax].regs->reg_name, > - register_prefix, i.op[intel_syntax].regs->reg_name); > - } > - else > + /* Warn about some common errors, but press on regardless. */ > + if (i.operands != 2) > { > /* Extraneous `l' suffix on fp insn. */ > as_warn (_("translating to `%s %s%s'"), i.tm.name, > register_prefix, i.op[0].regs->reg_name); > } > + else if (i.op[0].regs->reg_type.bitfield.instance != Accum) > + { > + /* Reversed arguments on faddp or fmulp. */ > + as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name, > + register_prefix, i.op[!intel_syntax].regs->reg_name, > + register_prefix, i.op[intel_syntax].regs->reg_name); > + } > } > } > > --- a/opcodes/i386-opc.tbl > +++ b/opcodes/i386-opc.tbl > @@ -686,11 +686,10 @@ fadd, 0xdec1, None, CpuFP, NoSuf|Ugh|ATT > fadd, 0xd8, 0, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex } > fiadd, 0xde, 0, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex } > > -faddp, 0xdec0, None, CpuFP, NoSuf, { FloatAcc, FloatReg } > +faddp, 0xdec0, None, CpuFP, D|NoSuf|Ugh, { FloatAcc, FloatReg } > faddp, 0xdec0, None, CpuFP, NoSuf, { FloatReg } > // alias for faddp %st, %st(1) > faddp, 0xdec1, None, CpuFP, NoSuf, {} > -faddp, 0xdec0, None, CpuFP, NoSuf|Ugh, { FloatReg, FloatAcc } > > // subtract > fsub, 0xd8e0, None, CpuFP, NoSuf, { FloatReg } > @@ -732,10 +731,10 @@ fmul, 0xdec9, None, CpuFP, NoSuf|Ugh|ATT > fmul, 0xd8, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex } > fimul, 0xde, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex } > > -fmulp, 0xdec8, None, CpuFP, NoSuf, { FloatAcc, FloatReg } > +fmulp, 0xdec8, None, CpuFP, D|NoSuf|Ugh, { FloatAcc, FloatReg } > fmulp, 0xdec8, None, CpuFP, NoSuf, { FloatReg } > +// alias for fmulp %st, %st(1) > fmulp, 0xdec9, None, CpuFP, NoSuf, {} > -fmulp, 0xdec8, None, CpuFP, NoSuf|Ugh, { FloatReg, FloatAcc } > > // divide > fdiv, 0xd8f0, None, CpuFP, NoSuf, { FloatReg } > -- H.J.