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Lu" Date: Wed, 30 Aug 2023 11:00:22 -0700 Message-ID: Subject: Re: [PATCH 5/5] x86: support AVX10.1 vector size restrictions To: Jan Beulich Cc: Binutils , "Jiang, Haochen" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-3016.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Wed, Aug 30, 2023 at 9:16=E2=80=AFAM Jan Beulich wro= te: > > On 30.08.2023 17:25, H.J. Lu wrote: > > On Wed, Aug 30, 2023 at 12:57=E2=80=AFAM Jan Beulich wrote: > >> > >> On 29.08.2023 18:26, H.J. Lu wrote: > >>> On Fri, Aug 25, 2023 at 5:48=E2=80=AFAM Jan Beulich wrote: > >>>> @@ -1673,6 +1680,12 @@ an unconditional jump to the target. > >>>> > >>>> Note that the sub-architecture specifiers (starting with a dot) can= be prefixed > >>>> with @code{no} to revoke the respective (and any dependent) functio= nality. > >>>> +Note further that @samp{.avx10.} can be suffixed with a vector l= ength > >>>> +restriction (@samp{/256} or @samp{/128}, with @samp{/512} simply re= storing the > >>>> +default). Despite these otherwise being "enabling" specifiers, usi= ng these > >>>> +suffixes will disable all insns with wider vector or mask register = operands. > >>>> +On SVR4-derived platforms, the separator character @samp{/} can be = replaced by > >>>> +@samp{:}. > >>>> > >>>> Following the CPU architecture (but not a sub-architecture, which a= re those > >>>> starting with a dot), you may specify @samp{jumps} or @samp{nojumps= } to > >>> > >>> Although CPUID bits in AVX10 spec may leave an impression that 128-bi= t, > >>> 256-bit and 512-bit vectors may be enabled independently. But it als= o says > >>> > >>> A =E2=80=9Cconverged=E2=80=9D version of Intel AVX10 with maximum vec= tor lengths of 256 > >>> bits and 32-bit opmask registers will be supported across all Intel p= rocessors, > >>> while 512-bit vector registers and 64-bit opmasks will continue to be= supported > >>> on some P-core processors. > >>> > >>> Adding avx10.1/128 isn't necessary. > >> > >> I agree it isn't necessary, but as expressed before I view it as desir= able. > >> Apart from the sentence you quoted the spec later also says "There are > >> currently no plans to support an Intel AVX10/128 implementation." For = my > >> choice of also supporting the 128-bit restriction I'd like to put emph= asis > >> on "currently". I think I said before that emulation environments (qem= u, > >> sde to name just two well-known examples) are free to implement such > >> further restricted ISAs without then becoming out-of-spec. > >> > >> Plus supporting this mode right away has made me make certain adjustme= nts > >> in what I'd call more clean a way, which I view as desirable as well. > > > > Since AVX10 spec doesn't specify if mask registers should be limited to > > 16 bits for AVX10/128, doing it in assembler is premature. > > It's hard to see why they would remain wider. The more that they were 16 > bits only in AVX512F. > > Plus of course nobody needs to use the options to enforce the 128-bit > limit. The way I've coded it, it matches what the specification says. > AVX10 spec only has Quadword opmask instructions will only be supported on processors supporting vector lengths of 512 bits. It doesn't say anything about 32-bit mask. 32-bit mask can be useful even with 16 byte vector. --=20 H.J.