From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ej1-x62b.google.com (mail-ej1-x62b.google.com [IPv6:2a00:1450:4864:20::62b]) by sourceware.org (Postfix) with ESMTPS id 9B8923858D28 for ; Mon, 7 Nov 2022 20:03:51 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 9B8923858D28 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ej1-x62b.google.com with SMTP id kt23so33094693ejc.7 for ; Mon, 07 Nov 2022 12:03:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=kwptsX9KmZ5I1UcSbzwd3Cmnovik2yRtIHI3AGU5Mn0=; b=jlG8fnopcLMFEWJcml5Pj91Qzb59AhmOgslkVQEbzvcrxkUILPf28VKlJHAwYHzZ7j UIc/vhZOPQacCLnut1aMdrM5+sPo50cGcWBarIPUqRA/OWS61nJHjBGd0TNXscz/eoHx u2/1HX3hv8RzJ7WrVa9v/85us3CywwWgN5p8bF8mQ1JHfECZh9cy8KrcbNO7AnfYKDrD 41SSWUssZnEmPw9+2MPfgwyo79BqJa8Iq7AqLFRskYeV2ob6PQ4viulXoGEnI75JHWi9 e6YdXxRW6plklFuyevmCdQ/8UuFF4paCFUv8oecM4XvQXDOyfq/+uKRLY3nEk2JhNLXr Ov6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kwptsX9KmZ5I1UcSbzwd3Cmnovik2yRtIHI3AGU5Mn0=; b=zq2af9gzAH6GIcOsfRWGmc3OVnF6Gk2Go19Bm/GRveK/4w/xVsbOvNn1rjVR9OY1n+ SIXwTP5tX5vrykD5QE2YxJgHgExMKTmOIaaHHHzSoN0wa0otfRLeboMhkdiyTELfnHdt p8Fq4m4peWsMf9MuEqRHgaDmfFPEGO11gRh/VoRBqYRbukO3UtLASynHS7WbRHzWDbBc WBMHZ0ci4polMLIbQJsgNjvVw1gq0y+R9ZwGhnZZ3tYbWXh4f2U9lwH0WeG6DYrc/1MG Z0NjCDxSUf2kRzh1qtYj47h3xWrir+6/3o3CYQ3gyqPP0rqSHMjDAyiFG2NOOTCGF+Ho UntA== X-Gm-Message-State: ANoB5pmw9G4GNlwEg895UKmMoIHa/DuqSkg+n2IOEIjvhB4XlfI0EIMT q8tnPP/6/TTht+GL7LVDrGx8Py8YdHa0sg7hpqB/R8Fw X-Google-Smtp-Source: AA0mqf7aaWr+hDRX+fRa5RgJDH9zuttqg1rTkaeqmAaJUEzTiEbh6SdmjFzet21PV2b3luzW51JxH2oYDK2nuEg/Nmw= X-Received: by 2002:a17:906:7c12:b0:7ae:59c0:4224 with SMTP id t18-20020a1709067c1200b007ae59c04224mr393500ejo.647.1667851430204; Mon, 07 Nov 2022 12:03:50 -0800 (PST) MIME-Version: 1.0 References: <20221014091248.4920-1-haochen.jiang@intel.com> <20221014091248.4920-7-haochen.jiang@intel.com> <1e6a7d9c-4b14-821e-cc46-453adbe6f183@suse.com> In-Reply-To: From: "H.J. Lu" Date: Mon, 7 Nov 2022 12:03:11 -0800 Message-ID: Subject: Re: [PATCH 06/10] Support Intel RAO-INT To: "Kong, Lingling" Cc: "Beulich, Jan" , "Jiang, Haochen" , "binutils@sourceware.org" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-3023.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Mon, Nov 7, 2022 at 5:37 AM Kong, Lingling wro= te: > > > On 06.11.2022 13:50, Kong, Lingling wrote: > > >>>>> +aadd, 0xf38fc, None, CpuRAOINT, > > >>>>> > > +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, > > >>>>> +Dword|Qword|Unspecified|BaseIndex} > > >>>>> +aand, 0x660f38fc, None, CpuRAOINT, > > >>>>> > > +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, > > >>>>> +Dword|Qword|Unspecified|BaseIndex} > > >>>>> +aor, 0xf20f38fc, None, CpuRAOINT, > > >>>>> > > +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, > > >>>>> +Dword|Qword|Unspecified|BaseIndex} > > >>>>> +axor, 0xf30f38fc, None, CpuRAOINT, > > >>>>> > > +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, > > >>>>> +Dword|Qword|Unspecified|BaseIndex} > > >>>> > > >>>> Why IgnoreSize? Instead I think you need CheckRegSize (assuming it > > >>>> does enough for Intel syntax memory operands - please double check= ; > > >>>> if not this will need fixing). > > >>>> > > > Yes, now it changed to CheckRegSize. > > > > For one I'm pretty sure I said I was wrong about IgnoreSize. And as to > > CheckRegSize - did you actually double check as indicated? While I thin= k the > > attribute should be there, I've also observed recently that it missing = on e.g. > > MOVBE does not currently make any difference (there are the same bogus > > diagnostics with and without it). So while I don't mind it being put th= ere, H.J. > > may view this differently as long as the attribute doesn't really have = any effect. > > Thanks for reminding, IgnoreSize was deleted by mistake. Although I test= ed some difference Intel syntax memory operands, there is no difference in= the result with or without CheckRegSize. For CheckRegSize, as far as the s= emantics of rao-int's operand is concerned, it needs to be checked. > > > > --- a/opcodes/i386-opc.h > > > +++ b/opcodes/i386-opc.h > > > @@ -223,6 +223,8 @@ enum > > > CpuMSRLIST, > > > /* Intel AVX NE CONVERT Instructions support required. */ > > > CpuAVX_NE_CONVERT, > > > + /* Intel RAO INT Instructions support required. */ CpuRAO_INT, > > > /* mwaitx instruction required */ > > > CpuMWAITX, > > > /* Clzero instruction required */ > > > > This and ... > > > > > --- a/opcodes/i386-opc.tbl > > > +++ b/opcodes/i386-opc.tbl > > > @@ -3321,3 +3321,12 @@ rdmsrlist, 0xf20f01c6, None, CpuMSRLIST|Cpu64, > > > No_bSuf|No_wSuf|No_lSuf|No_sSuf|N wrmsrlist, 0xf30f01c6, None, > > > CpuMSRLIST|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, > > {} > > > > > > // MSRLIST instructions end. > > > + > > > +// RAO-INT instructions. > > > + > > > +aadd, 0xf38fc, None, CpuRAO_INT, > > > > > +Modrm|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS > > uf,{ > > > +Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } aand, 0x660f38fc, > > > +None, CpuRAO_INT, > > > > > +Modrm|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS > > uf,{ > > > +Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } aor, 0xf20f38fc, > > > +Reg32|None, > > > +CpuRAO_INT, > > > > > +Modrm|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS > > uf,{ > > > +Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } axor, 0xf30f38fc, > > > +None, CpuRAO_INT, > > > > > +Modrm|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS > > uf,{ > > > +Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } > > > + > > > +// RAO-INT instructions end. > > > > ... this doesn't look like valid changes - line breaks are at the wrong= spots. > > > > Jan > > Sorry, It is mistake about my git send-email, updated again. > > Subject: [PATCH] Support Intel RAO-INT > > gas/ChangeLog: > > * NEWS: Support Intel RAO-INT. > * config/tc-i386.c: Add raoint. > * doc/c-i386.texi: Document .raoint. > * testsuite/gas/i386/i386.exp: Run RAO_INT tests. > * testsuite/gas/i386/raoint-intel.d: New test. > * testsuite/gas/i386/raoint.d: Ditto. > * testsuite/gas/i386/raoint.s: Ditto. > * testsuite/gas/i386/x86-64-raoint-intel.d: Ditto. > * testsuite/gas/i386/x86-64-raoint.d: Ditto. > * testsuite/gas/i386/x86-64-raoint.s: Ditto. > > opcodes/ChangeLog: > > * i386-dis.c (PREFIX_0F38FC): New. > (prefix_table): Add PREFIX_0F38FC. > * i386-gen.c: (cpu_flag_init): Add CPU_RAO_INT_FLAGS and > CPU_ANY_RAO_INT_FLAGS. > * i386-init.h: Regenerated. > * i386-opc.h: (CpuRAO_INT): New. > (i386_cpu_flags): Add cpuraoint. > * i386-opc.tbl: Add RAO_INT instructions. > * i386-tbl.h: Regenerated. > --- > gas/NEWS | 2 + > gas/config/tc-i386.c | 1 + > gas/doc/c-i386.texi | 3 +- > gas/testsuite/gas/i386/i386.exp | 4 + > gas/testsuite/gas/i386/raoint-intel.d | 18 + > gas/testsuite/gas/i386/raoint.d | 18 + > gas/testsuite/gas/i386/raoint.s | 15 + > gas/testsuite/gas/i386/x86-64-raoint-intel.d | 18 + > gas/testsuite/gas/i386/x86-64-raoint.d | 18 + > gas/testsuite/gas/i386/x86-64-raoint.s | 15 + > opcodes/i386-dis.c | 11 +- > opcodes/i386-gen.c | 5 + > opcodes/i386-init.h | 518 +- > opcodes/i386-opc.h | 3 + > opcodes/i386-opc.tbl | 9 + > opcodes/i386-tbl.h | 7906 +++++++++--------- > 16 files changed, 4389 insertions(+), 4175 deletions(-) > create mode 100644 gas/testsuite/gas/i386/raoint-intel.d > create mode 100644 gas/testsuite/gas/i386/raoint.d > create mode 100644 gas/testsuite/gas/i386/raoint.s > create mode 100644 gas/testsuite/gas/i386/x86-64-raoint-intel.d > create mode 100644 gas/testsuite/gas/i386/x86-64-raoint.d > create mode 100644 gas/testsuite/gas/i386/x86-64-raoint.s > > diff --git a/gas/NEWS b/gas/NEWS > index f35e8a93a0..86731348e3 100644 > --- a/gas/NEWS > +++ b/gas/NEWS > @@ -1,5 +1,7 @@ > -*- text -*- > > +* Add support for Intel RAO-INT instructions. > + > * Add support for Intel AVX-NE-CONVERT instructions. > > * Add support for Intel MSRLIST instructions. > diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c > index a846b9e865..6dcf11470c 100644 > --- a/gas/config/tc-i386.c > +++ b/gas/config/tc-i386.c > @@ -1102,6 +1102,7 @@ static const arch_entry cpu_arch[] =3D > SUBARCH (wrmsrns, WRMSRNS, ANY_WRMSRNS, false), > SUBARCH (msrlist, MSRLIST, ANY_MSRLIST, false), > SUBARCH (avx_ne_convert, AVX_NE_CONVERT, ANY_AVX_NE_CONVERT, false), > + SUBARCH (rao_int, RAO_INT, ANY_RAO_INT, false), > }; > > #undef SUBARCH > diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi > index 0ef1cece48..6fa1199f32 100644 > --- a/gas/doc/c-i386.texi > +++ b/gas/doc/c-i386.texi > @@ -201,6 +201,7 @@ accept various extension mnemonics. For example, > @code{wrmsrns}, > @code{msrlist}, > @code{avx_ne_convert}, > +@code{rao_int}, > @code{amx_int8}, > @code{amx_bf16}, > @code{amx_fp16}, > @@ -1496,7 +1497,7 @@ supported on the CPU specified. The choices for @v= ar{cpu_type} are: > @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.i= bt} > @item @samp{.prefetchi} @tab @samp{.avx_ifma} @tab @samp{.avx_vnni_int8} > @item @samp{.cmpccxadd} @tab @samp{.wrmsrns} @tab @samp{.msrlist} > -@item @samp{.avx_ne_convert} > +@item @samp{.avx_ne_convert} @tab @samp{.rao_int} > @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @s= amp{.cldemote} > @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpcl= mulqdq} > @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @s= amp{.tsxldtrk} > diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i38= 6.exp > index 9ddf2b451e..5b20ac7ce5 100644 > --- a/gas/testsuite/gas/i386/i386.exp > +++ b/gas/testsuite/gas/i386/i386.exp > @@ -485,6 +485,8 @@ if [gas_32_check] then { > run_list_test "msrlist-inval" > run_dump_test "avx-ne-convert" > run_dump_test "avx-ne-convert-intel" > + run_dump_test "raoint" > + run_dump_test "raoint-intel" > run_list_test "sg" > run_dump_test "clzero" > run_dump_test "invlpgb" > @@ -1166,6 +1168,8 @@ if [gas_64_check] then { > run_dump_test "x86-64-msrlist-intel" > run_dump_test "x86-64-avx-ne-convert" > run_dump_test "x86-64-avx-ne-convert-intel" > + run_dump_test "x86-64-raoint" > + run_dump_test "x86-64-raoint-intel" > run_dump_test "x86-64-clzero" > run_dump_test "x86-64-mwaitx-bdver4" > run_list_test "x86-64-mwaitx-reg" > diff --git a/gas/testsuite/gas/i386/raoint-intel.d b/gas/testsuite/gas/i3= 86/raoint-intel.d > new file mode 100644 > index 0000000000..2c22b9c8d0 > --- /dev/null > +++ b/gas/testsuite/gas/i386/raoint-intel.d > @@ -0,0 +1,18 @@ > +#as: > +#objdump: -dw -Mintel > +#name: i386 RAO_INT insns (Intel disassembly) > +#source: raoint.s > + > +.*: +file format .* > + > +Disassembly of section \.text: > + > +0+ <_start>: > +\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd DWORD PTR \[eax\],edx > +\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand DWORD PTR \[eax\],edx > +\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor DWORD PTR \[eax\],edx > +\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor DWORD PTR \[eax\],edx > +\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd DWORD PTR \[eax\],edx > +\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand DWORD PTR \[eax\],edx > +\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor DWORD PTR \[eax\],edx > +\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor DWORD PTR \[eax\],edx > diff --git a/gas/testsuite/gas/i386/raoint.d b/gas/testsuite/gas/i386/rao= int.d > new file mode 100644 > index 0000000000..4a6a4e9b21 > --- /dev/null > +++ b/gas/testsuite/gas/i386/raoint.d > @@ -0,0 +1,18 @@ > +#as: > +#objdump: -dw > +#name: i386 RAO_INT insns > +#source: raoint.s > + > +.*: +file format .* > + > +Disassembly of section \.text: > + > +0+ <_start>: > +\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd %edx,\(%eax\) > +\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand %edx,\(%eax\) > +\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor %edx,\(%eax\) > +\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor %edx,\(%eax\) > +\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd %edx,\(%eax\) > +\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand %edx,\(%eax\) > +\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor %edx,\(%eax\) > +\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor %edx,\(%eax\) > diff --git a/gas/testsuite/gas/i386/raoint.s b/gas/testsuite/gas/i386/rao= int.s > new file mode 100644 > index 0000000000..04a13ddeb9 > --- /dev/null > +++ b/gas/testsuite/gas/i386/raoint.s > @@ -0,0 +1,15 @@ > +# Check 32bit RAO-INT instructions > + > + .allow_index_reg > + .text > +_start: > + aadd %edx, (%eax) #RAO-INT > + aand %edx, (%eax) #RAO-INT > + aor %edx, (%eax) #RAO-INT > + axor %edx, (%eax) #RAO-INT > + > +.intel_syntax noprefix > + aadd DWORD PTR [eax], %edx #RAO-INT > + aand DWORD PTR [eax], %edx #RAO-INT > + aor DWORD PTR [eax], %edx #RAO-INT > + axor DWORD PTR [eax], %edx #RAO-INT > diff --git a/gas/testsuite/gas/i386/x86-64-raoint-intel.d b/gas/testsuite= /gas/i386/x86-64-raoint-intel.d > new file mode 100644 > index 0000000000..5b5c9051ac > --- /dev/null > +++ b/gas/testsuite/gas/i386/x86-64-raoint-intel.d > @@ -0,0 +1,18 @@ > +#as: > +#objdump: -dw -Mintel > +#name: x86_64 RAO_INT insns (Intel disassembly) > +#source: x86-64-raoint.s > + > +.*: +file format .* > + > +Disassembly of section \.text: > + > +0+ <_start>: > +\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd QWORD PTR \[rax\],rdx > +\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand QWORD PTR \[rax\],rdx > +\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor QWORD PTR \[rax\],rdx > +\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor QWORD PTR \[rax\],rdx > +\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd QWORD PTR \[rax\],rdx > +\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand QWORD PTR \[rax\],rdx > +\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor QWORD PTR \[rax\],rdx > +\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor QWORD PTR \[rax\],rdx > diff --git a/gas/testsuite/gas/i386/x86-64-raoint.d b/gas/testsuite/gas/i= 386/x86-64-raoint.d > new file mode 100644 > index 0000000000..ccdf027737 > --- /dev/null > +++ b/gas/testsuite/gas/i386/x86-64-raoint.d > @@ -0,0 +1,18 @@ > +#as: > +#objdump: -dw > +#name: x86_64 RAO_INT insns > +#source: x86-64-raoint.s > + > +.*: +file format .* > + > +Disassembly of section \.text: > + > +0+ <_start>: > +\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd %rdx,\(%rax\) > +\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand %rdx,\(%rax\) > +\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor %rdx,\(%rax\) > +\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor %rdx,\(%rax\) > +\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd %rdx,\(%rax\) > +\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand %rdx,\(%rax\) > +\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor %rdx,\(%rax\) > +\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor %rdx,\(%rax\) > diff --git a/gas/testsuite/gas/i386/x86-64-raoint.s b/gas/testsuite/gas/i= 386/x86-64-raoint.s > new file mode 100644 > index 0000000000..645bcfc3c4 > --- /dev/null > +++ b/gas/testsuite/gas/i386/x86-64-raoint.s > @@ -0,0 +1,15 @@ > +# Check 64bit RAO_INT instructions > + > + .allow_index_reg > + .text > +_start: > + aadd %rdx, (%rax) #RAO-INT > + aand %rdx, (%rax) #RAO-INT > + aor %rdx, (%rax) #RAO-INT > + axor %rdx, (%rax) #RAO-INT > + > +.intel_syntax noprefix > + aadd QWORD PTR [rax], %rdx #RAO-INT > + aand QWORD PTR [rax], %rdx #RAO-INT > + aor QWORD PTR [rax], %rdx #RAO-INT > + axor QWORD PTR [rax], %rdx #RAO-INT > diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c > index f0638a3193..ee7fc09932 100644 > --- a/opcodes/i386-dis.c > +++ b/opcodes/i386-dis.c > @@ -1076,6 +1076,7 @@ enum > PREFIX_0F38F8, > PREFIX_0F38FA, > PREFIX_0F38FB, > + PREFIX_0F38FC, > PREFIX_0F3A0F, > PREFIX_VEX_0F10, > PREFIX_VEX_0F11, > @@ -3620,6 +3621,14 @@ static const struct dis386 prefix_table[][4] =3D { > { MOD_TABLE (MOD_0F38FB_PREFIX_1) }, > }, > > + /* PREFIX_0F38FC */ > + { > + { "aadd", { Mdq, Gdq }, 0 }, > + { "axor", { Mdq, Gdq }, 0 }, > + { "aand", { Mdq, Gdq }, 0 }, > + { "aor", { Mdq, Gdq }, 0 }, > + }, > + > /* PREFIX_0F3A0F */ > { > { Bad_Opcode }, > @@ -4846,7 +4855,7 @@ static const struct dis386 three_byte_table[][256] = =3D { > { MOD_TABLE (MOD_0F38F9) }, > { PREFIX_TABLE (PREFIX_0F38FA) }, > { PREFIX_TABLE (PREFIX_0F38FB) }, > - { Bad_Opcode }, > + { PREFIX_TABLE (PREFIX_0F38FC) }, > { Bad_Opcode }, > { Bad_Opcode }, > { Bad_Opcode }, > diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c > index 6e723681df..60e6d89a29 100644 > --- a/opcodes/i386-gen.c > +++ b/opcodes/i386-gen.c > @@ -259,6 +259,8 @@ static initializer cpu_flag_init[] =3D > "CpuMSRLIST" }, > { "CPU_AVX_NE_CONVERT_FLAGS", > "CPU_AVX2_FLAGS|CpuAVX_NE_CONVERT" }, > + { "CPU_RAO_INT_FLAGS", > + "CpuRAO_INT" }, > { "CPU_IAMCU_FLAGS", > "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" }, > { "CPU_ADX_FLAGS", > @@ -467,6 +469,8 @@ static initializer cpu_flag_init[] =3D > "CpuMSRLIST" }, > { "CPU_ANY_AVX_NE_CONVERT_FLAGS", > "CpuAVX_NE_CONVERT" }, > + { "CPU_ANY_RAO_INT_FLAGS", > + "CpuRAO_INT"}, > }; > > static initializer operand_type_init[] =3D > @@ -673,6 +677,7 @@ static bitfield cpu_flags[] =3D > BITFIELD (CpuWRMSRNS), > BITFIELD (CpuMSRLIST), > BITFIELD (CpuAVX_NE_CONVERT), > + BITFIELD (CpuRAO_INT), > BITFIELD (CpuMWAITX), > BITFIELD (CpuCLZERO), > BITFIELD (CpuOSPKE), > diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h > index 78fc019c3c..b93a402f9f 100644 > --- a/opcodes/i386-opc.h > +++ b/opcodes/i386-opc.h > @@ -223,6 +223,8 @@ enum > CpuMSRLIST, > /* Intel AVX NE CONVERT Instructions support required. */ > CpuAVX_NE_CONVERT, > + /* Intel RAO INT Instructions support required. */ > + CpuRAO_INT, > /* mwaitx instruction required */ > CpuMWAITX, > /* Clzero instruction required */ > @@ -411,6 +413,7 @@ typedef union i386_cpu_flags > unsigned int cpuwrmsrns:1; > unsigned int cpumsrlist:1; > unsigned int cpuavx_ne_convert:1; > + unsigned int cpurao_int:1; > unsigned int cpumwaitx:1; > unsigned int cpuclzero:1; > unsigned int cpuospke:1; > diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl > index 16f59d3476..2c6e424a9a 100644 > --- a/opcodes/i386-opc.tbl > +++ b/opcodes/i386-opc.tbl > @@ -3321,3 +3321,12 @@ rdmsrlist, 0xf20f01c6, None, CpuMSRLIST|Cpu64, No_= bSuf|No_wSuf|No_lSuf|No_sSuf|N > wrmsrlist, 0xf30f01c6, None, CpuMSRLIST|Cpu64, No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, {} > > // MSRLIST instructions end. > + > +// RAO-INT instructions. > + > +aadd, 0xf38fc, None, CpuRAO_INT, Modrm|IgnoreSize|CheckRegSize|No_bSuf|N= o_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Dword|Qword|Unspeci= fied|BaseIndex } > +aand, 0x660f38fc, None, CpuRAO_INT, Modrm|IgnoreSize|CheckRegSize|No_bSu= f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Dword|Qword|Unsp= ecified|BaseIndex } > +aor, 0xf20f38fc, None, CpuRAO_INT, Modrm|IgnoreSize|CheckRegSize|No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Dword|Qword|Unspe= cified|BaseIndex } > +axor, 0xf30f38fc, None, CpuRAO_INT, Modrm|IgnoreSize|CheckRegSize|No_bSu= f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Dword|Qword|Unsp= ecified|BaseIndex }+ > +// RAO-INT instructions end. > -- > 2.27.0 OK. Thanks. --=20 H.J.