From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oi1-x234.google.com (mail-oi1-x234.google.com [IPv6:2607:f8b0:4864:20::234]) by sourceware.org (Postfix) with ESMTPS id D59023858C39 for ; Thu, 1 Dec 2022 16:42:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org D59023858C39 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-oi1-x234.google.com with SMTP id s141so2582303oie.10 for ; Thu, 01 Dec 2022 08:42:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=j+lzvBZ8GFxuDJQqvCvuLAx/KvFMNL2vCuda+TW8jtg=; b=kTrYbPJ2XOoFcHZ7hQXnATJCE/GP+zYnRrK2QL2OHLUPBQswtRkk6vddEb+kaEE/NQ FNWpgjnKVEzmXB0suwAD3DsIV3yhxamlCNX8PVIL7demgiTnhw2/1Uqh2nDfJhRJrCns BdDfKiKvg/by/uODYUUoTmqvA48CA9rBfk7kyWMWWpEc+OfVLeCKYzRfPZYzVkPCMYeV zDtISMOK45s0lVxpMJpcPygiERRdfRFDpE1HLBJTCuoqmUNZ6T75FaQ+oQ308EIuZhg/ HSkEGXu0aCJNFVp3Q7ZUDpzXNJu/y3gkbbBhLGRIE2izPCFbEMfZ7EkY1JcJ2VyhkFmO /pHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=j+lzvBZ8GFxuDJQqvCvuLAx/KvFMNL2vCuda+TW8jtg=; b=tjfighzlfsLADUBRucCljRQUF1Oz1nG8YNWcOPwo1MA5kjCMDBxPTCslVyMDynteH2 p3QOwSx4XfwWUnR3rLQjEbL0ihSj9BjcvFo0ahgFtqr68O8WFMdgqSQB+xgvxc6aHsoY 1riI2Oj6QFq9p8R1xBBDM+FQc2J/vph3z5mKXpNMNSTPSOCQC6v83yga3mDYMs1pMZQZ bMvW7e1U4vD8KjhH/gXtscZKovrd4SyNKA9bXQfZQpcVPtwd7W52v1CzDuXUWgYmy7// gyugEeQwLtbyyaxOmVC+A0PkUqhyRu2T6ElZWUdDEcxFlXS6y1d81TzapdXvm09auJlh qlZA== X-Gm-Message-State: ANoB5pkUYnVNz/4jX1DyvHfUt1gnDFP+E+pSX+w9Y8Y5HroteqjW49ll A7jwx33s8dig70IjqrDc5WsNjk7crwzEUb1LxDMpwvG/ X-Google-Smtp-Source: AA0mqf4g9m1DJYeUWPDEp5mOzJHSWuJpLqAf+kv5Ve16e7xj4IhY0/qCqLqfMW3T+z6GXORY5yUU9lcCjBSBQ+lIlB4= X-Received: by 2002:a05:6808:1309:b0:359:d97b:3f6f with SMTP id y9-20020a056808130900b00359d97b3f6fmr25771154oiv.298.1669912976122; Thu, 01 Dec 2022 08:42:56 -0800 (PST) MIME-Version: 1.0 References: <673753a0-ab7b-6c44-844e-3addfcf01693@suse.com> In-Reply-To: <673753a0-ab7b-6c44-844e-3addfcf01693@suse.com> From: "H.J. Lu" Date: Thu, 1 Dec 2022 08:42:19 -0800 Message-ID: Subject: Re: [PATCH] x86: also use D for XCHG and TEST To: Jan Beulich Cc: Binutils Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-3017.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Thu, Dec 1, 2022 at 1:09 AM Jan Beulich wrote: > > Leverage the C (commutative) attribute to also reduce the number of XCHG > and TEST templates we have. This way the reg <-> r/m (and reg <-> reg for > XCHG) forms can also be folded into a single template each, utilizing D. > > --- a/gas/config/tc-i386.c > +++ b/gas/config/tc-i386.c > @@ -6803,8 +6803,10 @@ match_template (char mnem_suffix) > || (t->base_opcode | 7) != 0x27)) > found_reverse_match = (t->base_opcode & 0xee) != 0x6e > ? Opcode_ExtD : Opcode_SIMD_IntD; > - else > + else if (!t->opcode_modifier.commutative) > found_reverse_match = Opcode_D; > + else > + found_reverse_match = ~0; > } > else > { > @@ -7001,9 +7003,6 @@ match_template (char mnem_suffix) > > i.tm.base_opcode ^= found_reverse_match; > > - i.tm.operand_types[0] = operand_types[i.operands - 1]; > - i.tm.operand_types[i.operands - 1] = operand_types[0]; > - > /* Certain SIMD insns have their load forms specified in the opcode > table, and hence we need to _set_ RegMem instead of clearing it. > We need to avoid setting the bit though on insns like KMOVW. */ > @@ -7011,6 +7010,11 @@ match_template (char mnem_suffix) > = i.tm.opcode_modifier.modrm && i.tm.opcode_modifier.d > && i.tm.operands > 2U - i.tm.opcode_modifier.sse2avx > && !i.tm.opcode_modifier.regmem; > + > + /* Fall through. */ > + case ~0: > + i.tm.operand_types[0] = operand_types[i.operands - 1]; > + i.tm.operand_types[i.operands - 1] = operand_types[0]; > break; > > case Opcode_VexW: > --- a/opcodes/i386-opc.tbl > +++ b/opcodes/i386-opc.tbl > @@ -230,10 +230,8 @@ popa, 0x61, None, Cpu186|CpuNo64, Defaul > // xchg commutes: we allow both operand orders. > > // In the 64bit code, xchg rax, rax is reused for new nop instruction. > -xchg, 0x90, None, 0, CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Acc|Word|Dword|Qword } > -xchg, 0x90, None, 0, CheckRegSize|No_bSuf|No_sSuf, { Acc|Word|Dword|Qword, Reg16|Reg32|Reg64 } > -xchg, 0x86, None, 0, W|CheckRegSize|Modrm|No_sSuf|HLEPrefixAny, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } > -xchg, 0x86, None, 0, W|CheckRegSize|Modrm|No_sSuf|HLEPrefixAny, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } > +xchg, 0x90, None, 0, D|C|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Acc|Word|Dword|Qword } > +xchg, 0x86, None, 0, D|W|C|CheckRegSize|Modrm|No_sSuf|HLEPrefixAny, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } > > // In/out from ports. > in, 0xe4, None, 0, W|No_sSuf|No_qSuf, { Imm8, Acc|Byte|Word|Dword } > @@ -301,8 +299,7 @@ cmp, 0x83, 7, 0, Modrm|No_bSuf|No_sSuf, > cmp, 0x3c, None, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } > cmp, 0x80, 7, 0, W|Modrm|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } > > -test, 0x84, None, 0, W|CheckRegSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|Byte|Word|Dword|Qword|BaseIndex } > -test, 0x84, None, 0, W|CheckRegSize|Modrm|No_sSuf, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } > +test, 0x84, None, 0, D|W|C|CheckRegSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } > test, 0xa8, None, 0, W|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } > test, 0xf6, 0, 0, W|Modrm|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } > OK. Thanks. -- H.J.