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From: "H.J. Lu" <hjl.tools@gmail.com>
Date: Thu, 11 Aug 2022 10:49:58 -0700
Message-ID: <CAMe9rOrRdFkui8UnFv6FYpvh1VzND1rTfXiSQz91DG7Uw0vBSA@mail.gmail.com>
Subject: Re: [PATCH 12/12] x86: shorten certain template names
To: Jan Beulich <jbeulich@suse.com>
Cc: Binutils <binutils@sourceware.org>
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On Fri, Aug 5, 2022 at 5:29 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> Now that we can purge templates, let's use this to improve readability a
> little by shortening a few of their names, making functionally similar
> ones also have identical names in their multiple incarnations.
>
> --- a/opcodes/i386-opc.tbl
> +++ b/opcodes/i386-opc.tbl
> @@ -1051,14 +1051,14 @@ pxor<mmx>, 0x<mmx:pfx>0fef, None, <mmx:c
>  <sse:cpu:attr:scal:vvvv, +
>      $avx:CpuAVX:Vex128|VexW0|SSE2AVX:VexLIG|VexW0|SSE2AVX:VexVVVV, +
>      $sse:CpuSSE::IgnoreSize:>
> -<sse_frel:imm:comm, eq:0:C, lt:1:, le:2:, unord:3:C, neq:4:C, nlt:5:, nl=
e:6:, ord:7:C>
> +<frel:imm:comm, eq:0:C, lt:1:, le:2:, unord:3:C, neq:4:C, nlt:5:, nle:6:=
, ord:7:C>
>
>  addps<sse>, 0x0f58, None, <sse:cpu>, Modrm|<sse:attr>|<sse:vvvv>|No_bSuf=
|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, =
RegXMM }
>  addss<sse>, 0xf30f58, None, <sse:cpu>, Modrm|<sse:scal>|<sse:vvvv>|No_bS=
uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|=
RegXMM, RegXMM }
>  andnps<sse>, 0x0f55, None, <sse:cpu>, Modrm|<sse:attr>|<sse:vvvv>|No_bSu=
f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex,=
 RegXMM }
>  andps<sse>, 0x0f54, None, <sse:cpu>, Modrm|<sse:attr>|<sse:vvvv>|C|No_bS=
uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex=
, RegXMM }
> -cmp<sse_frel>ps<sse>, 0x0fc2, <sse_frel:imm>, <sse:cpu>, Modrm|<sse:attr=
>|<sse:vvvv>|<sse_frel:comm>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS=
uf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
> -cmp<sse_frel>ss<sse>, 0xf30fc2, <sse_frel:imm>, <sse:cpu>, Modrm|<sse:sc=
al>|<sse:vvvv>|<sse_frel:comm>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_l=
dSuf|ImmExt, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM }
> +cmp<frel>ps<sse>, 0x0fc2, <frel:imm>, <sse:cpu>, Modrm|<sse:attr>|<sse:v=
vvv>|<frel:comm>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, {=
 RegXMM|Unspecified|BaseIndex, RegXMM }
> +cmp<frel>ss<sse>, 0xf30fc2, <frel:imm>, <sse:cpu>, Modrm|<sse:scal>|<sse=
:vvvv>|<frel:comm>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt,=
 { RegXMM|Dword|Unspecified|BaseIndex, RegXMM }
>  cmpps<sse>, 0x0fc2, None, <sse:cpu>, Modrm|<sse:attr>|<sse:vvvv>|No_bSuf=
|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseI=
ndex, RegXMM }
>  cmpss<sse>, 0xf30fc2, None, <sse:cpu>, Modrm|<sse:scal>|<sse:vvvv>|No_bS=
uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|Unspecified|Base=
Index|RegXMM, RegXMM }
>  comiss<sse>, 0x0f2f, None, <sse:cpu>, Modrm|<sse:scal>|No_bSuf|No_wSuf|N=
o_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegX=
MM }
> @@ -1151,8 +1151,8 @@ addpd<sse2>, 0x660f58, None, <sse2:cpu>,
>  addsd<sse2>, 0xf20f58, None, <sse2:cpu>, Modrm|<sse2:scal>|<sse2:vvvv>|N=
o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIn=
dex|RegXMM, RegXMM }
>  andnpd<sse2>, 0x660f55, None, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|=
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|Base=
Index, RegXMM }
>  andpd<sse2>, 0x660f54, None, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|C=
|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|Bas=
eIndex, RegXMM }
> -cmp<sse_frel>pd<sse2>, 0x660fc2, <sse_frel:imm>, <sse2:cpu>, Modrm|<sse2=
:attr>|<sse2:vvvv>|<sse_frel:comm>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|=
No_ldSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
> -cmp<sse_frel>sd<sse2>, 0xf20fc2, <sse_frel:imm>, <sse2:cpu>, Modrm|<sse2=
:scal>|<sse2:vvvv>|<sse_frel:comm>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|=
No_ldSuf|ImmExt, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM }
> +cmp<frel>pd<sse2>, 0x660fc2, <frel:imm>, <sse2:cpu>, Modrm|<sse2:attr>|<=
sse2:vvvv>|<frel:comm>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Imm=
Ext, { RegXMM|Unspecified|BaseIndex, RegXMM }
> +cmp<frel>sd<sse2>, 0xf20fc2, <frel:imm>, <sse2:cpu>, Modrm|<sse2:scal>|<=
sse2:vvvv>|<frel:comm>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Imm=
Ext, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM }
>  cmppd<sse2>, 0x660fc2, None, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|N=
o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified=
|BaseIndex, RegXMM }
>  cmpsd<sse2>, 0xf20fc2, None, <sse2:cpu>, Modrm|<sse2:scal>|<sse2:vvvv>|N=
o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Qword|Unspecified|=
BaseIndex|RegXMM, RegXMM }
>  comisd<sse2>, 0x660f2f, None, <sse2:cpu>, Modrm|<sse2:scal>|No_bSuf|No_w=
Suf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM,=
 RegXMM }
> @@ -1227,6 +1227,8 @@ psrldq<sse2>, 0x660f73, 3, <sse2:cpu>, M
>  punpckhqdq<sse2>, 0x660f6d, None, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vv=
vv>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|=
BaseIndex, RegXMM }
>  punpcklqdq<sse2>, 0x660f6c, None, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vv=
vv>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|=
BaseIndex, RegXMM }
>
> +<frel>
> +
>  // SSE3 instructions.
>
>  <sse3:cpu:attr:vvvv, $avx:CpuAVX:Vex128|VexW0|SSE2AVX:VexVVVV, $sse:CpuS=
SE3::>
> @@ -1452,7 +1454,7 @@ gf2p8mulb<gfni>, 0x660f38cf, None, <gfni
>
>  // AVX instructions.
>
> -<avx_frel:imm:comm, eq:00:C, eq_oq:00:C, lt:01:, lt_os:01:, le:02:, le_o=
s:02:, +
> +<frel:imm:comm, eq:00:C, eq_oq:00:C, lt:01:, lt_os:01:, le:02:, le_os:02=
:, +
>      unord:03:C, unord_q:03:C, neq:04:C, neq_uq:04:C, nlt:05:, nlt_us:05:=
, +
>      nle:06:, nle_us:06:, ord:07:C, ord_q:07:C, eq_uq:08:C, +
>      nge:09:, nge_us:09:, ngt:0a:, ngt_us:0a:, false:0b:C, false_oq:0b:C,=
 +
> @@ -1479,8 +1481,8 @@ vblendvp<sd>, 0x664a | <sd:opc>, None, C
>  vbroadcastf128, 0x661a, None, CpuAVX, Modrm|Vex=3D2|Space0F38|VexW=3D1|N=
o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|Base=
Index, RegYMM }
>  vbroadcastsd, 0x6619, None, CpuAVX, Modrm|Vex=3D2|Space0F38|VexW=3D1|Ign=
oreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecifi=
ed|BaseIndex, RegYMM }
>  vbroadcastss, 0x6618, None, CpuAVX, Modrm|Vex|Space0F38|VexW=3D1|IgnoreS=
ize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|B=
aseIndex, RegXMM|RegYMM }
> -vcmp<avx_frel>p<sd>, 0x<sd:ppfx>c2, 0x<avx_frel:imm>, CpuAVX, Modrm|<avx=
_frel:comm>|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf=
|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|Unspecified|BaseIndex, Re=
gXMM|RegYMM, RegXMM|RegYMM }
> -vcmp<avx_frel>s<sd>, 0x<sd:spfx>c2, 0x<avx_frel:imm>, CpuAVX, Modrm|<avx=
_frel:comm>|VexLIG|Space0F|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N=
o_qSuf|No_ldSuf|ImmExt, { RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, R=
egXMM }
> +vcmp<frel>p<sd>, 0x<sd:ppfx>c2, 0x<frel:imm>, CpuAVX, Modrm|<frel:comm>|=
Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_=
qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM,=
 RegXMM|RegYMM }
> +vcmp<frel>s<sd>, 0x<sd:spfx>c2, 0x<frel:imm>, CpuAVX, Modrm|<frel:comm>|=
VexLIG|Space0F|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ld=
Suf|ImmExt, { RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegXMM }
>  vcmpp<sd>, 0x<sd:ppfx>c2, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG=
|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Uns=
pecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
>  vcmps<sd>, 0x<sd:spfx>c2, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|Vex=
WIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, <sd:elem>|Uns=
pecified|BaseIndex|RegXMM, RegXMM, RegXMM }
>  vcomis<sd>, 0x<sd:ppfx>2f, None, CpuAVX, Modrm|VexLIG|Space0F|VexWIG|No_=
bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <sd:elem>|Unspecified|Base=
Index|RegXMM, RegXMM }
> @@ -1834,15 +1836,15 @@ vfnmsubs<sd>, 0x667e | <sd:opc>, None, C
>
>  // XOP instructions
>
> -<xop_elem:opc, b:0, w:1, d:2, q:3>
> -<xop_irel:imm, lt:0, le:1, gt:2, ge:3, eq:4, neq:5, false:6, true:7>
> -<xop_sign:opc, :00, u:20>
> +<xop:opc, b:0, w:1, d:2, q:3>
> +<irel:imm, lt:0, le:1, gt:2, ge:3, eq:4, neq:5, false:6, true:7>
> +<sign:opc, :00, u:20>
>
>  vfrczp<sd>, 0x80 | <sd:opc>, None, CpuXOP, Modrm|SpaceXOP09|VexW0|CheckR=
egSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Unspecified|=
BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
>  vfrczs<sd>, 0x82 | <sd:opc>, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSu=
f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { <sd:elem>|RegXMM|Unspecif=
ied|BaseIndex, RegXMM }
>  vpcmov, 0xa2, None, CpuXOP, D|Modrm|SpaceXOP08|VexSources=3D2|VexVVVV|Ve=
xW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Re=
gXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|Reg=
YMM }
> -vpcom<xop_sign><xop_elem>, 0xcc | 0x<xop_sign:opc> | <xop_elem:opc>, Non=
e, CpuXOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No=
_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM, RegXM=
M }
> -vpcom<xop_irel><xop_sign><xop_elem>, 0xcc | 0x<xop_sign:opc> | <xop_elem=
:opc>, <xop_irel:imm>, CpuXOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|No_bSu=
f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Unspecified|Bas=
eIndex, RegXMM, RegXMM }
> +vpcom<sign><xop>, 0xcc | 0x<sign:opc> | <xop:opc>, None, CpuXOP, Modrm|V=
ex128|SpaceXOP08|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_l=
dSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
> +vpcom<irel><sign><xop>, 0xcc | 0x<sign:opc> | <xop:opc>, <irel:imm>, Cpu=
XOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|=
No_qSuf|No_ldSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
>  vpermil2p<sd>, 0x6648 | <sd:opc>, None, CpuXOP, Modrm|Space0F3A|VexVVVV|=
VexW0|Vex|VexSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS=
uf|No_ldSuf, { Imm8, RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, Re=
gXMM|RegYMM, RegXMM|RegYMM }
>  vpermil2p<sd>, 0x6648 | <sd:opc>, None, CpuXOP, Modrm|Space0F3A|VexVVVV|=
VexW1|Vex|VexSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS=
uf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, Re=
gXMM|RegYMM, RegXMM|RegYMM }
>  vphaddb<dq>, 0xc2 | <dq:opc>, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bS=
uf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseI=
ndex, RegXMM }
> @@ -1869,10 +1871,14 @@ vpmacsww, 0x95, None, CpuXOP, Modrm|Spac
>  vpmadcsswd, 0xa6, None, CpuXOP, Modrm|SpaceXOP08|VexSources=3D2|VexVVVV=
=3D1|VexW=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXM=
M, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
>  vpmadcswd, 0xb6, None, CpuXOP, Modrm|SpaceXOP08|VexSources=3D2|VexVVVV=
=3D1|VexW=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXM=
M, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
>  vpperm, 0xa3, None, CpuXOP, D|Modrm|SpaceXOP08|VexSources=3D2|VexVVVV|Ve=
xW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, RegXMM|=
Unspecified|BaseIndex, RegXMM, RegXMM }
> -vprot<xop_elem>, 0x90 | <xop_elem:opc>, None, CpuXOP, D|Modrm|Vex128|Spa=
ceXOP09|VexW0|VexSources=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qS=
uf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM }
> -vprot<xop_elem>, 0xc0 | <xop_elem:opc>, None, CpuXOP, Modrm|Vex128|Space=
XOP08|VexW0|VexSources=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf=
, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
> -vpsha<xop_elem>, 0x98 | <xop_elem:opc>, None, CpuXOP, D|Modrm|Vex128|Spa=
ceXOP09|VexW0|VexSources=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qS=
uf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM }
> -vpshl<xop_elem>, 0x94 | <xop_elem:opc>, None, CpuXOP, D|Modrm|Vex128|Spa=
ceXOP09|VexW0|VexSources=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qS=
uf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM }
> +vprot<xop>, 0x90 | <xop:opc>, None, CpuXOP, D|Modrm|Vex128|SpaceXOP09|Ve=
xW0|VexSources=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, { RegX=
MM, RegXMM|Unspecified|BaseIndex, RegXMM }
> +vprot<xop>, 0xc0 | <xop:opc>, None, CpuXOP, Modrm|Vex128|SpaceXOP08|VexW=
0|VexSources=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, { Imm8, =
RegXMM|Unspecified|BaseIndex, RegXMM }
> +vpsha<xop>, 0x98 | <xop:opc>, None, CpuXOP, D|Modrm|Vex128|SpaceXOP09|Ve=
xW0|VexSources=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, { RegX=
MM, RegXMM|Unspecified|BaseIndex, RegXMM }
> +vpshl<xop>, 0x94 | <xop:opc>, None, CpuXOP, D|Modrm|Vex128|SpaceXOP09|Ve=
xW0|VexSources=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, { RegX=
MM, RegXMM|Unspecified|BaseIndex, RegXMM }
> +
> +<xop>
> +<irel>
> +<sign>
>
>  // LWP instructions
>
> @@ -2112,10 +2118,10 @@ vbroadcastsd, 0x6619, None, CpuAVX512F,
>  vpbroadcast<dq>, 0x6658 | <dq:opc>, None, CpuAVX512F, Modrm|Masking=3D3|=
Space0F38|<dq:vexw>|Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N=
o_ldSuf, { RegXMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
>  vpbroadcast<dq>, 0x667c, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|<=
dq:vexw64>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <dq:gpr>, Re=
gXMM|RegYMM|RegZMM }
>
> -vcmp<avx_frel>p<sd>, 0x<sd:ppfx>C2, 0x<avx_frel:imm>, CpuAVX512F, Modrm|=
Masking=3D2|Space0F|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|N=
o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, { RegXMM|RegYMM=
|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
> +vcmp<frel>p<sd>, 0x<sd:ppfx>C2, 0x<frel:imm>, CpuAVX512F, Modrm|Masking=
=3D2|Space0F|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|=
No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, { RegXMM|RegYMM|RegZMM=
|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
>  vcmpp<sd>, 0x<sd:ppfx>C2, None, CpuAVX512F, Modrm|Masking=3D2|Space0F|Ve=
xVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf=
|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|<sd:elem>|Unspe=
cified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
>
> -vcmp<avx_frel>s<sd>, 0x<sd:spfx>C2, 0x<avx_frel:imm>, CpuAVX512F, Modrm|=
EVexLIG|Masking=3D2|Space0F|VexVVVV|<sd:vexw>|Disp8MemShift|No_bSuf|No_wSuf=
|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE|ImmExt, { RegXMM|<sd:elem>|Unspecifie=
d|BaseIndex, RegXMM, RegMask }
> +vcmp<frel>s<sd>, 0x<sd:spfx>C2, 0x<frel:imm>, CpuAVX512F, Modrm|EVexLIG|=
Masking=3D2|Space0F|VexVVVV|<sd:vexw>|Disp8MemShift|No_bSuf|No_wSuf|No_lSuf=
|No_sSuf|No_qSuf|No_ldSuf|SAE|ImmExt, { RegXMM|<sd:elem>|Unspecified|BaseIn=
dex, RegXMM, RegMask }
>  vcmps<sd>, 0x<sd:spfx>C2, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D2|Sp=
ace0F|VexVVVV|<sd:vexw>|Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS=
uf|No_ldSuf|SAE, { Imm8, RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, Re=
gMask }
>
>  vcomis<sdh>, 0x<sdh:ppfx>2f, None, <sdh:cpu>, Modrm|EVexLIG|<sdh:spc1>|<=
sdh:vexw>|Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SA=
E, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM }
> @@ -2305,7 +2311,7 @@ vpunpckldq, 0x6662, None, CpuAVX512F, Mo
>  vpunpcklqdq, 0x666c, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=
|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|=
No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXM=
M|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
>  vpxor<dq>, 0x66ef, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV|<=
dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSu=
f|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|B=
aseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
>
> -<avx_irel:imm, eq:0, lt:1, le:2, neq:4, nlt:5, nle:6>
> +<irel:imm, eq:0, lt:1, le:2, neq:4, nlt:5, nle:6>
>
>  vpcmpeqd, 0x6676, None, CpuAVX512F, Modrm|Masking=3D2|Space0F|VexVVVV=3D=
1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_s=
Suf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, R=
egXMM|RegYMM|RegZMM, RegMask }
>  vpcmpeqq, 0x6629, None, CpuAVX512F, Modrm|Masking=3D2|Space0F38|VexVVVV|=
VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N=
o_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM=
|RegYMM|RegZMM, RegMask }
> @@ -2313,8 +2319,8 @@ vpcmpgtd, 0x6666, None, CpuAVX512F, Modr
>  vpcmpgtq, 0x6637, None, CpuAVX512F, Modrm|Masking=3D2|Space0F38|VexVVVV|=
VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N=
o_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM=
|RegYMM|RegZMM, RegMask }
>  vpcmp<dq>, 0x661f, None, CpuAVX512F, Modrm|Masking=3D2|Space0F3A|VexVVVV=
|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_s=
Suf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|Ba=
seIndex, RegXMM|RegYMM|RegZMM, RegMask }
>  vpcmpu<dq>, 0x661e, None, CpuAVX512F, Modrm|Masking=3D2|Space0F3A|VexVVV=
V|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_=
sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|B=
aseIndex, RegXMM|RegYMM|RegZMM, RegMask }
> -vpcmp<avx_irel><dq>, 0x661f, <avx_irel:imm>, CpuAVX512F, Modrm|Masking=
=3D2|Space0F3A|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSu=
f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|<=
dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
> -vpcmp<avx_irel>u<dq>, 0x661e, <avx_irel:imm>, CpuAVX512F, Modrm|Masking=
=3D2|Space0F3A|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSu=
f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|<=
dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
> +vpcmp<irel><dq>, 0x661f, <irel:imm>, CpuAVX512F, Modrm|Masking=3D2|Space=
0F3A|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|=
No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|<dq:elem>|U=
nspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
> +vpcmp<irel>u<dq>, 0x661e, <irel:imm>, CpuAVX512F, Modrm|Masking=3D2|Spac=
e0F3A|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf=
|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|<dq:elem>|=
Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
>
>  vptestm<dq>, 0x6627, None, CpuAVX512F, Modrm|Masking=3D2|Space0F38|VexVV=
VV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No=
_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIn=
dex, RegXMM|RegYMM|RegZMM, RegMask }
>  vptestnm<dq>, 0xf327, None, CpuAVX512F, Modrm|Masking=3D2|Space0F38|VexV=
VVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N=
o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseI=
ndex, RegXMM|RegYMM|RegZMM, RegMask }
> @@ -2661,8 +2667,8 @@ vpcmpeq<bw>, 0x6674 | <bw:opc>, None, Cp
>  vpcmpgt<bw>, 0x6664 | <bw:opc>, None, CpuAVX512BW, Modrm|Masking=3D2|Spa=
ce0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS=
uf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|R=
egYMM|RegZMM, RegMask }
>  vpcmp<bw>, 0x663f, None, CpuAVX512BW, Modrm|Masking=3D2|Space0F3A|VexVVV=
V|<bw:vexw>|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS=
uf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|Reg=
YMM|RegZMM, RegMask }
>  vpcmpu<bw>, 0x663e, None, CpuAVX512BW, Modrm|Masking=3D2|Space0F3A|VexVV=
VV|<bw:vexw>|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_q=
Suf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|Re=
gYMM|RegZMM, RegMask }
> -vpcmp<avx_irel><bw>, 0x663f, <avx_irel:imm>, CpuAVX512BW, Modrm|Masking=
=3D2|Space0F3A|VexVVVV|<bw:vexw>|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|=
No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified=
|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
> -vpcmp<avx_irel>u<bw>, 0x663e, <avx_irel:imm>, CpuAVX512BW, Modrm|Masking=
=3D2|Space0F3A|VexVVVV|<bw:vexw>|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|=
No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified=
|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
> +vpcmp<irel><bw>, 0x663f, <irel:imm>, CpuAVX512BW, Modrm|Masking=3D2|Spac=
e0F3A|VexVVVV|<bw:vexw>|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N=
o_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseInde=
x, RegXMM|RegYMM|RegZMM, RegMask }
> +vpcmp<irel>u<bw>, 0x663e, <irel:imm>, CpuAVX512BW, Modrm|Masking=3D2|Spa=
ce0F3A|VexVVVV|<bw:vexw>|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|=
No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseInd=
ex, RegXMM|RegYMM|RegZMM, RegMask }
>
>  vpslldq, 0x6673, 7, CpuAVX512BW, Modrm|Space0F|VexWIG|VexVVVV=3D2|Disp8S=
hiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm=
8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
>  vpsrldq, 0x6673, 3, CpuAVX512BW, Modrm|Space0F|VexWIG|VexVVVV=3D2|Disp8S=
hiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm=
8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
> @@ -3165,10 +3171,10 @@ vfcmulcsh, 0xf2d7, None, CpuAVX512_FP16,
>  vfmulcph, 0xf3d6, None, CpuAVX512_FP16, Modrm|VexVVVV|Masking=3D3|EVexMa=
p6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|DistinctDest|No_bSuf|No_wSuf|N=
o_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|=
Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
>  vfmulcsh, 0xf3d7, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3D3|EVexMa=
p6|VexVVVV|VexW0|Disp8MemShift=3D2|DistinctDest|No_bSuf|No_wSuf|No_lSuf|No_=
sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIn=
dex, RegXMM, RegXMM }
>
> -vcmp<avx_frel>ph, 0xc2, 0x<avx_frel:imm>, CpuAVX512_FP16, Modrm|Masking=
=3D2|Space0F3A|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No=
_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, { RegXMM|RegYMM|RegZMM|W=
ord|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
> +vcmp<frel>ph, 0xc2, 0x<frel:imm>, CpuAVX512_FP16, Modrm|Masking=3D2|Spac=
e0F3A|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_=
lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspe=
cified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
>  vcmpph, 0xc2, None, CpuAVX512_FP16, Modrm|Masking=3D2|Space0F3A|VexVVVV|=
VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N=
o_qSuf|No_ldSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseInde=
x, RegXMM|RegYMM|RegZMM, RegMask }
>
> -vcmp<avx_frel>sh, 0xf3c2, 0x<avx_frel:imm>, CpuAVX512_FP16, Modrm|EVexLI=
G|Masking=3D2|Space0F3A|VexVVVV|VexW0|Disp8MemShift=3D1|No_bSuf|No_wSuf|No_=
lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, { RegXMM|Word|Unspecified|BaseInd=
ex, RegXMM, RegMask }
> +vcmp<frel>sh, 0xf3c2, 0x<frel:imm>, CpuAVX512_FP16, Modrm|EVexLIG|Maskin=
g=3D2|Space0F3A|VexVVVV|VexW0|Disp8MemShift=3D1|No_bSuf|No_wSuf|No_lSuf|No_=
sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegX=
MM, RegMask }
>  vcmpsh, 0xf3c2, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3D2|Space0F3=
A|VexVVVV|VexW0|Disp8MemShift=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N=
o_ldSuf|SAE, { Imm8, RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegMask }
>
>  vcvtdq2ph<xy>, 0x5b, None, CpuAVX512_FP16|<xy:vl>, Modrm|<xy:attr>|Maski=
ng=3D3|EVexMap5|VexW0|Broadcast|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_=
ldSuf|<xy:sr>, { <xy:src>|Dword, <xy:dst> }
>

OK.

Thanks.

--=20
H.J.