From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 94742 invoked by alias); 17 Feb 2020 15:30:54 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 94570 invoked by uid 89); 17 Feb 2020 15:30:42 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-2.2 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,KAM_NUMSUBJECT,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=no version=3.3.1 spammy=SSE4*, H*f:sk:4f3e523, H*i:sk:4f3e523, flavors X-HELO: mail-ot1-f67.google.com Received: from mail-ot1-f67.google.com (HELO mail-ot1-f67.google.com) (209.85.210.67) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 17 Feb 2020 15:30:39 +0000 Received: by mail-ot1-f67.google.com with SMTP id 66so16423015otd.9 for ; Mon, 17 Feb 2020 07:30:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=HaMjz8PhvQX3aIoV8m0aIEAfsipU36TNYNAmDyxH0DM=; b=FsJxPcXBy7vgB6Boo7Sl/Q80rLUtbBaOXz262fWxDMRKJJk5IbBTvdy9Cl9UOUTpvv eORs415d9P5VI8GV8ZAQMh9diEIGD+rpLK9RheB2qglS05zZA2pWvwl1cNQrFW9InBNb HjCCaHgaJi4RxWNLAJBiV0ZAafIymKofyYaeJxjrloim4UDaZlgSvip+v0UL+BVhPAbe FN+cFPLkqv4SITqc/UXEicRYD1GYwldS86pbfDzA/Un0ulryRn6EeRxfT9PNS8GAnMt0 S3tQ0rO85sbBCVz0eEVrojUGrymzkKVCi1aOnba0Wh7B7I1+oZ16reE9Hh8IPEl2kIob +XkQ== MIME-Version: 1.0 References: <3bc597bb-10f9-80f9-8e00-f28aeb2eea77@suse.com> <4f3e5233-fb2f-a957-2788-8ffde3939ce2@suse.com> In-Reply-To: <4f3e5233-fb2f-a957-2788-8ffde3939ce2@suse.com> From: "H.J. Lu" Date: Mon, 17 Feb 2020 15:30:00 -0000 Message-ID: Subject: Re: [committed, PATCH] x86: Don't disable SSE4a when disabling SSE4 To: Jan Beulich Cc: "binutils@sourceware.org" Content-Type: text/plain; charset="UTF-8" X-IsSubscribed: yes X-SW-Source: 2020-02/txt/msg00395.txt.bz2 On Mon, Feb 17, 2020 at 7:27 AM Jan Beulich wrote: > > On 16.02.2020 17:47, H.J. Lu wrote: > > On Wed, Feb 12, 2020 at 9:18 AM H.J. Lu wrote: > >> > >> On Wed, Feb 12, 2020 at 9:08 AM Jan Beulich wrote: > >>> > >>> Since ".arch sse4a" enables SSE3 and earlier, disabling SSE3 should also > >>> disable SSE4a. And as per its name, ".arch .nosse4" should also do so. > >>> > >>> gas/ > >>> 2020-02-XX Jan Beulich > >>> > >>> * config/tc-i386.c (cpu_noarch): Use CPU_ANY_SSE4_FLAGS in > >>> "nosse4" entry. > >>> > >>> opcodes/ > >>> 2020-02-XX Jan Beulich > >>> > >>> * i386-gen.c (cpu_flag_init): Move CpuSSE4a from > >>> CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add > >>> CPU_ANY_SSE4_FLAGS entry. > >>> * i386-init.h: Re-generate. > >>> > >> > >> OK. > >> > >> Thanks. > > > > commit 7deea9aad8 changed nosse4 to include CpuSSE4a. But AMD SSE4a is > > a superset of SSE3 and Intel SSE4 is a superset of SSSE3. Disable Intel > > SSE4 shouldn't disable AMD SSE4a. This patch restores nosse4. It also > > adds .sse4a and nosse4a. > > And where is it said that "nosse4" means only the Intel flavors? As > said in the commit message of said change, to me the clear implication > is that anything called SSE4* will get disabled. > SSE4 refers to SSE4 from Intel, which includes SSE4.1 and SSE4.2. SSE4a from AMD is unrelated from Intel SSE4. -- H.J.