From: "H.J. Lu" <hjl.tools@gmail.com>
To: Jan Beulich <jbeulich@suse.com>
Cc: Binutils <binutils@sourceware.org>
Subject: Re: x86 ISA v3 / v4 coverage
Date: Thu, 2 Jun 2022 08:29:26 -0700 [thread overview]
Message-ID: <CAMe9rOrZSRGO3zQXGAK_rEwHkRFtJSAGEZe1WC1TDwZLjg-W7A@mail.gmail.com> (raw)
In-Reply-To: <c0960d4f-868c-fc5b-8ed4-eca0e990d822@suse.com>
On Thu, Jun 2, 2022 at 7:31 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> H.J.,
>
> the other day I came to notice two apparent anomalies:
>
> Shouldn't XOP and FMA4 be excluded from v3, just like LWP and TBM are?
Yes, they should be excluded since they don't require v3.
> Shouldn't AVX512_4FMAPS be excluded from v4, just like AVX512_4VNNIW is?
Yes, it should be since it doesn't require v4.
> And is it correct for new ISA additions (like not so long ago AVX512-FP16)
> to become part of what is covered by v3 or v4? AMX, for example, was
AVX512_FP16 requires v4.
> excluded from v3 when it was added to the code base. And e.g. GFNI is not
> part of v2 because there no "umbrella property" (VEX for v3, EVEX for v4)
> is checked, but it's strictly a white-listing of Cpu* flags.
>
> I'm afraid all of this once again is unobvious because the specification
> is not clear enough.
The ISA level is the minimum requirement. All ISAs listed in the level can
be freely used.
--
H.J.
next prev parent reply other threads:[~2022-06-02 15:30 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-02 14:31 Jan Beulich
2022-06-02 15:29 ` H.J. Lu [this message]
2022-06-07 13:13 ` Michael Matz
2022-06-07 21:39 ` H.J. Lu
2022-06-08 11:09 ` Michael Matz
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