From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 22318 invoked by alias); 8 Oct 2013 15:15:36 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 22306 invoked by uid 89); 8 Oct 2013 15:15:35 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=2.8 required=5.0 tests=AWL,BAYES_50,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPAM_SUBJECT,SPF_PASS autolearn=no version=3.3.2 X-HELO: mail-ob0-f171.google.com Received: from mail-ob0-f171.google.com (HELO mail-ob0-f171.google.com) (209.85.214.171) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Tue, 08 Oct 2013 15:15:35 +0000 Received: by mail-ob0-f171.google.com with SMTP id uy5so578577obc.16 for ; Tue, 08 Oct 2013 08:15:33 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.60.68.135 with SMTP id w7mr1630982oet.9.1381245333216; Tue, 08 Oct 2013 08:15:33 -0700 (PDT) Received: by 10.76.110.15 with HTTP; Tue, 8 Oct 2013 08:15:33 -0700 (PDT) In-Reply-To: <525435BC02000078000F9A51@nat28.tlf.novell.com> References: <5254349502000078000F9A3D@nat28.tlf.novell.com> <525435BC02000078000F9A51@nat28.tlf.novell.com> Date: Tue, 08 Oct 2013 15:15:00 -0000 Message-ID: Subject: Re: [PATCH 2/6] x86/MPX: fix address size handling From: "H.J. Lu" To: Jan Beulich Cc: kirill.yukhin@intel.com, Binutils Content-Type: text/plain; charset=ISO-8859-1 X-IsSubscribed: yes X-SW-Source: 2013-10/txt/msg00077.txt.bz2 On Tue, Oct 8, 2013 at 7:41 AM, Jan Beulich wrote: > While address overrides are ignored in 64-bit mode (and hence shouldn't > result in an error), trying to use 16-bit addressing is documented to > result in #UD, and hence the assembler should reject the attempt. > > gas/ > 2013-10-08 Jan Beulich > > * tc-i386.c (md_assemble): Alter address size checking for MPX > instructions. > > --- 2013-10-07/gas/config/tc-i386.c > +++ 2013-10-07/gas/config/tc-i386.c > @@ -3549,10 +3549,15 @@ md_assemble (char *line) > if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok) > as_bad (_("expecting valid branch instruction after `bnd'")); > > - if (i.tm.cpu_flags.bitfield.cpumpx > - && flag_code == CODE_64BIT > - && i.prefix[ADDR_PREFIX]) > - as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions.")); It is done on purpose. When 32-bit address prefix in 64-bit is ignored, MPX doesn't work correctly for x32. > + if (i.tm.cpu_flags.bitfield.cpumpx) > + { > + if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX]) > + as_warn (_("32-bit addressing is ignored in 64-bit MPX instructions")); > + else if (flag_code != CODE_16BIT > + ? i.prefix[ADDR_PREFIX] > + : i.mem_operands && !i.prefix[ADDR_PREFIX]) > + as_bad (_("16-bit addressing isn't allowed in MPX instructions")); > + } > > /* Insert BND prefix. */ > if (add_bnd_prefix > > > -- H.J.